Not Applicable
The present invention relates generally to plastic semiconductor packages, and more particularly, to a semiconductor package adapted for improved radio frequency performance through the integration of one or more transmission line elements.
As is well known in the electrical arts, recently industry trends in wireless communications are driving increased integration, size reduction, and cost reduction. In this regard, many radio frequency (RF) circuits require matching, filtering and biasing networks, which in turn require inductors having relatively high inductance values with low loss. In addition to inductors, many radio frequency circuits require other transmission line elements such as filters, baluns and couplers.
In an attempt to satisfy the need for implementing and integrating inductors into semiconductor packages, there has been developed in the prior art methods for forming inductors in leadframes for semiconductor packages. However, a major drawback associated with currently known leadframe based inductors for semiconductor packages such as RF modules is that such packages are limited to gross lines and pitches, typically on the order of six mil lines on six mil spaces. As a result, the number of inductors or other transmission line elements that can be incorporated into the finished semiconductor package are extremely limited.
The present invention addresses this deficiency by providing a tape based semiconductor package or RF module wherein a two or three layer tape substrate is used in order to increase the density of the components that can be integrated into the semiconductor package. The use of the two or three layer tape allows fine lines and pitches to be utilized in the semiconductor package or RF module design, which in turn allows for the integration into the package of all the transmission line elements that may be desired for the package. In addition to inductors, these transmission line elements include baluns, filters and couplers. As indicated above, because the semiconductor package or RF module of the present invention is tape based, finer lines and pitches can be obtained in comparison to leadframe based semiconductor packages including inductors. In this regard, the tape based semiconductor package or RF module of the present invention typically has one mil lines on one mil spaces, a significant improvement over the aforementioned six mil lines on six mil spaces typically found in comparable leadframe based packages. As also indicated above, because of the fine pitch and spaces inherent in the tape based package of the present invention, many other transmission line elements can be incorporated into the finished package. As such, the present invention provides a cost-effective technique for implementing and integrating inductors and other transmission line elements into semiconductor packages or RF modules. These, as well as other features and advantages of the present invention, will be described in more detail below.
In accordance with the present invention, there is provided a semiconductor package or RF module which is adapted to provide improved radio frequency performance through the integration of one or more transmission line elements. The semiconductor package of the present invention has a tape based construction, which allows for the implementation of the fine pitches and spaces needed to allow for the integration of one or more transmission line elements such as inductors, shortwave couplers, baluns and filters into the semiconductor package. In such tape based construction, metal layers are applied to each of the opposed sides or faces of a non-conductive film, with a subtractive or additive method thereafter being employed to facilitate the formation of leads and transmission line elements upon the film in any one of a variety of different configurations. Thus, the present invention represents a substantial departure from and provides significant advantages over leadframe based inductors for semiconductor packages which, due to their comparatively gross pitches and spaces, provide substantially less design flexibility.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.
These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.
Referring now to the drawings wherein the showings are for purposes of illustrating a preferred embodiment of the present invention only, and not for purposes of limiting the same,
The semiconductor package 10 comprises a tape or film layer 12 which defines a generally planar top surface 14 and an opposed, generally planar bottom surface 16. In this regard, the film layer 12 is a generally planar sheet which is fabricated from a non-conductive material. By way of example, the film layer 12 may be fabricated from a polyimide film having a thickness of approximately 50 microns. Alternatively, the film layer 12 may be formed of a fiber-reinforced epoxy laminate, woven aramid, BT laminate, or other plastic material. As shown in
In addition to the film layer 12, the semiconductor package 10 comprises a plurality of upper leads 20 which are disposed on the top surface 14 of the film layer 12. As best seen in
Disposed on the bottom surface 16 of the film layer 12 are a plurality of lower leads 22. Like the upper leads 20, each of the lower leads 22 is oriented on the bottom surface 16 so as to circumvent a respective one of the vias 18 of the inner and outer sets thereof. As shown in
As best seen in
Referring now to
In addition to the above-described transmission line elements, also formed on the top surface 14 of the film layer 12 are a plurality of conductive traces 32 which are electrically connected to and extend inwardly from certain ones of the upper leads 20. Each of the traces 32 is also fabricated from a conductive metal material such as copper. Though the traces 32 are shown in
Also formed on the top surface 14 of the film layer 12 is a plurality of terminals or pads 34. Each of the pads 34 is electrically connected to a respective one of the upper leads 20 by an elongate conductive trace 36. The pads 34 as shown in
The semiconductor package 10 further includes an integrated circuit device or semiconductor die 38 which is attached to a portion of the top surface 14 of the film layer 12. More particularly, the semiconductor die 38 is attached to a generally quadrangular (i.e., square) portion of the top surface 14 which is defined by portions of the transmission line elements and traces 32. The attachment of the semiconductor die 38 to the top surface 14 of the film layer 12 is preferably accomplished through the use of a layer 40 of a suitable adhesive. As seen in
In the semiconductor package 10, the semiconductor die 38, bond wires 44, transmission line elements, traces 32, 36, pads 34, upper leads 20, and the exposed portions of the top surface 14 of the film layer 12 are covered by a package body 46 of the semiconductor package 10. The package body 46 has a generally square configuration, and defines a generally planar top surface and four generally planar side surfaces. The bottom surface of the package body 46 is predominantly covered by the film layer 12. The package body 46 is typically fabricated from a plastic material (e.g., thermosets) via a molding process. In the completed semiconductor package 10, the outermost, bottom surfaces of the lower leads 22 extend in generally co-planar relation to each other along a plane which is generally parallel to and spaced outwardly from the plane defined by the bottom surface 16 of the film layer 12.
Having thus described the structural attributes of the semiconductor package 10 of the present invention, an exemplary method for fabricating the same will now be described. In the initial step of the fabrication method, an unpatterned, non-conductive sheet is provided which will eventually form the film layer 12. Thus, the non-conductive sheet is fabricated from the same material described above in relation to the film layer 12. The non-conductive sheet is subjected to a drilling process wherein the vias 18 of the outer set and the vias 18 of the inner set (if any) are drilled therein. It is contemplated that a laser will be used to drill the vias 18 into the non-conductive sheet, though alternative drilling methods are contemplated to be within the spirit and scope of the present invention. The completion of the drilling operation upon the non-conductive sheet facilitates the completion of the film layer 12.
In the next step of the fabrication process, the film layer 12 is metalized. More particularly, both the top and bottom surfaces 14, 16 of the film layer 12 are plated with a conductive metal material. Such conductive metal material, which is preferably copper, is also plated to those surfaces of the film layer 12 defining the vias 18. As indicated above, rather than the vias 18 simply being lined with the metal material, the vias 18 may be completely filled therewith. The plating of the top and bottom surfaces 14, 16 of the film layer 12 may be conducted simultaneously, or one at a time. The metal layers may be deposited on the top and bottom surfaces 14, 16 of the film layer 12 using a sputtering or other metal deposition process. Alternatively, the metal layers may comprise metal sheets which are mechanically attached to respective ones of the top and bottom surfaces 14, 16 through the use of an adhesive.
Subsequent to the application of the unpatterned metal layers to each of the top and bottom surfaces 14, 16 of the film layer 12, the metal layer applied to the top surface 14 is patterned to facilitate the formation of the upper leads 20, transmission line elements, traces 32, 36, and pads 34. Similarly, the metal layer applied to the bottom surface 16 of the film layer 12 is patterned to facilitate the formation of the lower leads 22. The patterning of each metal layer is preferably performed through the use of a conventional chemical etching process. In this process, a layer of photoresist is applied to each metal layer. The photoresist is exposed to light and developed, thereby forming a patterned mask of photoresist material on the corresponding metal layer. Next, a liquid etchant is applied, the etchant dissolving the metal that is not protected by the photoresist, thus transferring the photoresist mask pattern to the metal layer. Thereafter, the photoresist mask is removed. This process is a subtractive method in that those portions of each metal layer which do not ultimately form one of the above-described elements are simply etched away, thus exposing the underlying film layer. 12.
It is contemplated that as an alternative to the implementation of this subtractive method, an additive method may be implemented to facilitate the formation of these various elements. In accordance with such additive method, a layer of seed metal is applied to both the top and bottom surfaces 14, 16 of the film layer 12, much in the same manner the metal layers are initially applied thereto in the above-described subtractive method. Subsequent to the deposition of such seed metal, a plate-up process is completed in certain areas of each seed metal layer. More particularly, the plate-up is completed in a manner facilitating the formation of the upper leads 20, transmission line elements, traces 32, 36, pads 34, and lower leads 22. Upon the completion of such plate-up process as completely forms these particular elements, the exposed, remaining area of each seed or base metal layer is removed, thus effectively electrically isolating the plated-up elements from each other.
Subsequent to the formation of the upper and lower leads 20, 22, transmission line elements, traces 32, 36 and pads 34 by either the above-described subtracted method or additive method, each such element is preferably plated. Since each of these elements is preferably fabricated from copper, a typical plating metal for such copper is nickel/gold. In the case of those elements formed on the top surface 14 of the film layer 12 (i.e., the upper leads 20, transmission line elements, traces 32, 36 and pads 34), the nickel/gold plating applied thereto enhances the connection of the bond wires 44 to such elements. In the case of the lower leads 22, the nickel/gold plating applied thereto enhances the ability to electrically connect the lower leads 22 to an underlying substrate such as a printed circuit board through the use of conductive connectors such as solder bumps.
Upon the complete formation of the above-described elements on respective ones of the top and bottom surfaces 14, 16 of the film layer 12, the semiconductor die 38 is attached to the aforementioned exposed portion of the top surface 14 of the film layer 12 through the use of the above-described adhesive layer 40. Thereafter, the bond wires 44 are used to electrically connect respective ones of the terminals 42 included on the top surface of the semiconductor die 38 to one or more of the transmission line elements and traces 32. Subsequent to the electrical connection of the semiconductor die 38 to one or more of the transmission line elements and/or one or more of the traces 32, the aforementioned molding process is implemented to facilitate the formation of the package body 46. The formation of the package body 46 completes the fabrication process associated with the semiconductor package 10.
Numerous variants of the configuration of the semiconductor package 10 shown in
With particular regard to the various transmission line elements which may be integrated into the semiconductor package 10, a hexagonal implementation for the spiral inductor 28 is shown in
This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.
The present application is a continuation-in-part of U.S. application Ser. No. 10/667,759 entitled METHODS OF MAKING THIN INTEGRATED CIRCUIT DEVICE PACKAGES WITH IMPROVED THERMAL PERFORMANCE AND INCREASED I/O DENSITY filed Sep. 22, 2003, which is a continuation-in-part of U.S. application Ser. No. 10/354,772 entitled INTEGRATED CIRCUIT DEVICE PACKAGES AND SUBSTRATES FOR MAKING THE PACKAGES filed Jan. 30, 2003, which is a continuation of U.S. application Ser. No. 09/434,589 entitled INTEGRATED CIRCUIT DEVICE PACKAGES AND SUBSTRATES FOR MAKING THE PACKAGES filed Nov. 5, 1999 and issued as U.S. Pat. No. 6,580,159 on Jun. 17, 2003, the disclosures of which are incorporated herein by reference.
Number | Date | Country | |
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Parent | 09434589 | Nov 1999 | US |
Child | 10354772 | Jan 2003 | US |
Number | Date | Country | |
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Parent | 10667759 | Sep 2003 | US |
Child | 10812274 | Mar 2004 | US |
Parent | 10354772 | Jan 2003 | US |
Child | 10667759 | Sep 2003 | US |