Patent Application
20180294211
Stacking wafers, dies or chips, and the formation of multi-die package with dense interconnection are methods to provide increased density in an electronic system. Such three-dimensional (3D) integrated circuits and dense package interconnections can include chips manufactured via different technologies or processes, without the need to modify the manufacturing process used for each chip. Thermal and physical stresses can result at the connection points between chips in a 3D integrated circuit or dense multi-die packages. As a result, the interface used between such chips is essential to its operation. Probing and testing interfaces, which may be temporary connected to a chip or an integrated circuit, can also be subject to stresses at the connection points. Each chip in the 3D integrated circuit can also have irregularities in shape, making interconnection problematic. Specialization of interconnects can help to alleviate these issues.
Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.
One embodiment includes a substrate, among others, having: a first mechanically flexible interconnect having a first thickness and a second mechanically flexible interconnect having a second thickness. The first thickness and the second thickness are different. The first mechanically flexible interconnect and the second mechanically flexible interconnect have a substantially equivalent compliance.
Another embodiment includes a substrate, among others, having: a first mechanically flexible interconnect comprised of at least one first material and a second mechanically flexible interconnect comprised of at least one second material. At least one of the first material and at least one of the second material are different. The first mechanically flexible interconnect and the second mechanically flexible interconnect have a substantially equivalent compliance.
Yet another embodiment includes a bridge chip for connecting a plurality of chips, the bridge chip being configured to connect a first side of the bridge chip to a first chip via a first plurality of bumps. The bridge chip also connects the first side of the bridge chip to a second chip via a second plurality of bumps. The bridge chip also connects a second side of the bridge chip to a substrate, wherein the first chip is connected to the substrate via a first mechanically flexible interconnect, the second chip is connected to the substrate via a second mechanically flexible interconnect, and wherein the first mechanically flexible interconnect and the second mechanically flexible interconnect have a similar compliance.
A further embodiment includes a method, among others, including: moving a testing interface into a testing position, wherein the testing interface comprises a first mechanically flexible interconnect and a second mechanically flexible interconnect, each of the first mechanically flexible interconnect and the second mechanically flexible interconnect having a similar compliance. The method also comprises contacting the first mechanically flexible interface with a first portion of a circuit. The method also comprises contacting the second mechanically flexible interface with a second portion of the circuit. The method also comprises testing the first portion of the circuit and the second portion of the circuit.
Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
Before the present disclosure is described in greater detail, it is to be understood that this disclosure is not limited to particular embodiments described, and as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present disclosure will be limited only by the appended claims.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range, is encompassed within the disclosure. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges and are also encompassed within the disclosure, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present disclosure, the preferred methods and materials are now described.
As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any of the other several embodiments without departing from the scope or spirit of the present disclosure. Any recited method can be carried out in the order of events recited or in any other order that is logically possible.
Embodiments of the present disclosure will employ, unless otherwise indicated, techniques of microelectronics, electrical engineering, computer engineering, material science, mechanical engineering, and the like, which are within the skill of the art.
The following examples are put forth so as to provide those of ordinary skill in the art with a complete disclosure and description of how to perform the methods and use the probes disclosed and claimed herein. Efforts have been made to ensure accuracy with respect to numbers (e.g., amounts, temperature, etc.), but some errors and deviations should be accounted for. Unless indicated otherwise, parts are parts by volume, temperature is in ° C., and pressure is at or near atmospheric. Standard temperature and pressure are defined as 20° C. and 1 atmosphere.
Before the embodiments of the present disclosure are described in detail, it is to be understood that, unless otherwise indicated, the present disclosure is not limited to particular materials, reagents, manufacturing processes, or the like, as such can vary. It is also to be understood that the terminology used herein is for purposes of describing particular embodiments only, and is not intended to be limiting. It is also possible in the present disclosure that steps can be executed in different sequences where this is logically possible.
It must be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a compound” includes a plurality of compounds. In this specification and in the claims that follow, reference will be made to a number of terms that shall be defined to have the following meanings unless a contrary intention is apparent.
Processes used in integrated circuit fabrication often place a premium on uniformity of features on a substrate. Interconnects for connecting integrated circuits are often made with uniform dimensions and materials so that all interconnects will have similar properties. In order to change the properties of features, such as interconnects, industry solutions focus on changing width while keeping uniform thickness. For example, in modern industry practice a metal layer can have uniform thickness. However, in the field of mechanically deformable interconnects, which have applications in packaging, sockets, wafer probing, connectors, and the like, varying the width alone can be insufficient to maintain a similar mechanical compliance. One example of this is when the distance between two chips, or any surfaces with electrical interface, has a large variance, requiring interconnects of different lengths in order to make contact with different areas on the chips. In this situation, varying the width of the interconnect alone may be insufficient to maintain similar compliance.
One type of interconnect is a mechanically flexible interconnect (MFI). Generally, the present disclosure relates to devices and systems incorporating multiple MFIs having multiple thicknesses and/or multiple materials on the same substrate, while maintaining similar compliance in each. As used herein, the term substrate can refer to substrates, chips, integrated circuits, testing interfaces, wafers, dies, chips, package substrates, flexible substrates, and the like.
Compliance is an important consideration in interconnect design. Compliance refers to how flexible a structure is. It is a measure of the deformation or deflection of an object when a certain force is applied. Compliance of a structure can be measured, for example, in meters per newton, inches per pound, or other appropriate measure. The reciprocal of compliance is stiffness, or the resistance to deformation offered by an object. An object can also have a rotational compliance, indicating the change in angle of the object when a moment is applied, which can be measured in radians per newton-meter, degrees per inch-pound, and the like.
A number of factors can affect compliance of an object, including material, geometry of the object, and other factors. Geometry of the object can affect its compliance in a number of ways. For example, a structure can deflect when a force is applied, and the deflection is related to the geometry of the structure. To best understand this, let us consider a simple uniform beam with a force applied at the top. One way to calculate deflection of such a beam is
where F is the force applied, L is length, E is elastic modulus, and I is moment of inertia.
Generally, a structure of greater length has a greater compliance (will be more flexible), and will have an increased deflection when force is applied, and an object of lesser length will have a lesser compliance (will be more stiff).
Moment of inertia I, which appears in equation (1), can be calculated for a rectangular structure as
Where T is thickness and W is width. Thus geometric factors such as Length, Thickness, and Width can each affect compliance, as well as deflection of a structure when a force is applied. While equations (1) and (2) can be used to illustrate one compliance calculation for a simple structure, an object's specific geometry, such as its shape, dimensions, and connection to other objects, for example, can further affect compliance. Complex or irregular geometries and configurations can have more complex compliance and deflection calculations.
The different lengths of the MFIs can affect compliance or stiffness, as compliance is a property related to structure or geometry of an object. As discussed above, compliance is proportional to length such that a longer object is more compliant. Thus, all other factors being equal (such as material, shape, and the like), MFIs of different lengths can have different compliance, longer MFIs being more compliant than shorter MFIs. While MFIs are often described in terms of length above, the size of an MFI can also be described by its height above the substrate upon which the MFI is formed. An MFI's height, then, can also affect compliance.
MFIs can be manufactured on a single substrate to have a different geometry, material composition, and/or pitch. An MFI can be used as a compliant electrical interconnection between substrates or chips. For example, an MFI can be designed to extend from one chip to make contact with a pad on another chip. The flexible or compliant quality of the MFI allows the MFI to make effective contact with the pad at a range of distances between chips without causing undue stress, allowing for variances such as when the chips are imperfectly or irregularly shaped. While the MFIs are at times referred to as electrical interconnections, an MFI can also be used as a compliant physical interconnection among other uses.
As previously discussed, two or more substrates can be interfaced or connected in an electronic system, or a substrate can be temporarily connected to an integrated circuit for testing. To illustrate, a testing interface comprising a substrate can have a number of probes (interconnects) extending from the bottom of a substrate. To electrically connect the testing interface to an integrated circuit, the probes can be pressed against an integrated circuit having contact pads on the top of the integrated circuit. Assuming that the substrate and the integrated circuit are each perfectly flat, and each probe is exactly the same length, then all of the probes will make contact with the contact pads concurrently. The forces resulting from the connection will be equally distributed on each probe of the testing interface, and the forces on the integrated circuit will also be evenly distributed at each contact pad.
However, if one of the probes is longer than the other probes, and the probes are very stiff (not compliant), then the long probe will make contact first, and stress on the testing interface and/or the integrated circuit can result if all probes are forced to make contact with all contact pads in this situation. This is merely one way to illustrate potential stresses that can occur when connecting two substrates. Similar stresses can result, for example, if any portion of the testing interface, the probes, the contact pads, or the integrated circuit is imperfectly formed, or has minor variances, for example in size, shape, placement, composition, and the like. Mechanically flexible interconnects can help alleviate stresses caused by such imperfections or variances. In the above illustration, if the longer probe is an MFI, then at least some of the stress can be alleviated as the compliance of the longer MFI probe will flex as it makes contact with the contact pad, decreasing the stress on the integrated circuit and the testing interface.
Additionally, in the above illustration, if each of the probes of the testing interface are MFIs, they can each flex when each MFI makes contact with each corresponding contact pad of the testing interface. This would alleviate some of the stress on the integrated circuit and the testing interface as they are pressed together, even if all of the MFIs are the same length. All of the MFIs can also have similar compliance. If some of the MFIs have different compliance than other MFIs, the integrated circuit and the testing interface can be unduly stressed.
Integrated circuits, package substrates, motherboard substrates, and the like, can have irregular shapes. For example, while the substrate and the integrated circuit in the above illustration are described as being generally flat, in other situations, each may instead not be flat, causing the distance between the substrate and the integrated circuit to vary. Further, a substrate may have pads on different levels (i.e., different planes, such that a set of pads is higher than the other set). This would require MFIs of different lengths in order to make proper contact.
In another example, the top of a substrate can be flat, but a chip might be affixed to the top of the substrate such that the top of the chip is higher than the top of the substrate. If contact pads on the top of the substrate and the top of the chip are to be tested by a single, flat testing interface, MFIs (probes) extending from the testing interface can have different lengths to accommodate the contact pads on the top of the substrate and the top of the chip concurrently. In such a situation, varying the width of the MFIs alone in order to give each MFI a similar compliance may be impractical or impossible.
Geometry of an MFI can affect its compliance such that an increase in the thickness of an MFI decreases the compliance of the MFI. This application discloses multiple MFIs incorporating different geometries, such as different shapes, thicknesses, widths, and multiple materials, that can be made at various pitches on the same substrate. The MFIs can be designed to have a similar compliance. MFIs utilized on a chip, substrate, and the like, can have similar compliance, which is a design characteristic that can be chosen or selected to fit a particular purpose. A first plurality of MFIs utilized together can have a first compliance for one purpose, while a second plurality of MFIs utilized together can have a second compliance for another purpose. In an embodiment, the compliance can be about 1 μm/mN to about 20 μm/mN.
The MFIs can be incorporated on one or both sides of a substrate embodying a wafer, die, chip, package substrate, flexible substrate, and the like. A substrate can be silicon, glass, ceramic, organic, flexible polymeric, or other material, and can be incorporated into an integrated circuit. A substrate can also have additional features including but not limited to bumps of various pitches and sizes, vias, optical vias, optical waveguides, and the like that are formed on the same substrate as the MFIs. For example, electrical or physical connections can be made with bumps of various pitches of about 10 μm to about 2,000 μm and can include a variety of solder compositions or alloys such as tin-based solder. Bumps can also include copper bonding, gold-to-gold thermo-compression bonding, polymer bonding, epoxy bonding, and the like. Conductive pillars, for example, copper pillars or columns, can also be utilized in bumps or alone.
A substrate can have a number of planes on a single side of the substrate. For example, a trench can be dug in the substrate, or the surface of a substrate can be otherwise removed creating more than one plane on a single side. MFIs on a plane or surface of the substrate can have differing lengths, heights, thicknesses and/or widths, as well as different shapes and/or geometries. For example, MFI heights from a surface can be about 5 μm to about 200 μm, thicknesses can be about 2 μm to about 15 μm, and widths can be about 1 μm to about 100 μm. Where substrates are stacked in a 3D integrated circuit, bumps can be integrated adjacent to MFIs in order to securely hold the structure together. A glue-like polymer or an epoxy can also be used locally in certain positions on the chips.
Turning to the figures,
Referring to
Next, referring to
The first outer layer 207 envelops the core layer 205. The first outer material 207 can be made by electroplating over the core layer 205 while nothing is under the core later 205 and can be chosen to have a higher yield strength, a lower compliance, or both. One example of a high yield strength material is NiW. In other embodiments, the first outer layer may not be selected for its conductivity, and may be selected for other properties.
The second outer layer 209 envelops the first outer material 207, and can be made via electroplating, passivation, and the like. The second outer material 209 can similarly be chosen for its properties. There may also be additional layers of additional materials on the MFI 203. Each layer in the MFI 203 can be made via electroplating, passivation, or other process, and each layer can have a different thickness. In some situations, the outermost layer of an MFI can be gold or other conductive, non-corrosive material. In other embodiments, the outermost layer may be selected for other properties. As used herein, a layer can be a few molecular layers to about 15 μm thick, and can completely or partially cover a surface, and can have an evenly or unevenly distributed thickness.
Much like the MFI 203, the MFI 213 is made of a core layer 215, a first outer layer 217, and a second outer layer 219. Each of the layers 215, 217, and 219 are different materials, but in other embodiments they may be layers of the same material. The core layer 215 of the MFI 213 is shown as having a different material and different thickness from the core layer 205 of the MFI 203. In other embodiments, they may have the same or different material and thickness. The first outer layer 217 envelops the core layer 215 of the MFI 213. The first outer layer 217 is shown as a different material from the first outer layer 207, but in other embodiments each can have the same or different material and thickness. The second outer layer 219 envelops the first outer layer 217. As shown, the second outer layer 219 is the same as the second outer layer 209, but in other embodiments each can have the same or different material and thickness. There may also be additional layers of additional materials on the MFI 213, each layer having its own thickness. This can be achieved, for example, by electroplating a layer on one MFI while the other MFI is protected, for example, by covering it with a layer of photoresist.
While each layer in the MFI 203 and the MFI 213 can have its own material, geometry, length, width, and thickness, the MFI 203 and the MFI 213 can be designed to have a similar compliance once fully formed. In this way, the MFIs can be customizable to fit the application local to their probing or interconnection location while minimizing stresses involved with interconnections as discussed. This enables fine-grain customization of the flexible interconnects on the same wafer, die, package substrate, or motherboard.
Moving to
In one example, the MFI 223 can be made by electroplating the core layer 225 on a seed layer on the surface of a curved shape of photoresist. The outer layer 227 can be made by electroplating on the core layer 225 while the photoresist remains under the core layer 225, completing the MFI 223.
The MFI 233 can be made using a similar process for the core layer 235 as the core layer 225, and a similar process for the outer layers. While not shown, each of the MFIs 223 and 233 can have a number of additional layers that envelop the MFIs 223 and 233.
Further MFIs can be formed having a wide variety of geometries with different side views and top views. In some embodiments, an MFI can have a multi-pronged tip. Similarly, the photoresist upon which the MFIs can be formed can have a wide variety of side views and top views.
The photoresist mound 405 can be made in a number of ways. For example, a layer of photoresist can be formed on the substrate by spin coating. The spin coating can be exposed to a pattern of light and developed, leaving a shape of photoresist that can be reflowed to make the mound 405. Alternatively, the mound 405 can be formed by injection molding, stamping, 3D printing, or other techniques.
The photoresist mounds 406 and 407 can similarly be made in a number of ways. For example, mounds 406 and 407 can be formed, much like the mound 405, by exposing a spin coating to a pattern of light, developing, and reflowing the remaining shapes. In another example, a spin coated layer of photoresist can be formed on the substrate. The spin coating can be exposed to a first pattern of light and can be developed a first time, leaving a single shape of photoresist that can be reflowed to appear much like the mound 405. The reflowed shape can be exposed to a second pattern of light and can be developed a second time, leaving two smaller shapes. These smaller shapes can then be reflowed to make mounds 406 and 407. Alternatively, the mounds 406 and 407 can be formed by injection molding, stamping, 3D printing, or other techniques. The mounds 405, 406, and 407 can each be made using the same or different techniques or processes, for example the mound 405 may be made using an exposure, development, and reflow method while the mound 406 is 3D printed, and the mound 407 is injection molded, and the like.
The MFIs 415, 416, and 417 can be formed by electroplating or other metallization techniques. Metallization may require a seed layer (not shown) to facilitate electroplating. In this example, the seed layer can be formed on the surface of the substrate 403, the mounds 405, 406, and 407 before the photoresist 409 is applied. When the photoresist 409 is patterned using the mask 411, the seed layer can be exposed for metallization. A first metallization for a first duration forms the MFI 415 and the MFIs 417.
MFIs can also be transferred from one substrate to another substrate. For example, a solder ball can be placed at the tip of the MFI 415. Another substrate can, for example, be lowered from above and connected to the solder ball on the tip of the MFI 415. Once the MFI 415 is attached to the other substrate, the MFI 415 can be transferred to the other substrate by detaching the MFI 415 from the substrate 403.
Since the chip 512 is on top of the substrate 506, the distance between the substrate 503 and the substrate 506 is greater than the distance between the substrate 503 and the chip 512. As a result, the MFIs 521 must be longer than the MFIs 524 in order to make even contact. As discussed earlier, however, the MFIs 521 and the MFIs 524 can have a similar compliance in order to reduce the stress of interconnection and to enable substantially equivalent contacting force. To this end, the MFIs 521 and the MFIs 524 can have a different thickness and/or comprise a different material or materials.
The large bumps 509 are located at the edges of the integrated circuit 501 and provide a solid physical connection that keeps the MFIs 521 and the MFIs 524 of the substrate 503 connected to contact pads on the substrate 506 and the chip 512, respectively. Note that adhesive polymeric materials can also be used.
MFIs 545 and MFIs 548 extend from the substrate 535 to connect to contact pads on the substrate 533. The substrate 535 has two planes, so the MFIs 545 must be long than the MFIs 548 in order to make even contact to the contact pads of the substrate 533. The MFIs 545 and the MFIs 548 can have a similar compliance in order to reduce the stress of interconnection and can have a different thickness and/or comprise different material or materials. A solid physical connection between the substrate 533 and the substrate 535 is made using a combination of the large bump 539 and the connection through the chip 537 (and the bumps 541 and 543).
The integrated circuit 602 has a substrate 612 with a number of contact pads 621 on a top surface of the substrate 612. A MEMS chip 615 and an ASIC chip 618 are also on the top surface of the substrate 612. The MFIs 605, 607, and 609 each have different lengths or heights measured from the substrate, to accommodate the MEMS chip 615, the ASIC chip 618, and the contact pads 621 of the integrated circuit 602. The MFIs 605, 607, and 609 can also have different thicknesses and/or comprise a different material or materials so each has an appropriate compliance for connection to the MEMS chip 615, the ASIC chip 618, and the contact pads 621 of the integrated circuit 602, respectively.
The temporary testing interface 601 may not be permanently connected to the integrated circuit 602. Instead, the temporary testing interface 601 can be held in place temporarily, or can, for example, be raised/lowered into a position to make connection between the MFIs 605, 607, and 609 and the integrated circuit 602 for testing or other purposes.
The MFIs 705 extend from the substrate 712 to make contact with the chip 715. The MFIs 708 extend from the substrate 712 to make contact with the chip 718. The MFIs 705 and the MFIs 708 can have a similar compliance in order to reduce the stress of interconnection and can have a different thickness and/or comprise different material or materials. The bridge chip can use fine-pitch bumps 721 for electrical and physical connections. The fine-pitch bumps 721 can be used in a variety of situations such as when the required pitch, or the number of required connections, is impractical for MFIs. MFIs can still be utilized for other connections, however. A solid physical connection between the substrate 712 and each of the chip 715 and the chip 718 is made using a combination of large bumps 724 and the bridge chip 703.
In
In some embodiments, the supports 911 and 913 can be connected to the substrate 903 before the photoresist mounds 905 and 907 are formed, and the MFIs 915 and 917 can be formed on the surface of the photoresist mounds 905 and 907, respectively, thereafter. In other embodiments, the supports 911 and 913 can be formed, for example, by masking, exposing, and developing those areas of the photoresist 905, and 907, forming a seed layer and performing metallization. In some embodiments, the metallization of the supports 911 and 913 can be performed before the MFIs 915 and 917 are formed. In further embodiments, the supports 911 and 913 can be formed concurrently with the MFIs 915 and 917. The MFIs 915 and 917 can act as a spring, allowing the pogo pin 920 to move, and allowing for compliant connections using the pogo pin 920.
It should be noted that ratios, concentrations, amounts, dimensions, and other numerical data may be expressed herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a concentration range of “about 0.1% to about 5%” should be interpreted to include not only the explicitly recited concentration of about 0.1 wt % to about 5 wt %, but also include individual concentrations (e.g., 1%, 2%, 3%, and 4%) and the sub-ranges (e.g., 0.5%, 1.1%, 2.2%, 3.3%, and 4.4%) within the indicated range. In an embodiment, the term “about” can include traditional rounding according to significant figures of the numerical value. In addition, the phrase “about ‘x’ to ‘y’” includes “about ‘x’ to about ‘y’”.
As used herein, the terms “similar compliance” and “substantially equivalent compliance” can refer to compliance that differs about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, or about 5% or less. As used herein, the terms “similar contacting force” and “substantially equivalent contacting force” can refer to contacting force that differs about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, or about 5% or less. The term “or less” can extend to 0 or to 0.01.
It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations, and are set forth only for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiments of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.
This application claims priority to the following copending U.S. provisional applications: provisional application entitled, “Single and Dual-Sided Substrates with Flexible Interconnects of Differing Sizes,” having Ser. No. 62/155,960, filed May 1, 2015; provisional application entitled, “Mechanical Interconnects,” having Ser. No. 62/255,935, filed Nov. 16, 2015; and provisional application entitled, “Mechanically Flexible Interconnects for Large Scale Heterogeneous System Integration,” having Ser. No. 62/306,307, filed Mar. 10, 2016. Each of the above applications are entirely incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US16/29799 | 4/28/2016 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62155960 | May 2015 | US | |
| 62255935 | Nov 2015 | US | |
| 62306307 | Mar 2016 | US |
