Patent Application
20180242455
The present invention relates generally to semiconductor modules and methods for packaging the same and, more particularly, to semiconductor modules that incorporate three dimensional stacking of devices.
Electronic modules generally include active integrated circuits (ICs) and associated analog circuitry situated and interconnected on a main substrate board. One or more metallization layers on the substrate board provide conductive traces that interconnect the various electronic devices making up the module. The current technology for “system in package” modules combines active devices (e.g., CMOS devices formed in silicon) with discrete surface mount passive components (e.g., capacitors, inductors and resistors) in a two dimensional planar geometry on a substrate board, to provide a module with a given electrical function. Generally, the active devices are located near the center of the board, while the passive components are located around the edges of the board.
For many applications, including cellular handset and other wireless/mobile applications, it is important that the size of the main substrate board be as small as possible. One factor requiring reductions in the size of the board is the physical dimension of an associated product which makes use of the board (e.g., a cellular handset or MP3 player). Therefore, higher density modules are desirable to pack more functionality into less space. Accordingly, it becomes crucial to configure and package the individual module devices so that the surface area of the substrate board is optimized.
There have been several attempts to address the problem of adding increased functionality to substrate boards with limited space. Many of these include methods of packaging devices, including integrated circuits, in a vertical, or three-dimensional, geometry. For example, thin film technology has been used to stack one active die on top of another, particularly to create high density memory devices. A thin film of adhesive is disposed over the lower die to act as a spacer and allow another die to be stacked on top of, and secured to, the lower die. The adhesive is thermally sensitive such that it can be heated and applied over the lower die in liquid form so as not to bend the bond wires that connect the lower die to the substrate board. This process allows stacking of multiple, similar, active devices, for example, stacking of memory ICs with other application specific integrated circuits (ASICs).
In another example, where a great number of passive devices are required in a high density circuit, active devices have been stacked over integrated passive devices. The term “integrated passive device” as used herein refers to a passive device that is integrally formed with a substrate, such as a printed circuit board. Integrated passive devices are created using semiconductor processing techniques, such as dielectric film and metal deposition (e.g., silicon on insulator and/or thin-film technology). Active devices can then be disposed on substrates that incorporate integrated passive devices, resulting in stacking of the active devices above the integrated passive devices. This approach is often presently preferred because stacking similar device technologies, for example, a CMOS ASIC with a CMOS passive network, uses processes that are already used for stacking multiple active devices (e.g., stacking memory ICs with ASICs), as discussed above. One such example that combines integrated passive devices with active ICs is described in U.S. Pat. No. 5,670,824 to Weinberg, entitled “Vertically integrated device assembly incorporating active and passive components” which discloses an electronic assembly formed as a multi-layered structure having integrated passive devices disposed on a substrate layer.
Although conventional methods of stacking of active devices over one another or over integrated passive devices provide some increase in board density and/or some reduction in substrate size, neither solution is ideal. Stacking of active devices over one another does not reduce the space required by passive devices in the module, which can be a large percentage of the total substrate surface area. As discussed further below, integrated passive devices are expensive and time-consuming to manufacture compared to surface mount passive devices. Therefore, although stacking of active devices over integrated passive devices can result in higher density circuit boards, the use of integrated passive devices can be undesirable, particularly for low cost, high volume applications.
Accordingly, to address these and other disadvantages present in the prior art, aspects and embodiments of the present invention are directed to electronic modules that incorporate stacking of active devices over surface mount passive devices.
One embodiment of a semiconductor packaged module comprises a substrate having first and second conductive traces disposed thereon, at least one passive surface mount component having an upper surface and a lower surface, at least a portion of the lower surface being connected to the first conductive trace, and an active device adhered to the upper surface of the at least one passive surface mount component by an adhesive. In one example, the adhesive is an epoxy paste. The adhesive may be conductive or non-conductive. In one example, the at least one passive surface mount component comprises a body and a connection terminal, the connection terminal being electrically connected to the first conductive trace. In this example, the adhesive may be conductive and disposed between a selected portion of the active device and the upper surface of the connection terminal. In another example, a wire bond is used to electrically connect the active device to the second conductive trace. Molding compound may be used to encapsulate the active device.
According to another embodiment, a method of packaging a semiconductor module comprises connecting a passive surface mount component to a substrate, and mounting an active device on top of the passive surface mount component. In one example, mounting the active device includes adhering the active device to the passive surface mount component using an adhesive. In one example, adhering the active device to the passive surface mount component includes disposing a layer of adhesive on a surface of the active device and mounting the active device to the passive surface mount component such that the adhesive is interposed between the active device and the passive surface mount component. In another example, adhering the active device to the passive surface mount component includes disposing a conductive adhesive on a connection terminal of the passive surface mount component, aligning a connection pad on the active device with the connection terminal of the passive surface mount component, and bonding and electrically connecting the connection pad to the connection terminal with the conductive adhesive. The method may further comprise encapsulating the active device with a molding compound. In another example, the method includes connecting a plurality of passive surface mount components to the substrate, and mounting the active device may include disposing a layer of adhesive on the active device, and mounting the active device on top of the plurality of passive surface mount components with the layer of adhesive interposed between the plurality of passive surface mount components and the active device. The method may further comprise curing the layer of adhesive to bond the active device to the plurality of passive surface mount components.
Still other aspects, embodiments, and advantages of these exemplary aspects and embodiments, are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. The accompanying drawings are included to provide illustration and a further understanding of the various aspects and embodiments, and are incorporated in and constitute a part of this specification. The drawings, together with the remainder of the specification, serve to explain principles and operations of the described and claimed aspects and embodiments.
Various aspects of at least one embodiment are discussed below with reference to the accompanying figures. In the figures, which are not intended to be drawn to scale, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The figures are provided for the purposes of illustration and explanation and are not intended as a definition of the limits of the invention. In the figures:
As discussed above, in order to accommodate the growing demand for smaller and more complex electronic devices, designers have moved toward electronic modules that incorporate vertically stacked devices in a three-dimensional (3-D) geometry. Conventionally, for 3-D modules that comprise many passive devices, the tendency has been to stack active integrated circuits (ICs) over integrated passive devices. These integrated passive devices are formed using semiconductor fabrication technologies (e.g., silicon-on-insulator technology, thin-film technology, etc.) and are incorporated into the module during die fabrication and assembly, which typically occurs in a clean room environment.
Although the use of integrated passive devices allows some increase in the effective surface area of the substrate board (by enabling vertical stacking of active ICs above the integrated passive devices), there are several disadvantages associated with it. For example, integrated passive devices are formed and assembled on the substrate board with the active dies, using high technology semiconductor processes. These processes, such as semiconductor doping, masking, etching, metal deposition, oxidation, etc. are relatively slow and expensive processes, and generally must be performed in a clean room environment. Maintaining a clean room can also be relatively expensive. In addition, because integrated passive devices are integrally formed with the die, adding additional devices to a module or replacing defective devices can be difficult and expensive.
By contrast, surface mount passive components are discrete devices, separate from the active dies, generally comprising a ceramic body with solderable terminals for attaching the surface mount passive component to the substrate board. Some common examples of surface mount passive components include resistors, inductors and capacitors. Surface mount components are generally positioned on the substrate board and attached using soldering techniques (e.g., wave or reflow soldering) either before or after die assembly is complete. Assembly machines are capable of placing surface mount components on a substrate at a rate of up to about 50,000 components per hour. In addition, placement and soldering of surface mount passive components are generally part of the printed circuit board assembly, rather than the active die assembly, and do not need to occur in a clean room. Thus, in many instances, the use of surface mount passive components is desirable, particularly for low cost, high volume applications.
Accordingly, aspects and embodiments are directed to packaged multi-die modules, and methods of assembly thereof, that incorporate stacking of active devices over internal discrete surface mount passive components. Such three-dimensional stacking of active ICs over surface mount passive components can reduce the size of the substrate for a given package and/or can increase the device density for a given substrate surface area. This allows module designers to achieve the same or greater functionality in a smaller package form factor. In addition, packaged three-dimensional modules according to aspects of the invention can be assembled using high speed assembly processes and low cost surface mount components, and may also allow improved design flexibility, as discussed further below.
It is to be appreciated that embodiments of the methods and apparatuses discussed herein are not limited in application to the details of construction and the arrangement of devices set forth in the following description or illustrated in the accompanying drawings. The methods and apparatuses are capable of implementation in other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, elements and features discussed in connection with any one or more embodiments are not intended to be excluded from a similar role in any other embodiments. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use herein of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Referring to
In a first step 100, a substrate or carrier is prepared for assembly. Referring to
In a next step 102, one or more passive surface mount components may be assembled onto the substrate 202.
Furthermore, it is to be appreciated that two or more surface mount passive components may be combined into a single surface mount device. For example, a bank of several capacitors or resistors may be supplied as a single surface mount device. Therefore, the term “passive surface mount component” as used herein is intended to refer to both single component devices and multi-component devices.
Referring again to
According to another embodiment, the layer of adhesive film or paste may be applied to the tops of at least some of the passive surface mount components 206. As discussed above, the adhesive film or paste may be non-conductive, in which case it may be applied over the body 218 or and/or connection terminals 220 of the passive surface mount component(s) 206. It is to be appreciated that numerous variations on the adhesive layer 210 are possible. For example, in some instances where the adhesive layer is a non-conductive adhesive film, it may have a substantially uniform appearance, as illustrated in
As discussed above, in another example, the adhesive may be conductive and may be used not only to adhere the active die 212 to the array of passive surface mount components 206, but also to form an electrical connection between selected ones of the passive surface mount components 206 and the die 212. Referring to
In one example, the active die 212 may be formed on a wafer that comprises multiple dies, as known in the art. Therefore, according to one embodiment, a layer of adhesive may be applied over one side of the wafer, which may then be singulated into the individual dies (step 106). The die(s) are then mounted to the top of the array of passive surface mount components, as discussed above. In another example, the substrate 202 is a carrier wafer upon which multiple module layouts are arranged. In this example, the step 106 includes singulating the carrier wafer into multiple individual substrates to provide corresponding multiple individual modules. It is to be appreciated that although the flow diagram in
Referring again to
It is to be appreciated that although a single-die module 200 is illustrated in
Thus, methods and apparatus according to aspects and embodiments of the invention may be used to provide single- or multi-die packaged modules that allow three-dimensional integration of active devices with standard, widely available, low cost, discrete passive devices in lieu of using integrated passive devices that tend to be more expensive and require longer development and manufacturing cycle times. In addition, by creating a package structure that allows active devices (such as, a silicon controller or gallium-arsenide switch, etc.) to share the same footprint area as the array of passive surface mount components, the package footprints can be reduced.
Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure and are intended to be within the scope of the invention. Accordingly, the foregoing description and drawings are by way of example only, and the scope of the invention should be determined from proper construction of the appended claims, and their equivalents.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.
The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.
While some implementations of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
This application is a continuation of U.S. application Ser. No. 12/107,890 filed Apr. 23, 2008, entitled 3-D STACKING OF ACTIVE DEVICES OVER PASSIVE DEVICES, the disclosure of which is hereby expressly incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12107890 | Apr 2008 | US |
| Child | 15961859 | US |
