BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a sectional diagram of a semiconductor package structure with several chips stacked therein.
FIG. 2 is a diagram of a conventional circuit board structure with semiconductor component embedded therein;
FIGS. 3A to 3D are sectional diagrams of a circuit board structure having passive component according to a first embodiment of the present invention; and
FIG. 4 is a sectional diagram of a circuit board structure having passive component according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be made without departing from the spirit of the present invention.
First Embodiment
FIGS. 3A to 3D show a fabrication process of a circuit board structure having a passive component according to a first embodiment of the present invention.
As shown in FIG. 3A, a carrier board 11 formed with at least one through opening 110 is provided. The carrier board 11 may be a metal board, a dielectric board, or a circuit board having circuits thereon. A semiconductor component 12 having an active surface 12a is received in the through opening 110, wherein the active surface 12a of the semiconductor component 12 has a plurality of electrode pads 121 formed thereon. The semiconductor component 12 can be an active component such as a CPU, a DRAM, a SRAM or a SDRAM. An adhesive layer 112 is formed on one surface of the carrier board 11 that is opposite to the active surface 12a of the semiconductor component 12, and the adhesive layer 112 is used to fill in gaps between the opening 110 and the semiconductor component 12 for securing in position the semiconductor component 12 in the opening.
Referring to FIG. 3B, a dielectric layer 13 is formed on the carrier board 11 and the active surface 12a of the semiconductor component 12, and a plurality of openings 130 is formed in the dielectric layer 13 for exposing the electrode pads 121 of the semiconductor component 12. The dielectric layer 13 may be made of an epoxy resin, polyimide, cyanate ester, glass fiber, bismaleimide triazine (BT) or glass fiber-epoxy resin composites.
Referring to FIG. 3C, a circuit layer 14 is formed on the dielectric layer 13 and a plurality of conductive structures 141 are formed in the openings 130 of the dielectric layer 13 for electrically connecting the electrode pads 121 of the semiconductor component 12. In addition, the circuit layer 14 has a plurality of lands 142 to which at least one passive component 15 can be mounted such that the passive component 15 can be electrically connected with the circuit layer 14 through the lands 142. The passive component can be such as a capacitor, a resistor or an inductor.
The resistor may be formed by dispersing silver powder or carbon particles in resin, or dispersing RuO2 and glass particles in a binder and then coating and curing, or filling such as Ni—Cr, Ni—P, Ni—Sn, Cr—Al, or TaN alloys in the passive component region. The capacitor is a high dielectric layer having big dielectric constant, which may be made of a high polymer material, a ceramic material, high polymer with dispersed ceramic particles or the like, such as barium-titanate, lead-zirconate-titanate, amorphous hydrogenated carbon or powders thereof dispersed in a binder.
Referring to FIG. 3D, a circuit build-up structure 16 is formed on the dielectric layer 13, the circuit layer 14 and the passive component 15. The circuit build-up structure 16 comprises a dielectric layer 161, a circuit layer 162 stacked on the dielectric layer 161, and a plurality of conductive structures 163 formed in the dielectric layer 161 and electrically connected with the circuit layer 14. Moreover, a plurality of electrically connecting pads 164 are formed on the circuit build-up structure 16. Further, a solder mask layer 17 is formed on the circuit build-up structure 16, and the solder mask layer 17 is formed with a plurality of openings 170 for exposing the electrically connecting pads 164 of the circuit build-up structure 16. Thus, the electricity function of the circuit board is enhanced through the circuit build-up structure 16.
Through the above-described fabrication method, the present invention further provides a circuit board assembly having at least a semiconductor component, which comprises: a carrier board 11 having at least one through opening 110 for receiving a semiconductor component 12 having an active surface 12a on which a plurality of electrode pads 121 are formed; a dielectric layer 13 formed on the carrier board 11 and the active surface 12a of the semiconductor component 12, and having a plurality of openings 130 for exposing the electrode pads 121 of the semiconductor component 12; a circuit layer 14 formed on the dielectric layer 13 and with a plurality of conductive structures 141 in the openings 130 of the dielectric layer 13 for electrically connecting the electrode pads 121 of the semiconductor component 12, in addition, the circuit layer 14 further has a plurality of lands 142; and at least one passive component 15 mounted on the lands 142 for electrically connecting the circuit layer 14.
As the passive component 15 is mounted on the lands 142 of the circuit layer 14, in combination with the semiconductor component 12 embedded in the opening 110 of the carrier board 11, the electricity function of the circuit board is improved and the semiconductor package size is decreased.
Second Embodiment
FIG. 4 shows a stack structure of a circuit board assembly having at least a passive component according to a second embodiment of the present invention. As shown in FIG. 4, the stack structure of the circuit board assembly comprises: at least two carrier boards 11, 11′ each having a through opening 110,110′ respectively for receiving semiconductor components 12, 12′ in the openings 110,110′, the semiconductor components 12, 12′ respectively having active surfaces 12a, 12a′ and non-active surfaces 12b, 12b′ and the active surfaces 12a, 12a′ respectively have a plurality of electrode pads 121,121′, the two carrier boards 11, 11′ as the non-active surfaces 12b, 12b′ of the semiconductor components 12, 12′ and the non-active surfaces 12b, 12b′ of the semiconductor components 12, 12′ are combined together by an adhesive layer 18; dielectric layers 13, 13′ respectively formed on the active surfaces 12a, 12a′ of the semiconductor components 12, 12′ as well as surfaces of the carrier boards 11, 11′ as the active surfaces 12a, 12a′, the dielectric layers 13, 13′ respectively having openings 130, 130′ for exposing the electrode pads 121, 121′ of the semiconductor components 12, 12′; circuit layers 14, 14′ respectively formed on the dielectric layers 13, 13′, wherein the circuit layers 14, 14′ have a plurality of conductive structures 141, 141′ respectively formed in the openings 130, 130′ of the dielectric layers 13, 13′ for electrically connecting the electrode pads 121, 121′ of the semiconductor components 12, 12′, the circuit layers 14, 14′ respectively have a plurality of lands 142, 142′ to which passive components 15, 15′ can be mounted and electrically connected with the circuit layers 14, 14′; circuit build-up structures 16,16′ formed on surfaces of the dielectric layers 13,13′, circuit layers 14, 14′ and passive components 15,15′, the circuit build-up structures 16,16′ having a plurality of conductive structures 163, 163′ formed for electrically connecting the circuit layers 14, 14′.
Through the above-described structure, two carrier board structure with the semiconductor components 12, 12′ embedded therein and mounted with the passive components 15,15′ are integrated together through the adhesive layer 18, thereby improving the electricity function.
The above-described structure can further comprise at least a plated through hole 19 penetrating through the carrier boards 11, 11′ and the dielectric layers 13, 13′ and electrically connecting the two circuit layers 14, 14′. The circuit build-up structures 16,16′ comprise dielectric layers 161, 161′, circuit layers 162, 162′ stacked on the circuit layers 161, 161′, and conductive structures 163, 163′ formed in the dielectric layers 161,161′. A plurality of electrically connecting pads 164, 164′ are formed on surfaces of the circuit build-up structures 16, 16′ and solder mask layers 17, 17′ are formed on the surfaces of the circuit build-up structures 16, 16′. A plurality of openings 170, 170′ is formed in the solder mask layers 17, 17′ for exposing the electrically connecting pads 164, 164′ of the circuit build-up structures 16, 16′.
Since the two carrier boards 11, 11′ with the semiconductor components 12, 12′ embedded therein and mounted with the passive components 15,15′ are electrically connected together through the plated through hole 19 and the circuit build-up structures 16,16′ are further formed on the two carrier boards 11, 11′, electricity connecting function of the carrier boards are enhanced.
The carrier boards 11, 11′ can be metal board, dielectric boards or circuit boards having circuits. The semiconductor components 12, 12′ can be active components or passive components such as resistors, capacitors, or inductors.
The present invention embeds a semiconductor component in a carrier board and disposes a passive component to the carrier board so as to obtain a circuit board structure. Further, circuit board structures can be integrated together to form a stack structure. Thus, the carrier board space can be efficiently utilized and the module size can be reduced. The structure can further be varied according to practical needs.
The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.
Patent Application
20080047740
