The present invention relates to microelectronic packages, to components for use in fabrication of microelectronic packages, and to methods of making the packages and component.
Microcontact elements in the form of elongated posts or pins may be used to connect microelectronic packages to circuit boards and for other connections in microelectronic packaging. In some instances, microcontacts have been formed by etching a metallic structure including one or more metallic layers to form the microcontacts. The etching process limits the size of the microcontacts. Conventional etching processes typically cannot form microcontacts with a large ratio of height to maximum width, referred to herein as “aspect ratio”. It has been difficult or impossible to form arrays of microcontacts with appreciable height and very small pitch or spacing between adjacent microcontacts. Moreover, the configurations of the microcontacts formed by conventional etching processes are limited.
For these and other reasons, further improvement would be desirable.
In one embodiment, a method of forming microcontacts, includes, (a) providing a first etch-resistant material at selected locations on a top surface of a substrate, (b) etching a top surface of the substrate at locations not covered by the first etch-resistant material and thereby form first microcontact portions projecting upwardly from the substrate at the selected locations, (c) providing a second etch-resistant material on the first microcontact portions, and (d) further etching the substrate to form second microcontact portions below the first microcontact portions, the second etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step.
In another embodiment, a method of forming microcontacts, includes (a) applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and (b) etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step.
In still another embodiment, a microelectronic unit includes (a) a substrate, and (b) a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region, remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
In yet another embodiment, a microelectronic unit includes a substrate, a plurality of microcontacts projecting in a vertical direction from the substrate wherein a pitch between two adjacent microcontacts is less than 150 microns.
In still another embodiment, a microelectronic unit includes (a) a substrate, and (b) a plurality of elongated microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region, remote from the substrate, each microcontact having an axis and a circumferential surface which slopes toward or away from the axis in the vertical direction along the axis, such that the slope of the circumferential wall changes abruptly at a boundary between the tip region and the base region.
In another embodiment, a microelectronic unit includes (a) a substrate, and (b) a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact having a proximal portion adjacent the substrate and an elongated distal portion extending from the proximal portion in the vertical direction away from the substrate, the width of the post increasing in stepwise fashion at the juncture between the proximal and distal portions.
A first method or embodiment is described.
Once the mask 22 is placed atop the first photoresist 20, radiation is provided. Most often the radiation is in the form of ultraviolet light. This radiation exposes the first photoresist 20 at the uncovered areas 28 resulting in making the uncovered areas 28 insoluble. The opposite is true when a negative photoresist is used: the covered areas 26 become insoluble. After exposing the first photoresist 20, the mask 22 is removed. The first photoresist 20 is then developed by washing with a solution which removes the first photoresist 20 in the locations where the first photoresist 20 has not become insoluble. Thus, the photoresist exposure and development leaves a pattern of insoluble material on the top of surface 18 of the substrate 10. This pattern of insoluble material mirrors the pattern 24 of the mask 22.
After exposure and development of the photoresist, the substrate is etched as shown in
Once the thick layer 16 has been etched to a desired depth, a second layer of photoresist 34 (
At the next step, the substrate with the first and second photoresists, 20 and 34 is exposed to radiation and then the second photoresist is developed. As shown in
Once portions of the second photoresist 34 have been exposed and developed, a second etching process is performed, removing additional portions of the thick layer 16 of the tri-metal substrate 10, thereby forming second microcontact portions 36 below the first microcontact portions 32 as shown in
These steps may be repeated as many times as desired to create the preferred aspect ratio and pitch forming third, fourth or nth microcontact portions. The process may be stopped when the etch-stop layer 14 is reached. As a final step, the first and second photoresists 20 and 34, respectively, may be stripped entirely.
These processes result in microcontacts 38 shown in
may change abruptly at the boundary 52 between the first and second portions. The particular functions and hence the shape of the microcontacts are determined by the etching conditions used in the first and second etching steps. For example, the composition of the etchant and etching temperature can be varied to vary the rate at which the etchant attacks the metal layer. Also, the mechanics of contacting the etchant with the metal layer can be varied. The etchant can be sprayed forcibly toward the substrate, or the substrate can be dipped into the etchant. The etching conditions may be the same or different during etching of the first and second portions.
In the microcontacts shown in
increases in the downward direction. The second portion 36 also has a circumferential surface 46 flares outwardly; the magnitude of the slope or
of the second is dZ at a minimum at boundary 52, and progressively increases in the direction toward the base of the post. There is a substantially change in slope at boundary 52. The maximum width or diameter X of the second portion, at the base of the microcontact where the microcontact joins layer 14, is substantial greater than the maximum width or diameter of the first portion. In
changes sign at the boundary 52 between the portions. In
Lastly,
Although arrays including only two microcontacts or posts are depicted in each of
In an alternate embodiment, rather than remove the first photoresist 20 only at selected locations after the first etching step, the entire first photoresist 20 may be removed. In this instance, the second photoresist 34 may be deposited over the entire surface of the substrate 10. Then the mask 22 is placed onto the second photoresist 34. The mask 22 must be properly aligned so as to expose only at the locations previously exposed, on the first microcontact portions 32. The second photoresist 34 is then developed and further etching may be performed on the substrate 10.
Next, another photoresist is deposited, known as n+1 at step 112. Then, at step 114, this n+1 photoresist is exposed to radiation. Subsequently, at step 116, the photoresist n+1 is removed at select locations and the substrate is etched again. Then, it is evaluated whether the desired microcontact height has been achieved at step 118. If the desired microcontact height has not been achieved, at step 120, the process returns to step 112 and another photoresist is deposited onto the substrate. If the desired height has been achieved at step 122, then the remaining photoresists are removed at step 124 and the process ends.
Next, at step 220, photoresist n+1 is selectively removed and the substrate is etched again. This process may also be repeated until the desired microcontact height is achieved. Thus, at step 222, it is evaluated whether the desired microcontact height has been achieved. If the preferred height has not been achieved at step 224, then the process returns to step 212 where the photoresist is removed entirely and another photoresist n+1 is deposited and the steps continue thereon. However, if the desired height has been achieved at step 224, the remaining photoresist is removed at step 228 and the process ends.
The etch-stop layer 14 and the thin layer 12 may be united with a dielectric layer and then thin layer 12 may be etched to form traces so as to provide a component with the microcontacts connected to the traces and with the microcontacts projecting from the dielectric layer. Such a structure can be used, for example, as an element of a semiconductor chip package. For example, U.S. patent application Ser. No. 11/318,822, filed Dec. 27, 2005, the disclosure of which is hereby incorporated by reference herein, may be used.
The structure described herein may be an integral part of a multilayer substrate 10, for instance, the top layer of a multilayer substrate 10, as shown in
Certain packages include microelectronic chips that are stacked. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. Packages which include microcontacts fabricated using the processes recited herein may be stacked. Reference is made to co-pending U.S. patent application Ser. No. 11/140,312, filed May 27, 2005; and U.S. Pat. No. 6,782,610, the disclosures of which are hereby incorporated by reference. The microcontact etching steps taught in these disclosures may be replaced by the processes discussed herein.
Although a tri-metal substrate is discussed above, a suitable substrate having any number of layers may be utilized, such as for example a single metal. Additionally, rather than use a photoresist, an etch-resistant metal such as gold or other metal substantially resistant to the etchant used to etch the thick metallic layer, may be used. For example, the etch-resistant metal can be used in place of the first photoresist 20 discussed above. Spots of etch-resistant metal may be plated onto the top of the thick layer 16 after applying a mask such as a photoresist with holes at the desired locations for the spots. After plating the etch-resistant metal onto the top of the thick layer, the thick layer is etched to form the microcontacts as discussed above. The etch-resistant metal may be left in place on the tip of the microcontact. In the event an etch-resistant metal is used, as a second etch-resistant material (in place of second photoresist 34 discussed above), a mask may be used to limit deposition of the second etch-resistant metal to only the first portions 32 of the microcontacts, so that the areas between the microcontacts remain free of the etch-resistant metal. Alternately, the entire first layer of etch-resistant metal may be removed upon etching first microcontact portions 32, then a second layer of etch-resistant metal may be deposited to protect the first microcontact portions 32.
With reference to
The microcontacts formed from these processes may have a typical height ranging from about 40 microns to about 200 microns. Further, the typical pitch between microcontacts may be less than about 200 microns, preferably less than 150 microns. In particular, in reference to
In many applications, particularly where microcontacts are used connected to contacts of a semiconductor chip as, for example, in a structure as discussed below with reference to
However, the pitch between microcontacts using the process recited herein can be less than Po, (P<Po), for example, P=(0.9)P0 or less. For instance, if the diameter d of the tip is 30 microns and the height h is 60 microns, a conventional process would achieve a pitch Po of 90 microns. However, the process described herein, with at least two etches, can achieve a pitch P of about 80 microns or less. Stated another way, the multi-step etching process allows formation of unitary metallic microcontacts or posts from a single metallic layer with combinations of pitch, tip diameter and height not attainable in conventional etching processes. As the number of etching steps increases, the minimum attainable pitch for a given tip diameter and height decreases.
Referring now to
The tips of microcontacts 38 are bonded to contacts 55 of a microelectronic element such as a semiconductor chip or die 54. For example, the tips of the microcontacts may be solder-bonded to the contacts 55 of the microelectronic element. Other bonding processes, such as eutectic bonding or diffusion bonding, may be employed. The resulting packaged microelectronic element has some or all of contacts 55 on the microelectronic element connected to terminals 61 by the microcontacts and traces. The packaged microelectronic element may be mounted to a circuit panel 92, such as a printed circuit board by bonding terminals 61 to pads 94 on the circuit board. For instance, pads 94 on the circuit panel 92 may be soldered to the terminals 61, at openings 82, using solder balls 96.
The connection between the microcontacts 38 and the contacts 55 of the microelectronic element can provide a reliable connection even where the contacts 55 are closely spaced. As discussed above, the microcontacts 38 can be formed with reasonable tip diameters and height. The appreciable tip diameter can provide substantial bond area between the tip of each microcontact and the contact of the microelectronic element. In service, differential thermal expansion and contraction of the chip 54 relative to the circuit panel 92 can be accommodated by bending and tilting of microcontacts 38. This action is enhanced by the height of the microcontacts. Moreover, because the microcontacts are formed from a common metal layer, the heights of the microcontacts are uniform to within a very close tolerance. This facilitates engagement and formation of robust bonds between the microcontact tips with the contacts of the chip or other microelectronic element.
The structure of the chip carrier can be varied. For example, the chip carrier may include only one dielectric layer. The traces may be disposed on either side of the dielectric layer. Alternatively, the chip carrier may include a multi-layer dielectric, and may include multiple layers of traces, as well as other features such as electrically conductive ground planes.
A process for further embodiment of the invention uses a structure having post portions 550 (
The process of building up successive post portions may be repeated so as to form additional portions on portions 504, so that microcontacts of essentially any length can be formed. The long microcontacts provide increased flexibility and movement of the post tips. Where one or more dielectric encapsulant layers are left in place around the already-formed post portions, such as layer 508 in
As shown in
Reference is also made to the following, which are hereby incorporated by reference: U.S. patent application Ser. No. 10/985,126, filed Nov. 10, 2004; Ser. No. 11/318,822, filed Dec. 27, 2005; Ser. No. 11/318,164, filed Dec. 23, 2005; Ser. No. 11/166,982, filed Jun. 24, 2005; Ser. No. 11/140,312, filed May 27, 2005; and U.S. Pat. No. 7,176,043.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
This application is a continuation-in-part of U.S. patent application Ser. No. 11/166,982, filed Jun. 24, 2005, which application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/583,109, filed Jun. 25, 2004. application Ser. No. 11/166,982 is also a continuation-in-part of U.S. patent application Ser. No. 10/959,465, filed Oct. 6, 2004. application Ser. No. 10/959,465 also claims the benefit of the filing dates of U.S. Provisional Patent Application No. 60/508,970, filed Oct. 6, 2003; 60/533,210, filed Dec. 30, 2003; 60/533,393, filed Dec. 30, 2003; and 60/533,437, filed Dec. 30, 2003. The disclosures of all of the aforementioned applications are hereby incorporated by reference herein.
Number | Date | Country | |
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60583109 | Jun 2004 | US | |
60533210 | Dec 2003 | US | |
60533393 | Dec 2003 | US | |
60533437 | Dec 2003 | US | |
60508970 | Oct 2003 | US |
Number | Date | Country | |
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Parent | 11166982 | Jun 2005 | US |
Child | 11717587 | Mar 2007 | US |
Parent | 10959465 | Oct 2004 | US |
Child | 11717587 | Mar 2007 | US |