K. Nogami et. al., “A 9-ns HIT-Delay 32-kbyte Cache Macro for High-Speed RISC”, IEEE Journal of Solid State Circuits, vol. 25 No. 1, pp. 100-108 (Feb. 1990). |
F. Towler et. al., “A 128k 6.5ns Access/ 5ns Cycle CMOS ECL Static RAM”, 1989 IEEE international Solid State Circuits Conference, (Feb. 1989). |
M. Kimoto, “A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array”, 1989 IEEE Custom Integrated Circuits Conference. |
D. Wendell et. al. “A 3.5ns, 2Kx9 Self Timed SRAM”, 1990 IEEE Symposium on VLSI Circuits (Feb. 1990). |
T. Williams et. al., “An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation”, IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1085-1094 (Oct. 1988). |
D. Jones, “Synchronous static ram”, Electronics and Wireless World, vol. 93, No. 1622, pp. 1243-4 (Dec. 1987). |
F. Miller et. al., “High Frequency System Operation Using Synchronous SRAMS”, Midcon/87 Conference Record, pp. 430-432 Chicago, IL, USA; Sep. 15-17, 1987. |
K. Ohta, “A 1-Mbit DRAM with 33-MHz Serial I/O Ports”, IEEE Journal of Solid State Circuits, vol. 21 No. 5, pp. 649-654 (Oct. 1986). |
T.L. Jeremiah et. al., “Synchronous Packet Switching Memory and I/O Channel,” IBM Tech. Disc. Bul,. vol. 24, No. 10, pp. 4986-4987 (Mar. 1982). |
L. R. Metzeger, “A 16K CMOS PROM with Polysilicon Fusible Links”, IEEE Journal of Solid State Circuits, vol. 18 No. 5, pp. 562-567 (Oct. 1983). |
A. Yuen et. al., “A 32K ASIC Synchronous RAM Using a Two-Transistor Basic Cell”, IEEE Journal of Solid State Circuits, vol. 24 No. 1, pp. 57-61 (Feb. 1989). |
D.T. Wong et al., “An 11-ns 8Kx18 CMOS Static RAM with 0.5-βm Devices”, IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1905-1103 (Oct. 1988). |
E.H. Frank “The SBUS: Sun's High Performance System Bus for RISC Workstations” Sun Microsystems Inc. 1990. |
Ohno, C.; “Self-Timed RAM: STRAM”; Fujitsu Sci. TechJ., 24, 4, pp. 293-300 (Dec. 1988). |
“Fast Packet Bus for Microprocessor Systems with Caches”, IBM Technical Disclosure Bulletin, pp. 279-282 (Jan. 1989). |
Gustavson, D. “Scalable Coherent Interface”; Invited Paper, COMPCON Spring '89, San Francisco, CA; IEEE, pp. 536-538 (Feb. 27-Mar. 3, 1989). |
James, D.; “Scalable I/O Architecture for Buses”; IEEE, pp. 539-544 (Apr. 1989). |
Z. Amitai, “New System Architectures for DRAM Control and Error Correction”, Monolithic Memories Inc., Electro/87 and Mini/Mico Northeast: Focusing on the OEM Conference Record, pp. 1132, 4/31-3, (Apr. 1987). |
N. Siddique, “100-MHz DRAM Controller Sparks Multiprocessor Designs”, Electronic Design, pp. 138-141, (Sep. 1986). |
H. Kuriyama et al., “A 4-Mbit CMOS SRAM with 8-NS Serial Access Time”, IEEE Symposium On VLSI Circuits Digest Of Technical Papers, pp. 51-52, (Jun. 1990). |
A. Fielder et al., “A 3 NS 1K X 4 Static Self-Timed GaAs RAM”, IEEE Gallium Arsenide Integrated Circuit Symposium Technical Digest, pp. 67-70, (Nov. 1988). |
JEDEC Standard No. 21C. |
H. L. Kalter et al. “A 50-ns 16Mb DRAM with a 10-ns Data Rate and On-Chip ECC” IEEE Journal of Solid State Circuits, vol. 25 No. 5, pp. 1118-1128 (Oct. 1990). |
J. Chun et al. “A pipelined 650MHz GaAs 8K ROM with Translation Logic” GaAs IC Symposium 1990. |
Motorola MC88200 Cache/Memory Management Unit User's Manual, Motorola Inc. 1989. |
B. Ramakrishna et al., “The Cydra 5 Departmental Supercomputer Design Philosophies, Decisions, and Trade-offs” Computer IEEE, Jan. 1989 pp. 12-35. |
Takasugi, A. et al., “A Data-Transfer Architecture for Fast Multi-Bit Serial Acess Mode DRAM,” 11th European Solid State Circuits Conference, Toulouse, France pp. 161-165 (Sep. 1985). |
Amitai, Z., “Burst Mode Memories Improve Cache Design,” WESCON/90 Conference Record, pp. 29-32 (Nov. 1990). |
Fagan, J.L., “A 16-kbit Nonvolatile Charge Addressed Memory,” IEEE Journal of Solid-State Circuits, vol. SC-11, No. 5, pp. 631-636 (Oct. 1976). |
Ikeda, Hiroaki et al., “100 MHz Serial Acess Architectures for 4Md Field Memory,” Symposium of VLSI Circuits, Digest of Technical Papers, pp. 11-12 (Jun. 1990). |
Schmitt-Landsiedel, Doris, “Pipeline Architecture for Fast CMOS Buffer RAMs,” IEEE Journal of Solid-State Circuits, vol. 25, No. 3, pp. 741-747 (Jun. 1990). |
Horowitz et al., “MIP-X: A 20-MIPS Peak 32-Bit Microprocessor with ON-Chip Cache”, IEEE J. Solid State Circuits, vol. SC-22, No. 5, pp. 790-798 (Oct. 1987). |
Robert J. Lodi et al., “Chip and System Characteristics of 2048-Bit MNOS-BORAM LSI Circuit,” 1976 IEEE International Solid-State Circuits Conference (Feb. 18, 1976). |
1989 GaAs IC Data Book & Designers Guide, Gigabit Logic Inc. (Aug. 1989). |
“IC's for Entertainment Electronics, Picture in Picture System Edition 8.89”, Siemens AG, 2/89. |
Pelgrom et al., “A 32-kbit Variable-Length Shift Register for Digital Audio Application”, IEEE Journal of Solid-State Circuits, vol. sc-22, No. 3, Jun. 1987, pp. 415-422. |
Grover et al., “Precision Time-Transfer in Transport Networks Using Digital Crossconnect Systems”, IEEE Paper 47.2 Globecom, 1988, pp. 1544-1548. |
Gustavson et al., “The Scalable Interface Project (Superbus)” (DRAFT), SCI-22 Aug. 88-doc1 pp. 1-16, Aug. 22, 1988. |
Knut Alnes, “SCI: A Proposal for SCI Operation”, SCI-Nov. 10, 1988-doc23, Norsk Data, Oslo, Norway, pp. 1-12, Nov. 10, 1988. |
Knut Alnes, “SCI: A Proposal for SCI Operation”, SCI-Jan. 6, 1989-doc31, Norsk Data, Oslo, Norway, pp. 1-24, Jan. 6, 1989. |
Bakka et al., “SCI: Logical Level Proposal”, SCI-Jan. 6, 1989-doc32, Norsk Data, Oslo, Norway, pp. 1-20, Jan. 6, 1989. |
Knut Alnes, “Scalable Coherent Interface”, SCI-Feb. 89-doc52, Norsk Data, Oslo, Norway, pp. 1-8, May 10, 1989. |
Boysel et al., “Four-Phase LSI Logic Offers New Approach to Computer Designer”, Four-Phase System Inc. Cupertino, CA, Computer Design, Apr. 1970, pp. 141-146. |
Boysel et al., “Random Access MOS Memory Packs More Bits To The Chip”, Electronics, Feb. 16, 1970, pp. 109-146. |
Hansen et al., “A RISC Microprocessor with Integral MMU and Cache Interface”, MIPS Computer Systems, Sunnyvale, CA, IEEE 1986 pp. 145-148. |
Moussouris et al., “A CMOS Processor with Integrated Systems Functions”, MIPS Computer Systems, Sunnyvale, CA, IEEE 1986 pp. 126-130. |
“LR2000 High Performance RISC Microprocessor Preliminary” LSI Logic Corp. 1988, pp. 1-15. |
“LR2010 Floating Point Accelerator Preliminary” LSI Logic Corp. 1988, pp. 1-20. |
“High Speed CMOS Databook”, Integrated Device Technology Inc. Santa Clara, CA, 1988 pp. 9-1 to 9-14. |
Riordan T. “MIPS R2000 Processor Interface 78-00005(C)”, MIPS Computer Systems, Sunnyvale, CA, Jun. 30, 1987, pp. 1-83. |
Moussouris, J. “The Advanced Systems Outlook-Life Beyond RISC: The next 30 years in high-performance computing”, Computer Letter, Jul. 31, 1989 (an edited excerpt from an address at the fourth annual conference on the Advanced Systems Outlook, in San Francisco, CA (Jun. 5)). |