BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic view (No. 1) illustrating an embodiment of the present invention;
FIG. 2 is a schematic view (No. 2) illustrating an embodiment of the present invention;
FIGS. 3A and 3B are each a schematic view (No. 3) illustrating an embodiment of the present invention;
FIG. 4 is a schematic view (No. 4) illustrating an embodiment of the present invention;
FIG. 5 is a schematic view (No. 5) illustrating an embodiment of the present invention;
FIGS. 6A and 6B are each a schematic view (No. 6) illustrating an embodiment of the present invention;
FIGS. 7A, 7B, and 7C are each a schematic view (No. 7) illustrating an embodiment of the present invention;
FIG. 8 is a schematic view (No. 8) illustrating an embodiment of the present invention;
FIG. 9 is a schematic view (No. 9) illustrating an embodiment of the present invention;
FIGS. 10A and 10B are each a schematic view (No. 10) illustrating an embodiment of the present invention;
FIG. 11 is a schematic view (No. 11) illustrating an embodiment of the present invention;
FIG. 12 is a schematic view (No. 12) illustrating an embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view of the case in which grooves formed by etching each have a depth deeper than planned;
FIG. 14 is a schematic cross-sectional view (No. 1) illustrating a measure;
FIG. 15 is a schematic cross-sectional view (No. 2) illustrating a measure;
FIGS. 16A, 16B, and 16C are each a schematic cross-sectional view (No. 1) illustrating an example of a method of forming grooves before forming a device;
FIGS. 17A, 17B, and 17C are each a schematic cross-sectional view (No. 2) illustrating an example of a method of forming grooves before forming a device;
FIGS. 18A and 18B are each a schematic cross-sectional view (No. 1) illustrating another example of a method of forming grooves before forming a device; and
FIGS. 19A and 19B are each a schematic cross-sectional view (No. 2) illustrating another example of a method of forming grooves before forming a device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In a method according to an embodiment for producing a semiconductor device, monolithic microwave IC (MMIC) chips each including a high-In-content device produced by epitaxial lift-off (ELO) are exemplified. The method according to this embodiment for producing the MMIC chips has the following advantages.
1. A device layer is separated from a substrate by ELO to form MMIC chips.
2. Grooves which are in the form of a grid and which are each located between adjacent chips are formed in the device substrate side before the device substrate is bonded to a supporting substrate. The grooves in the form of a grid function as inlets for an etching solution that etches a sacrificial layer during the subsequent ELO step. In the ELO step, the penetration of the etching solution through the grooves results in the rapid completion of etching of the sacrificial layer.
3. The device layer is transferred to the supporting substrate while chip arrangement on the device substrate is maintained.
4. The supporting substrate serves as a heat sink for the MMIC chips.
5. In some cases, after the completion of the ELO step, a backside process is performed. Then the supporting substrate is subjected to dicing. The resulting chips are mounted on IC cases.
An embodiment of the present invention will be described below on the basis of the drawings. As shown in FIG. 1, a sacrificial layer 2 composed of AlAs and having a thickness of about 2 nm is formed on a semiconductor substrate 1 composed of InP. A device-protecting layer 3 composed of InP is formed thereon. A device layer 4 is epitaxially grown on the device-protecting layer 3. The device layer 4 is formed so as to be lattice-matched to the semiconductor substrate 1. In this embodiment, the device layer 4 has a structure of n+InGaAs/n−InP/u−InGaAs/p+InGaAs/n−InP/n+InP/n+InGaAs in that order from the semiconductor substrate 1 side.
As shown in FIG. 2, desired devices are formed by photolithography or the like in the epitaxially grown device layer 4. Hetero-junction bipolar transistors (HBTs) having emitters to be grounded are exemplified in FIG. 2.
An insulating film 5 composed of benzocyclobutene (BCB) and having a thickness of about 2 μm is formed around the HBTs. The insulating film 5 may also be an inorganic film, such as a SiO2 film or a SiN film, formed by plasma-enhanced chemical vapor deposition (CVD) or an organic film such as a polyimide film. Preferably, the insulating film 5 is an organic coating film, such as a BCB film or a polyimide film, which can easily have a thickness of several micrometers. Passive elements are formed in plane with the HBTs. Ground vias are appropriately formed. Connection metal films 7 composed of Au or the like and communicating with the ground vias are formed on the surface of the insulating film 5.
As shown in FIGS. 3A and 3B, a resist 6 is applied on the device layer. A grid pattern in response to the chip size is formed. That is, openings are formed by photolithography in portions of the resist 6 corresponding to peripheries of the chips.
As shown in FIG. 4, the insulating film 5 composed of BCB is etched by dry etching with a mixture gas of CF4/O2 through the openings in the resist 6 located on the device layer.
As shown in FIG. 5, the device-protecting layer 3 and the sacrificial layer 2 are etched by wet etching with, for example, diluted hydrochloric acid, through openings formed by etching the insulating film 5, thereby forming grooves extending from the device layer 4 to the sacrificial layer 2 and in the form of a grid on the surface of the substrate. The device layer 4 is surrounded by the device-protecting layer 3 and the insulating film 5, and the device-protecting layer 3 is strongly bonded to the insulating film 5, thereby preventing the penetration of the etching solution to the device layer 4 during etching.
As shown in FIGS. 6A and 6B, the resist 6 shown in FIG. 5 is removed. The resulting grooves d are arranged along dicing lines that lie at the peripheries of the chips. The grooves each have a width A of about 100 μm. The grooves d lying along the dicing lines serve as reference lines during cutting in the subsequent dicing step. The distance B between the side face of each groove d and a corresponding one of the active regions of the devices is set at about 10 μm. A larger distance B is preferred from the viewpoint of the protection of the devices.
As shown in FIGS. 7A, 7B, and 7C, a supporting substrate 10 (composed of, for example, Cu or AlN) having a film 11 composed of Au and formed by evaporation on the entirety of a surface is bonded to the device layer 4 side of the semiconductor substrate 1. The connection metal film 7 composed of Au is formed on the device layer 4 side. Bonding the supporting substrate 10 connects the film 11 on the supporting substrate 10 to the connection metal film 7 disposed on the device layer 4. In this case, Au is used for connection. Alternatively, the connection may be established by heating with solder. Cu may also be used.
When the semiconductor substrate 1 is bonded to the supporting substrate 10, the grooves d formed in the device layer 4 appear as openings located at the periphery of the bonded substrate.
As shown in FIG. 8, the bonded substrate (obtained by bonding the semiconductor substrate 1 to the supporting substrate 10) formed in the prior step is immersed in a HF solution (etching solution). The HF solution has a concentration of, for example, 10% to 50%. The immersion of the bonded substrate in the HF solution results in the dissolution of the sacrificial layer 2, thereby separating the semiconductor substrate 1 from the supporting substrate 10 connected to the device layer 4.
The HF solution penetrates through the grooves d formed in the device layer 4. That is, the HF solution rapidly penetrates from the middle portion to the end portions of the bonded substrate through the grooves d in the form of a grid. The grooves d extend to the sacrificial layer 2. Thus, the HF solution penetrates to the sacrificial layer 2 in a small amount of time through the grooves d, resulting in the rapid separation of the substrate. The supporting substrate 10 may be slightly warped during the separation step.
As shown in FIG. 9, after the supporting substrate 10 connected to the device layer 4 is separated from the semiconductor substrate 1, the semiconductor substrate 1 is alone. Thus, the semiconductor substrate 1 can be reused after surface cleaning.
As shown in FIGS. 10A and 10B, the supporting substrate 10 is placed down. The devices are subjected to backside treatment, according to need, to form electrodes 8.
As shown in FIG. 11, the devices (chips) on the supporting substrate 10 are subjected to dicing to form individual chips 100. As shown in FIG. 12, each of the chips 100 is mounted on a package 101, such as a low temperature co-fired ceramic package (LTCC). Interconnection is established with bonding wire 102 to complete semiconductor devices.
According to this embodiment, the grooves each extending from the device layer 4 to the sacrificial layer 2 are formed; hence, in separating the semiconductor substrate 1 from the device layer 4, the etching solution penetrates efficiently to the sacrificial layer 2 through the grooves and dissolves the sacrificial layer 2 in a small amount of time, thus separating the semiconductor substrate 1.
From the viewpoint of the reuse of the semiconductor substrate 1 separated, wet etching performed in the final stage of the process of forming the grooves will be described. FIG. 13 is a schematic cross-sectional view of the case in which the grooves formed by wet etching each have a depth deeper than planned. That is, during the formation of the grooves d, the grooves are dug by etching from the device-protecting layer 3 to the sacrificial layer 2. In the case of the failure of controlling etching depth, the semiconductor substrate 1 is disadvantageously etched. If the semiconductor substrate 1 is etched, the semiconductor substrate 1 may not be reused unless irregularities of the surface are removed.
Therefore, in this embodiment, to prevent the semiconductor substrate 1 from being etched during the formation of the grooves, the following method is employed (see FIG. 14):
(1) The device-protecting layer 3 is composed of InGaAs.
(2) A stop layer 1a composed of InP is formed under the sacrificial layer 2.
(3) The device-protecting layer 3 and the sacrificial layer 2 are etched with a mixed solution of phosphoric acid and a hydrogen peroxide solution.
In this case, the stop layer 1a composed of InP disposed under the sacrificial layer 2 is not etched with the mixed solution of phosphoric acid and the hydrogen peroxide solution, thereby terminating the etching.
Therefore, only the device-protecting layer 3 and the sacrificial layer 2 are etched, resulting in the prevention of etching the semiconductor substrate 1.
Another method will be described below (see FIG. 15);
(1) The device-protecting layer 3 is composed of InP.
(2) A mixed crystal layer 1b containing As, e.g., InGaAs or InAlAs, is formed under the sacrificial layer 2.
(3) The device-protecting layer 3 and the sacrificial layer 2 are etched with diluted hydrochloric acid.
In this case, the mixed crystal layer 1b containing As, e.g., InGaAs or InAlAs, disposed under the sacrificial layer 2 is not etched by diluted hydrochloric acid, thereby terminating the etching. Therefore, only the device-protecting layer 3 and the sacrificial layer 2 are etched, resulting in the prevention of etching the semiconductor substrate 1. When the mixed crystal layer 1b containing As, e.g., InGaAs or InAlAs, left on the surface of the separated semiconductor substrate 1 is dissolved with a phosphoric acid-based etching solution, a flat InP surface can be obtained and is reusable.
In the above-describe embodiment, the MMICs are exemplified as target semiconductor devices. The present invention is not limited thereto. The present invention is applicable to another semiconductor device. The composition of each layer is only an example and is not limited to this embodiment. The grooves are preferably in the form of a grid and arranged along the dicing lines between the chips. Alternatively, in order to allow the etching solution to penetrate to the sacrificial layer 2 through the grooves, the grooves may be formed in desired positions on the substrate. In this case, when the supporting substrate 10 larger than the semiconductor substrate 1 is bonded, the grooves need to communicate with ends of the semiconductor substrate 1. This prevents the occlusion of inlets of the grooves d for the etching solution by bonding the supporting substrate 10 to the semiconductor substrate 1.
In the above-described embodiment, with respect to the depth of the grooves d, the case of the grooves each extending from the device layer 4 to the bottom of the sacrificial layer 2 is described. Alternatively, each groove may extend from the device layer 4 to the middle of the thickness of the sacrificial layer 2. Each groove may extend from the device layer 4 to the surface of the sacrificial layer 2. That is, it is necessary to increase the contact area between the etching solution and the sacrificial layer 2 when the etching solution penetrates through the grooves d. Therefore, preferably, each groove extends from the device layer 4 to the middle of the thickness of the sacrificial layer 2. More preferably, each groove extends from the device layer 4 to the surface of the sacrificial layer 2. Most preferably, each groove extends from the device layer 4 to the bottom of the sacrificial layer 2, as described in the embodiment above.
In the above-described embodiment, the grooves are formed after the formation of the devices in the device layer 4. Alternatively, after the device layer 4 is grown, the grooves d may be formed before the devices are formed. In the case where the grooves are formed before the devices are formed, preferably, the grooves d are filled with an insulating material, or the inner walls of the grooves d are covered with insulating films, from the standpoint of the prevention of damage to the inside of the device layer 4 from the grooves d during the formation of the devices.
FIGS. 16A to 17C are each a schematic cross-sectional view illustrating an example of a method of forming the grooves before forming the devices. As shown in FIG. 16A, the sacrificial layer 2 composed of AlAs and having a thickness of about 2 nm is formed on the semiconductor substrate 1 composed of InP. The device-protecting layer 3 composed of InP is formed thereon. The device layer 4 is epitaxially grown on the device-protecting layer 3. The device layer 4 is lattice-matched to the semiconductor substrate 1. In this embodiment, the device layer 4 has a structure of n+InGaAs/n−InP/u−InGaAs/p+InGaAs/n−InP/n+InP/n+InGaAs in that order from the semiconductor substrate 1 side. The resist 6 is applied to the device layer 4. A grid pattern in response to the chip size is formed. That is, openings are formed by photolithography in portions of the resist 6 corresponding to peripheries of the chips.
As shown in FIG. 16B, the grooves d are formed by wet etching with, for example, diluted hydrochloric acid, through the openings formed in the resist 6. The grooves d are formed in the form of a grid on the surface of the substrate so as to extend to the sacrificial layer 2 through the device layer 4 and the device-protecting layer 3.
After the resist 6 is detached, as shown in FIG. 16C, a silicon oxide film 9 is deposited by, for example, plasma-enhanced CVD so as to cover surfaces of the grooves d. This prevents the exposure of the device layer 4 at the grooves d. A material that can be dissolved in the etching solution used in etching the sacrificial layer 2 in the subsequent step should be used as the material of the film deposited.
As shown in FIG. 17A, portions of the silicon oxide film 9 corresponding to top faces of the chips are removed by reactive ion etching (RIE) to form openings. Then a common device processing is performed. As shown in FIG. 17B, devices are formed in the device layer 4. The connection metal film 7 is formed on the surface of each chip. As shown in FIG. 17C, the supporting substrate 10 (composed of, for example, Cu or AlN) having the film 11 composed of Au and formed by evaporation on the entirety of a surface is bonded to the device layer 4 side of the semiconductor substrate 1.
The subsequent steps are equal to the steps shown in FIGS. 8 to 12. The HF solution (etching solution) penetrates to the sacrificial layer 2 through the grooves d, thus rapidly separating the substrate. Also, the silicon oxide film 9 disappears during etching.
FIGS. 18A to 19B are each a schematic cross-sectional view illustrating another example of a method of forming the grooves before forming the devices. As shown in FIG. 18A, silicon oxide films 12 having a striped pattern are formed at portions corresponding to peripheries of chips on the semiconductor substrate 1 composed of InP. A material that can be dissolved in the etching solution used in etching the sacrificial layer in the subsequent step should be used as the material of the film formed.
As shown in FIG. 18B, the sacrificial layers 2 having a thickness of about 2 nm and composed of AlAs are formed between the silicon oxide films 12 on the semiconductor substrate 1. The device-protecting layers 3 composed of InP are formed thereon. The device layers 4 are epitaxially grown on the device-protecting layers 3. The device layers 4 are lattice-matched to the semiconductor substrate 1. In this embodiment, the device layer 4 has a structure of n+InGaAs/n−InP/u−InGaAs/p+InGaAs/n−InP/n+InP/n+InGaAs in that order from the semiconductor substrate 1 side. The device layers 4 and the silicon oxide films 12 constitute grooves d.
As shown in FIG. 19A, devices are formed in the device layers 4. The connection metal films 7 are formed on the surfaces of the chips. As shown in FIG. 19B, the supporting substrate 10 (composed of, for example, Cu or AlN) having the film 11 composed of Au and formed by evaporation on the entirety of a surface is bonded to the device layer 4 side of the semiconductor substrate.
The subsequent steps are equal to the steps shown in FIGS. 8 to 12. The HF solution (etching solution) penetrates to the sacrificial layers 2 through the grooves d, thus rapidly separating the substrate. Also, the silicon oxide films 12 disappear during etching.
In this embodiment, the method forming the grooves d before forming the devices in the device layer 4 and forming the devices after forming the grooves d may be employed.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Patent Application
20080050858
