Patent Application
20130001760
Disclosed embodiments relate to semiconductor packaging, and more specifically to substrates for packaged semiconductor devices that include non-planar die pads.
One type of semiconductor package is referred to as a ball grid array (BGA) package. BGA packages were developed to provide a higher lead count and a smaller foot print as compared to conventional plastic or ceramic semiconductor packages. A BGA package includes an area array of solder balls that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component.
A conventional BGA package includes a planar dielectric substrate, a semiconductor die mounted to the substrate using a die attach material (e.g., a paste), and an encapsulating epoxy resin which encapsulates the die. The substrate is initially a segment of a substrate panel (or sheet). The substrate panel includes multiple substrates that is used to simultaneously fabricate multiple BGA packages. Following the fabrication process for the BGA packages, the substrate panel is singulated into individual BGA package devices.
Typically, the substrate comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin. The substrate includes a planar die attach surface that generally comprises a dielectric solder resist layer on a metal layer (e.g., copper). During a die attach step of the assembly process, the semiconductor die is adhesively bonded to a planar solder resist layer on the substrate using a die attach adhesive. The semiconductor die is then bonded to bond pads on the substrate that are revealed by apertures in the solder resist layer.
Another type of package substrate is a lead frame that is generally processed as a lead frame sheet. For lead frames the die pad is generally flat and comprises a metal and a plurality of metal lead fingers are around the die pad.
Both dielectric substrates for BGA packages and lead frames for lead frame-based devices are subject to problems associated with the inability to control the volume of die attach material either under the semiconductor die in the case of under dispense, or lateral to the semiconductor die in the case of over dispense. Such inability to control the volume of the die attach material in the case of wirebonding assembly can result in wire bond failures between the semiconductor die and pads on a package substrate or the lead fingers of a lead frame.
Disclosed embodiments include substrate designs that comprise a die pad having an outer raised flat portion and a recessed portion including an interior recessed portion. The semiconductor die sits directly on the outer raised flat portion so that there is no intervening die attach material between the semiconductor die and the outer raised flat portion. Disclosed embodiments have been found to solve the above-described assembly problems leading to wire bond failures when using conventional substrate designs including both tilting of the semiconductor die and the die attach material bleeding out so that it covers the substrate pads.
Disclosed embodiments apply to a variety of package substrates including dielectric (e.g., organic or ceramic) substrates, as well as lead frames. In the case of dielectric substrates, the outer raised flat portion can be provided by solder resist, while for lead frame embodiments the outer raised flat portion can comprise a metal or metal alloy.
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Substrate 110 in the embodiment shown in
Solder resist (or solder mask) as used herein and known in the art is a lacquer-like layer of polymer (e.g., an epoxy) that provides a permanent protective coating for metal (e.g., copper) traces of substrates including printed circuit boards (PCBs) that prevents solder from bridging between conductors, thereby preventing short circuits. One solder resist material is epoxy liquid that is silkscreened through a pattern onto the substrate. Other types are the liquid photoimageable solder mask (LPSM) inks and dry film photoimageable solder mask (DFSM). All three of these processes go through a thermal cure of some type after the pattern is defined.
Metal layer 111 provides metal traces a plurality of substrate contact pad regions, such as contact pad regions 111(a) and 111(b) that are shown coupled to bond pads 126 on semiconductor die 125 by bond wires 132.
The depiction 340 shown in
Disclosed substrates can also be used for a variety of electronic assemblies. One example is for flip chip mounted semiconductor die.
Advantages of disclosed embodiments include the ability to use industry standard equipment. Moreover, there is no need for 100% coverage of the die attach material, thus saving die attach material. Other advantages include the ability to mount with larger die sizes without increasing die pad size, or the package footprint.
Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different IC devices and related products. Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
