Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a power overlay (POL) packaging structure that includes an improved thermal interface.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system.
The general structure of a prior art power overlay (POL) structure 10 is shown in
A heat sink 22 is also typically included in the POL structure 10 to providing a way to remove the heat generated by semiconductor devices 12 and protect the devices 12 from the external environment. Heat sink 22 is thermally coupled to the devices 12 using a direct bond copper (DBC) substrate 24. As shown, DBC substrate 24 is positioned between the upper surfaces of semiconductor devices 12 and the lower surface of heat sink 22.
DBC substrate 24 is a prefabricated component that includes a non-organic ceramic substrate 26 such as, for example, alumina, with upper and lower sheets of copper 28, 30 bonded to both sides thereof via a direct bond copper interface or braze layer 31. The lower copper sheet 30 of DBC substrate 24 is patterned to form a number of conductive contact areas before DBC substrate 24 is attached to semiconductor devices 12. A typically DBC substrate may have an overall thickness of approximately 1 mm.
During the fabrication process of POL structure 10, solder 32 is applied to the surfaces of semiconductor devices 12. DBC substrate 24 is then lowered onto solder 32 to align the patterned portions of lower copper sheet 30 with solder 32. After DBC substrate 24 is coupled to semiconductor devices 12, an underfill technique is used to apply a dielectric organic material 34 in the space between adhesive layer 16 and DBC substrate 24 to form a POL sub-module 36. A thermal pad or thermal grease 38 is then applied to the upper copper layer 28 of DBC substrate 24.
The use of a DBC substrate in a POL structure 10 has a number of limitations. First, the material properties of the copper and ceramic materials of the DBC substrate place inherent limitations on the design of the DBC substrate. For example, due to the inherent stiffness of ceramics and the differences in the thermal expansion coefficients of the copper and ceramic materials of DBC substrate 24, copper sheets 28, 30 must be kept relatively thin to avoid undue stresses placed on the ceramics caused by large swings in temperature in the copper material. In addition, since the surface of the lower copper layer of the DBC substrate 24 that faces semiconductor device(s) 12 is planar, the DBC substrate 24 does not facilitate fabrication of a POL package having semiconductor devices of differing height.
Also, DBC substrates are relatively expensive to manufacture and are a prefabricated component. As DBC substrate 24 is a prefabricated component, the thickness of copper sheets 28, 30 is predetermined based on the thickness of the copper foil layer applied to the ceramic substrate 26. Also, because DBC substrate 24 is fabricated prior to assembly with the remainder of the components of the POL structure, the dielectric filler or epoxy substrate that surrounds the semiconductor devices 12 is applied using an underfill technique after the DBC substrate 24 is coupled to semiconductor devices 12. This underfill technique is time consuming and can result in undesirable voids within the POL structure.
Therefore, it would be desirable to provide a POL structure having an improved thermal interface that overcomes the aforementioned structural and processing limitations of known POL structures that incorporate a DBC substrate. It would further be desirable for such a POL structure to account for semiconductor devices of different thickness while minimizing cost of the POL structure.
Embodiments of the invention overcome the aforementioned drawbacks by providing a power overlay (POL) structure that eliminates the usage of a DBC substrate as a thermal interface between a POL sub-module and a heat sink. An improved thermal interface is provided for semiconductor devices that includes conducting shims that account for semiconductor devices of varying heights.
In accordance with one aspect of the invention, a semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.
In accordance with another aspect of the invention, a method of forming a semiconductor device package includes providing a semiconductor device, affixing a first surface of the semiconductor device to a first surface of a dielectric layer, and affixing a first surface of a conductive shim to the first surface of the dielectric layer. The method also includes disposing a heatspreader on a second surface of the semiconductor device and a second surface of the conductive shim, the heatspreader electrically coupling the semiconductor device to the conducting shim, and forming a metal interconnect structure on a second surface of the dielectric layer. The metal interconnect structure extends through vias formed in the dielectric layer to contact the first surface of the semiconductor device and the first surface of the conductive shim.
In accordance with yet another aspect of the invention, a power overlay (POL) structure includes an insulating substrate, a power device attached to the insulating substrate via an adhesive layer and an electrically conducting shim attached to the insulating substrate via the adhesive layer. The POL structure further includes an electrically and thermally conducting slab coupled to a top surface of the power device and a top surface of the conducting shim and a metallization layer extending through the insulating substrate. The metallization layer is electrically coupled to contact locations on the first and second surfaces of the power device.
These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings.
The drawings illustrate embodiments presently contemplated for carrying out the invention.
In the drawings:
Embodiments of the present invention provide for a power overlay (POL) structure having an improved thermal interface included therein, as well as a method of forming such a POL structure. The POL structure includes conducting shims that account for semiconductor devices of varying heights and a thermal interface layer that increases options for encapsulation materials and methods.
Referring to
Semiconductor devices 43, 44, 45 are coupled to a dielectric layer 48 by way of an adhesive layer 50. Dielectric layer 48 may be in the form of a lamination or a film, according to various embodiments, and may be formed of one a plurality of dielectric materials, such as Kapton®, Ultem®, polytetrafluoroethylene (PTFE), Upilex®, polysulfone materials (e.g., Udel®, Radel®), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide material.
POL sub-module 42 also includes a metallization layer or interconnect structure 52, which forms a direct metallic connection to semiconductor devices 43, 44, 45 by way of a metal interconnects 54 that extends through vias 56 formed in dielectric layer 48 to connect to contact pads 58 on respective semiconductor devices 43, 44, 45.
POL sub-module 42 further includes one or more conducting slabs or heatspreaders 60, which are secured to semiconductor devices 43, 44, 45 with a thermally and electrically conductive contact layer 62. According to various embodiments, conductive contact layer 62 may be a solder material, a conductive adhesive, or a sintered silver, as examples. Conducting slabs 60 are a metal or alloy material, such as, for example, copper, aluminum, molybdenum, or combinations thereof such as copper-molybdenum or copper-tungsten, and composites such as aluminum-silicon, aluminum-silicon carbide, aluminum-graphite, copper-graphite and the like.
A dielectric filler material 64 is also provided in POL sub-module 42 to fill gaps in the POL sub-module 42 between and around semiconductor devices 43, 44, 45 and conducting slabs 60, so as to provide additional structural integrity to POL sub-module 42. According to various embodiments, dielectric filler material 64 may be in the form of a polymeric material, such as, for example, an underfill (e.g., capillary underfill or no-flow underfill), encapsulate, silicone, or a molding compound.
POL structure 40 also includes a heat sink 66 to facilitate cooling of semiconductor devices 43, 44, 45. Heat sink 66 comprises a material having a high thermal conductivity, such as copper, aluminum, or a composite material. Heat sink 66 is coupled to POL sub-module 42 by way of a thermal interface substrate or layer 68 formed over conducting slabs 60 and dielectric filler material 64.
Thermal interface layer 68 is a thermally conductive, electrically insulating polymeric or organic material such as, for example, a thermal pad, a thermal paste, a thermal grease, or a thermal adhesive. Thermal interface layer 68 electrically isolates heat sink 66 from conducting slabs 60. According to one embodiment, thermal interface layer 68 comprises conductive fillers, particles, or fibers suspended in a matrix of resin or epoxy. For example, thermal interface layer 68 may be an epoxy or silicon resin that is filled with thermally conductive, electrically insulating fillers such as alumina and/or boron nitride. According to one embodiment, thermal interface layer 68 has a thickness of approximately 100 μm. However, one skilled in the art will recognize that the thickness of thermal interface layer 68 may vary based on design specifications. Thermal interface layer 68 provides superior thermal performance as compared to a DBC substrate because thermal interface layer 68 is not subject to the thermal resistance of the ceramic layer included within DBC substrate.
In embodiments where thermal interface layer 68 is a thermal paste, a thermal grease, or a thermal pad, such as, for example a pre-formed sheet or film of organic material, heat sink 66 is secured to POL sub-module 42 using screws or other fastening devices (not shown), at a number of locations around the perimeter of POL sub-module 42 causing thermal interface layer 68 to be sandwiched between conducting slabs 60 and heat sink 66. Alternatively, in embodiments where thermal interface layer 68 is a polymeric adhesive, thermal interface layer 68 is applied to POL sub-module 42 in a tacky state and cured after heat sink 66 is positioned atop thermal interface layer 68, thereby bonding heat sink 66 to POL sub-module 42 absent additional fasteners. POL sub-module 42 also includes an input-output (I/O) connection 70 to enable surface mounting of the POL structure 40 to an external circuit, such as a printed circuit board (PCB), as described in more detail with respect to
Referring now to
As shown, POL sub-module 78 includes a multi-layer thermal interface 80 positioned between conducting slabs 60 and heat sink 66. Multi-layer thermal interface 80 includes a first thermal interface layer 82, a ceramic insulator layer 84, and a second thermal interface layer 86. The inclusion of ceramic insulator layer 84 between POL sub-module 78 and heat sink 66 provides additional electrical isolation for high voltage applications. Insulator layer 84 may be constructed of a ceramic material such as alumina or aluminum nitride, as examples.
As shown, first thermal interface layer 82 is sandwiched between conducting slabs 60 and ceramic insulator layer 84. According to one embodiment first thermal interface layer 82 of
In an alternative embodiment, first thermal interface layer 82 comprises an electrically conductive material, such as, for example, solder, conductive adhesive, or sintered silver, formed as a number of discrete pads 88 atop conducting slabs 60, as illustrated in
Referring now to
While the embodiments described with respect to
Referring now to
A plurality of vias 56 is then formed through adhesive layer 50 and dielectric layer 48, as illustrated in
While the formation of vias 56 through adhesive layer 50 and dielectric layer 48 is shown in
Referring now to
As shown in
Referring now to
According to one embodiment of the invention, and as shown in
As shown in
In a next step of the fabrication process, a first side 110 of a thermal interface 112 is applied to respective top surfaces 106, 108 of conducting slabs 60 and dielectric filler material 64, as shown in
In a next step of the fabrication technique, I/O connections 70 are applied to solder mask layer 74. In one embodiment, I/O connections 70 are solder bumps 72, as shown in
Referring now to
As shown, POL sub-module 118 includes semiconductor device(s) 44 mounted to a dielectric layer 48 by way of an adhesive layer 50. Metal interconnects 54 extend through vias 56 formed in dielectric layer 48 to connect to contact pads (not shown) on semiconductor device(s) 44. A heatspreader/conducting slab 120 is coupled to each semiconductor device 44 by way of a conductive contact layer 62. Similar to conducting slabs 60 of
As shown in
Referring now to
Referring first to
An alternative embodiment of POL sub-module 124 is shown in
While embodiments of the invention have been described as including power semiconductor devices used in high voltage power applications, one skilled in the art will recognize that the techniques set forth herein are equally applicable to low power applications and chip packages that incorporate non-power semiconductor devices or semiconductor devices having electrical connections that run to only a single side of the semiconductor devices. In such applications, integrated chip packages may be formed similar to POL sub-module 42 (
Referring now to
Referring first to the embodiment illustrated in
As shown, a first surface 39 of semiconductor device 44 and a first surface 41 of conducting shim 45 are coupled to dielectric layer 48 via adhesive layer 50. Conducting shim 45 is sized such that a second surface 49 of conducting shim 45 is substantially co-planar with a second surface 47 of semiconductor device 44, as shown in
Conductive contact layer 62 is an electrically and thermally conductive material such as, for example, a solder material, a conductive adhesive, or a sintered silver, as examples. Heatspreader 60 comprises a material that is thermally and electrically conductive. As such, heatspreader 60 electrically couples second surface 47 of semiconductor device 44 to conducting shim 45 and facilitates heat transfer away from semiconductor device 44. Metallization layer 54 extends through vias 56 formed in dielectric layer 48 and creates electrical connections to both the first surface 39 and the second surface 47 of semiconductor device 44.
According to embodiments where semiconductor device 44 is a low power device, the top surface 59 of conducting slab 60 may be left exposed for convective cooling, as shown in
Referring to
While the embodiments disclosed in
Beneficially, embodiments of the invention thus provide a POL packaging and interconnect structure that includes a thermal interface that is absent the drawbacks of a DBC substrate. For example, as thermal interface layer 68 and multi-layer thermal interface 80 may be applied in a fabrication step that occurs after dielectric filler material 64 is applied and cured, dielectric filler material 64 may be applied using an encapsulating or overmolding technique rather than a more costly and time-consuming underfill process that is more likely to result in voids. Also, because the thermal interface is formed during the package build-up process, rather than being provided as a prefabricated component, the dimensions and materials of thermal interface may be tailored based on desired operating characteristics. Further, the use of conducting slabs 60, 120, 130, 142, and/or 152 provides the ability to account for semiconducting devices of varying heights.
Therefore, according to one embodiment of the invention, a semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.
According to another embodiment of the invention, a method of forming a semiconductor device package includes providing a semiconductor device, affixing a first surface of the semiconductor device to a first surface of a dielectric layer, and affixing a first surface of a conductive shim to the first surface of the dielectric layer. The method also includes disposing a heatspreader on a second surface of the semiconductor device and a second surface of the conductive shim, the heatspreader electrically coupling the semiconductor device to the conducting shim, and forming a metal interconnect structure on a second surface of the dielectric layer. The metal interconnect structure extends through vias formed in the dielectric layer to contact the first surface of the semiconductor device and the first surface of the conductive shim.
According to yet another embodiment of the invention, a power overlay (POL) structure includes an insulating substrate, a power device attached to the insulating substrate via an adhesive layer and an electrically conducting shim attached to the insulating substrate via the adhesive layer. The POL structure further includes an electrically and thermally conducting slab coupled to a top surface of the power device and a top surface of the conducting shim and a metallization layer extending through the insulating substrate. The metallization layer is electrically coupled to contact locations on the first and second surfaces of the power device.
While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
The present application claims priority to U.S. Provisional Patent Application Ser. No. 61/784,834 filed Mar. 14, 2013, the disclosure of which is incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
3586102 | Richard | Jun 1971 | A |
4561011 | Kohara et al. | Dec 1985 | A |
5250843 | Eichelberger | Oct 1993 | A |
5315486 | Fillion et al. | May 1994 | A |
5888884 | Wojnarowski | Mar 1999 | A |
5926696 | Baxter et al. | Jul 1999 | A |
6013356 | Horiguchi | Jan 2000 | A |
6030854 | Mashimoto et al. | Feb 2000 | A |
6104078 | Iida et al. | Aug 2000 | A |
6154366 | Ma et al. | Nov 2000 | A |
6232151 | Ozmat et al. | May 2001 | B1 |
6297550 | Chia et al. | Oct 2001 | B1 |
6306680 | Fillion et al. | Oct 2001 | B1 |
6534859 | Shim et al. | Mar 2003 | B1 |
6558977 | Nakaoka et al. | May 2003 | B2 |
6707671 | Yamashita et al. | Mar 2004 | B2 |
6710463 | Choi | Mar 2004 | B2 |
6777800 | Madrid et al. | Aug 2004 | B2 |
7015640 | Schaepkens et al. | Mar 2006 | B2 |
7190581 | Hassani et al. | Mar 2007 | B1 |
7262444 | Fillion et al. | Aug 2007 | B2 |
7688497 | Danner et al. | Mar 2010 | B2 |
7733554 | Danner et al. | Jun 2010 | B2 |
7763969 | Zeng et al. | Jul 2010 | B2 |
7781882 | Zhong et al. | Aug 2010 | B2 |
7804131 | Cheah et al. | Sep 2010 | B2 |
7999369 | Malhan et al. | Aug 2011 | B2 |
8018056 | Hauenstein | Sep 2011 | B2 |
8097490 | Pagaila | Jan 2012 | B1 |
8304903 | Herbsommer et al. | Nov 2012 | B2 |
8395269 | Kawano et al. | Mar 2013 | B2 |
8409922 | Camacho et al. | Apr 2013 | B2 |
8409926 | Lin et al. | Apr 2013 | B2 |
8581416 | Massie et al. | Nov 2013 | B2 |
8941208 | Chauhan et al. | Jan 2015 | B2 |
8987876 | Gowda et al. | Mar 2015 | B2 |
9001524 | Akre | Apr 2015 | B1 |
9299630 | Gowda et al. | Mar 2016 | B2 |
20010023983 | Kobayashi et al. | Sep 2001 | A1 |
20010030059 | Sugaya | Oct 2001 | A1 |
20020074146 | Okubora | Jun 2002 | A1 |
20020167062 | Narita | Nov 2002 | A1 |
20030077951 | Sturgeon et al. | Apr 2003 | A1 |
20030122232 | Hirano et al. | Jul 2003 | A1 |
20040070087 | Wang | Apr 2004 | A1 |
20040201081 | Joshi et al. | Oct 2004 | A1 |
20050045855 | Tonapi | Mar 2005 | A1 |
20050046079 | Murugan | Mar 2005 | A1 |
20050167849 | Sato | Aug 2005 | A1 |
20050218486 | Morrison et al. | Oct 2005 | A1 |
20050258533 | Kumano et al. | Nov 2005 | A1 |
20060018607 | Rosenberg | Jan 2006 | A1 |
20060044772 | Miura | Mar 2006 | A1 |
20060103005 | Schulz-Harder et al. | May 2006 | A1 |
20060128069 | Hsu | Jun 2006 | A1 |
20060151860 | Islam et al. | Jul 2006 | A1 |
20060166397 | Lau et al. | Jul 2006 | A1 |
20060177098 | Stam | Aug 2006 | A1 |
20060183349 | Farnworth et al. | Aug 2006 | A1 |
20070035033 | Ozguz et al. | Feb 2007 | A1 |
20070138651 | Hauenstein | Jun 2007 | A1 |
20070145547 | McKerreghan et al. | Jun 2007 | A1 |
20070196950 | Shirai et al. | Aug 2007 | A1 |
20070257343 | Hauenstein et al. | Nov 2007 | A1 |
20070262436 | Kweon et al. | Nov 2007 | A1 |
20070295387 | Adriani et al. | Dec 2007 | A1 |
20080006936 | Hsu | Jan 2008 | A1 |
20080122061 | Edwards | May 2008 | A1 |
20080142954 | Hu | Jun 2008 | A1 |
20080164588 | Lee et al. | Jul 2008 | A1 |
20080303125 | Chen et al. | Dec 2008 | A1 |
20090207574 | Chen et al. | Aug 2009 | A1 |
20090291296 | McConnelee et al. | Nov 2009 | A1 |
20100059853 | Lin | Mar 2010 | A1 |
20100230800 | Beaupre et al. | Sep 2010 | A1 |
20100244225 | Sabatini et al. | Sep 2010 | A1 |
20100308453 | Scheid et al. | Dec 2010 | A1 |
20110045634 | Pagaila | Feb 2011 | A1 |
20110233690 | Feiertag et al. | Sep 2011 | A1 |
20110291249 | Chi et al. | Dec 2011 | A1 |
20120014069 | Zeng et al. | Jan 2012 | A1 |
20120270354 | Hooper et al. | Oct 2012 | A1 |
20130043571 | Gowda et al. | Feb 2013 | A1 |
20140029210 | Gowda et al. | Jan 2014 | A1 |
20140061893 | Saeidi | Mar 2014 | A1 |
20140262449 | Gektin | Sep 2014 | A1 |
20150194375 | Gowda et al. | Jul 2015 | A1 |
20170077014 | Gowda et al. | Mar 2017 | A1 |
20170263539 | Gowda et al. | Sep 2017 | A1 |
Number | Date | Country |
---|---|---|
1969383 | May 2007 | CN |
101202259 | Jun 2008 | CN |
06177320 | Jun 1994 | JP |
07321257 | Dec 1995 | JP |
407321257 | Dec 1995 | JP |
11121662 | Apr 1999 | JP |
411121662 | Apr 1999 | JP |
2000049280 | Feb 2000 | JP |
2002050889 | Feb 2002 | JP |
2003258166 | Sep 2003 | JP |
2005223008 | Aug 2005 | JP |
2005228929 | Aug 2005 | JP |
2006278771 | Oct 2006 | JP |
2007521656 | Aug 2007 | JP |
2009059760 | Mar 2009 | JP |
2009076657 | Apr 2009 | JP |
2009130044 | Jun 2009 | JP |
2013042135 | Feb 2013 | JP |
2005051525 | Jun 2005 | WO |
2011103341 | Aug 2011 | WO |
Entry |
---|
Oxford Dictionaries, Wayback Machine, May 2, 2013. |
“Improved Direct Bond Copper (DBC) Substrate for High Temperature Packaging”, Abstract, Virginia Tech Center for Power Electronics Systems, 2008, p. 1, www.cpes.vt.edu/public/showcase/DBC.php. |
Jensen, “Ultra-Thin Moisture Barrier Coatings for Passive Components,” Abstract, Massachusetts Institute of Technology, Jun. 2004, p. 1. |
Yin, “High Temperature SiC Embedded Chip Module (ECM) with Double-Sided Metallization Structure”, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, Dec. 2005, pp. I-XIII and 1-159. |
Kokko et al, “Thermal Cycling of Flip Chips on FR-4 and PI Substrates with Parylene C Coating,” Surface Mount Technology, vol. 22, No. 3, 2010, pp. 42-48. |
Wakharkar et al., “Materials Technologies for Themomechanical Management of Organic Packages”, Intel Technology Journal, vol. 9, Issue 4, Nov. 9, 2005, pp. 309-324. |
Wu et al., “Interface-Adhesion-Enhanced Bi-Layer Conformal Coating for Avionics Application,” Proceedings International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, Mar. 14-17, 1999, pp. 302-310. |
Kaltenpoth et al., “The Effect of PECVD SiN Moisture Barrier Layers on the Degradation of a Flip Chip Underfill Material,” Soldering & Surface Mount Technology, vol. 13, No. 3, 2001, pp. 12-15. |
Huang et al., “Effect of Organic/Inorganic Coating on Moisture Diffusion in a Chip-On-Board Package with Globtop,” Journal of Electronic Materials, 2004, vol. 33, No. 2, 2004, pp. 101-105. |
U.S. Appl. No. 14/665,735, filed Mar. 23, 2015, Arun Virupaksha Gowda et al. |
U.S. Appl. No. 13/211,057, filed Aug. 16, 2011, Arun Virupaksha Gowda et al. |
U.S. Appl. No. 13/561,811, filed Jul. 30, 2012, Shakti Singh Chauhan et al. |
U.S. Appl. No. 13/561,868, filed Jul. 30, 2012, Arun Virupaksha Gowda et al. |
U.S. Appl. No. 15/363,237, filed Nov. 29, 2016, Arun Virupaksha Gowda et al. |
U.S. Notice of Allowance office Action issued in connection with Related U.S. Appl. No. 13/211,057 dated Oct. 9, 2013. |
U.S. Non-Final office Action issued in connection with Related U.S. Appl. No. 13/561,811 dated Apr. 10, 2014. |
U.S. Non-Final office Action issued in connection with Related U.S. Appl. No. 13/561,868 dated Oct. 17, 2014. |
U.S. Non-Final office Action issued in connection with Corresponding U.S. Appl. No. 13/897,638 dated Apr. 24, 2014. |
U.S. Non-Final office Action issued in connection with Related U.S. Appl. No. 13/561,868 dated Mar. 3, 2015. |
U.S. Non-Final office Action issued in connection with Related U.S. Appl. No. 14/165,707 dated Mar. 5, 2015. |
U.S. Non-Final office Action issued in connection with Related U.S. Appl. No. 14/165,725 dated Mar. 16, 2015. |
European Search Report and Opinion issued in connection with corresponding EP Application No. 14159735.1 dated Mar. 27, 2015. |
European Search Report and Opinion issued in connection with corresponding EP Application No. 14159901.9 dated Mar. 27, 2015. |
U.S. Final office Action issued in connection with Related U.S. Appl. No. 13/561,868 dated Jun. 17, 2015. |
U.S. Notice of Allowance office Action issued in connection with Related U.S. Appl. No. 14/165,707 dated Jun. 22, 2015. |
U.S. Notice of Allowance office Action issued in connection with Related U.S. Appl. No. 14/165,725 dated Jun. 22, 2015. |
European Search Report and Opinion issued in connection with corresponding EP Application No. 13177219.6 dated Jun. 24, 2015. |
Unofficial English Translation of Chinese office Action issued in connection with Related CN Application No. 201210291894.5 dated Feb. 15, 2016. |
U.S. Non-Final office Action issued in connection with Corresponding U.S. Appl. No. 14/665,735 dated May 19, 2016. |
Unofficial English Translation of Japanese office Action issued in connection with Related JP Application No. 2012179136 dated May 24, 2016. |
Unofficial English Translation of Taiwan office Action issued in connection with Related TW Application No. 102125294 dated Oct. 12, 2016. |
Taiwan office Action issued in connection with Related TW Application No. 102125293 dated Oct. 26, 2016. |
European office Action issued in connection with Corresponding EP Application No. 14159735.1 dated Nov. 2, 2016. |
Unofficial English Translation of Japanese Search Report issued in connection with Related JP Application No. 2012179136 dated Dec. 2, 2016. |
Machine Translation and Japanese Office Action issued in connection with corresponding JP Application No. 2014048289 dated Feb. 20, 2018. |
Machine Translation and Japanese Office Action issued in connection with corresponding JP Application No. 2014048290 dated Mar. 27, 2018. |
Number | Date | Country | |
---|---|---|---|
20140264800 A1 | Sep 2014 | US |
Number | Date | Country | |
---|---|---|---|
61784834 | Mar 2013 | US |