The present invention relates to a semiconductor component having, on the surface of a semiconductor element, a joining layer made from a joining material containing Bi as an essential ingredient, a semiconductor wafer component, a manufacturing method of the semiconductor component, and a manufacturing method of a joining structure.
A semiconductor component is mounted on a substrate using a soldering material. For example, as a soldering material used for joining a semiconductor component such as an IGBT (Insulated Gate Bipolar Transistor) to a substrate, a soldering material having a composition of Sn-3 wt % Ag-0.5 wt % Cu and having a melting point of 220° C. is generally used.
Thus, as a joining material having a melting temperature higher than 260° C. and containing no lead, a joining material containing 90 wt % or more of Bi (hereinafter referred to as a joining material containing Bi as an essential ingredient) (for example, a material having a composition of Bi-2.5 Ag and having a melting point of 262° C., and a material having a composition of Bi-0.5 Cu and having a melting point of 270° C.) is considered to be suitable. A material containing Zn has also been investigated as the other joining material, but at present, the joining material containing Bi as an essential ingredient is suitable in view of the wettability and the ease of joining. Thus, a power semiconductor module using the joining material containing Bi as an essential ingredient has been proposed (see Japanese Patent Laid-Open No. 2007-281412 (page 24, FIG. 2)).
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However, Bi which is an essential ingredient of the joining material described in Japanese Patent Laid-Open No. 2007-281412 (page 24, FIG. 2) and whose standard formation energy of oxide is −494 kJ/mol is liable to be oxidized. As described above, in order to form the joining structure 501, the molten joining material 502 containing Bi as an essential ingredient is supplied onto the electrode 503, and the semiconductor element 504 is mounted on the joining material 502 so as to be joined to the electrode 503. In this case, on the surface of the molten joining material 502 containing Bi as an essential ingredient and supplied onto the electrode 503, an oxide 505, which is naturally generated by the exposure to the atmosphere, is formed.
For this reason, when the semiconductor element 504 is mounted on the surface of the molten joining material 502, the layer of the oxide 505 is wetly spread on the surface of the semiconductor element 504, and is eventually moved to the outer peripheral edge portion of the joining material 502. However, when air reservoirs exist as shown by the arrows in
In the state where the void 506 is incorporated in the joining material 502, there is a problem that, when stress is repetitively applied to the solidified joining material 502 during the heat cycle, a crack is formed in the joining material 502, so that a failure of the semiconductor component having the joining structure 501 is caused.
The present invention has been made in view of the above-described problem of the conventional semiconductor component. The present invention is directed to a semiconductor component which can reduce the generation of a void in the joining layer consisting of the joining material containing Bi as an essential ingredient, a joining structure configured by joining the semiconductor component to an electrode, a semiconductor wafer component, a manufacturing method of the semiconductor component, and a manufacturing method of the joining structure.
The 1st aspect of the present invention is a semiconductor component comprising:
The 2nd aspect of the present invention is the semiconductor component according to the 1st aspect of the present invention, wherein a height of the projecting section is 5 μm or more to 30 μm or less.
The 3rd aspect of the present invention is a manufacturing method of a semiconductor component, comprising:
The 4th aspect of the present invention is the manufacturing method of the semiconductor component according to the 3rd aspect of the present invention, wherein a thickness of the mask at the hole section corresponds to a height of the projecting section, and
The 5th aspect of the present invention is a manufacturing method of a joining structure formed by joining the semiconductor component according to the 1st aspect of the present invention to an electrode, comprising:
The 6th aspect of the present invention is a semiconductor wafer component comprising:
The 7th aspect of the present invention is a manufacturing method of a joining structure formed by joining the semiconductor component according to the 2nd aspect of the present invention to an electrode, comprising:
An invention relating to the present invention is a joining structure comprising:
Further, another invention relating to the present invention is a manufacturing method of the joining structure of the above-described invention relating to the present invention, the manufacturing method comprising:
In the structure according to the present invention, the joining layer consisting of the joining material containing Bi as an essential ingredient is provided on one surface of the semiconductor element, and the projecting section is formed, for example, on the surface of the joining layer on the side opposite to the surface in contact with the semiconductor element, whereby an air passage is occurred around the projecting section at the time of joining the joining layer to the electrode and thereby the generation of a void which is air surrounded by the oxide of Bi can be suppressed.
The present invention exhibits the effect of reducing the generation of a void in the joining layer consisting of the joining material containing Bi as an essential ingredient.
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In the following, embodiments according to the present invention will be described with reference to the accompanying drawings.
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A semiconductor element 101 is made from Si, and is cut out in a size of 4.5 mm×3.55 mm from a wafer (semiconductor wafer) having a diameter of 6 inches and a thickness of 0.3 mm. The semiconductor element 101 may be made from not only Si but also Ge, and further, may also be made from a compound semiconductor, such as GaN, GaAs, InP, ZnS, ZnSe, SiC and SiGe. Further, as for the size of the semiconductor element 101, a semiconductor element having a large size of 6 mm×5 mm, or a semiconductor element 101 having a small size, such as 3 mm×2.5 mm and 2 mm×1.6 mm, may also be used according to the function of the semiconductor element 101. The thickness of the semiconductor element 101 is not limited to 0.3 mm, and a semiconductor element having a thickness, such as 1.0 mm, 0.5 mm, 0.1 mm and 0.01 mm, may also be used.
A joining layer 102 is made from Bi-2.5 wt % Ag (having a melting point of 262° C.), and one hemispherical projecting section 103 is formed in the central portion of the surface of the joining layer 102 on the side opposite to the side in contact with the semiconductor element 101. Further, an oxide 104, which is naturally generated by the exposure to the atmosphere, is formed on the surface of the joining layer 102 and of the projecting section 103 on the side opposite to the side of the semiconductor element 101.
The thermal conductivity of Bi which is the main component of the joining layer 102 is 9 W/m·K. Thus, when the thickness h of the joining layer 102 is too large, the product performance of the semiconductor component will not be satisfied from the view point of thermal resistance, and when the thickness h of the joining layer 102 is too small, joint failure is caused. From the above, it is preferred that the thickness h of the joining layer 102 is set to about 10 μm or more and about 30 μm or less.
The size of the projecting section 103, which is formed in an approximately hemispherical shape, is set such that the maximum height m in the normal direction is 10 μm on the basis of the surface of the joining layer 102 on the side opposite to the side in contact with the semiconductor element 101 (plane P corresponding to the position indicated by reference character P in
Here, when the projecting section 103 is formed and then exposed to the atmosphere, the layer of the oxide 104 is naturally generated, but the thickness of the layer of the oxide 104 is substantially uniform. Therefore, the height of the projecting section 103 after the formation of the layer of the oxide 104 will be described below under the assumption that the height based on the surface of the layer of the oxide 104 on the side of the electrode 201 (based on the plane Q corresponding to the position indicated by reference character Q in
Note that, since it is only necessary that a passage of the air existing between the joining layer 102 and the electrode 201 (see
Next, while a method for forming the projecting section 103 is described, an example of a manufacturing method of the semiconductor component according to the present invention will be described.
In a joining layer forming step, the joining layers 102 made from a joining material containing Bi as an essential ingredient are formed by electrolytic plating so as to have a desired thickness with respect to the main surface of a semiconductor wafer on which surface a plurality of semiconductor elements are formed.
Then, as shown in
Here, in the mask 601, one or more hole sections 603 are formed in each region corresponding to each position of the plurality of semiconductor elements formed on the main surface 602a of the semiconductor wafer 602. Further, as shown in
Next, after the mask 601 is arranged in the mask arranging step, the joining material containing Bi as an essential ingredient is formed into the shape of the projecting section 103 by electrolytic plating. When the mask 601 is removed after the electrolytic plating, the projecting section 103 is formed on the surface of the joining layer 102 on the side opposite to the side in contact with the semiconductor element 101.
Note that the height of the projecting section 103 can be adjusted by controlling the time during which the semiconductor wafer 602 with mask 601 arranged thereon is subjected to the electrolytic plating.
Next, a dicing sheet serving as a protective sheet is bonded on the side of the main surface 602a of the semiconductor wafer 602 on which side the projecting section 103 is formed. Then, in a cutting step, the semiconductor wafer 602 is cut in a predetermined size by a dicing device. The semiconductor wafer 602, to which the dicing sheet is bonded, is an example of a semiconductor wafer component according to the present invention.
b) is a plan view showing the surface of the joining layer on the side opposite to the surface in contact with the semiconductor element. Since the projecting section 103 is formed at one place, an air passage is occurred around the projecting section 103 at the time of joining to the electrode, so that the generation of a void which is the air surrounded by the oxide of Bi can be prevented.
c) is a plan view which shows the surface of the joining layer 102 on the side opposite to the surface in contact with the semiconductor element 101, and which shows a state where five projecting sections 103 are formed on the plane of the oxide 104. The distance L, shown in
d) shows the state of wet-spreading of the joining layer at the time when the joining layer is molten from the projecting sections 103 shown in
In the following, an example of a manufacturing method of the joining structure according to the present invention will be described with reference to
a) shows an arranging step in which a semiconductor component 100 is arranged in the vicinity of the electrode 201 of a lead frame 202. That is, in this step, the semiconductor component 100 is held by a holding device (not shown) so that the surface of the joining layer 102 with the projecting section 103 formed thereon faces the electrode 201 at a predetermined distance.
Further, as shown in
b) is a schematic diagram showing a state where the semiconductor component 100 is held above the electrode 201 by the holding device when the lead frame 202 is heated to at least the temperature of 262° C. which is the melting start temperature of the joining layer 102.
When the joining layer 102 is to be joined to the electrode 201 as shown in
In this way, the time difference is provided in the timing of melting of the joining layer 102, and thereby the oxide 104 is pushed out to the outer peripheral edge portion of the joining layer 102 as shown in
d) is a schematic diagram showing the joining structure in which the semiconductor component and the lead frame are joined to each other. As shown in
Therefore, the present embodiment has the feature that the oxide, which exists on the outer peripheral edge portion of the joining layer 102, is distributed more on the outer peripheral edge portion (portion corresponding to the outer peripheral surface 102a) on the side of the electrode 201 as compared with the outer peripheral edge portion on the side of the semiconductor element 101.
With this configuration, when an electrode is joined to a semiconductor component which includes a semiconductor element, and a joining layer made from a joining material containing Bi as an essential ingredient and provided on one surface of the semiconductor element, and in which a projecting section is formed on the surface of the joining layer on the side opposite to the surface in contact with the semiconductor element, the peripheral area of the projecting section serves as an air passage, so that the generation of a void which is the air surrounded by the oxide of Bi can be suppressed or prevented.
In the semiconductor component according to embodiment 1, the projecting section 103 is formed on the surface of the joining layer on the side opposite to the surface in contact with the semiconductor element, and is formed in a hemispherical shape whose maximum height m in the normal direction is 10 μm on the basis of the plane P (see
However, it is also conceivable that, when the height of the projecting section is set extremely low, the air passage is easily closed. Thus, the relationship between the height of the projecting section and the presence/absence of generation of the void was verified.
The void generation rate (%) is expressed as follows:
Void generation rate (%)=(void area)÷surface area of joining material×(100) (%)
The void area in an IGBT, in which the semiconductor component was joined and assembled, was measured by a transmission X-ray apparatus.
As can be seen from the results of
On the other hand, in the case where the height of the projecting section is set to 25 μm, the void generation rate is also 0%, but the case where the height of the projecting section is set higher than this value will be described.
For example, in the case where the height of the projecting section was set to 30 μm, the void generation rate was 0%. However, when the height of the projecting section exceeds 30 μm, and when the semiconductor wafer is bonded to a dicing sheet so as to be cut by a dicing device in the cutting step as described above, the projecting section 103 causes an air bubble to be generated between the dicing sheet and the bonding surface of the joining layer 102 bonded to the dicing sheet. When dicing is performed in this state, cutting chips generated during the dicing is trapped in the air bubble and contaminates the surface of the joining layer, so that a junction failure is caused. Thus, it is not preferred that the height of the projecting section is set to exceed 30 μm. From the above results, it is preferred that the height of the projecting section is set to 5 μm or more to 30 μm or less.
In the above-described verification, a semiconductor component using the joining material having the composition of Bi-2.5 wt % Ag was used, but the effectiveness of the projecting section was also verified by using a joining material having another composition.
Table 1 shows the results of the measurement of void generation rate performed by changing the kind of the joining layer, the height of the projecting section, and the number of the projecting sections. Also when no projecting section was formed, the verification was performed for reference (comparison example 1).
As can be seen from table 1, also when Bi-1.0 wt % Ag-0.5 wt % Cu was used as the joining material, and 100 wt % Bi was used as the joining material, the void generation rate was 0%. It was seen from these results that, when a material containing Bi as an essential ingredient was used as the joining material, the generation of a void could be prevented. When the height of the projecting section was set to 5 μm or more to 30 μm or less, the void generation rate was 0%. Further, when the above-described arrangement conditions of the projecting sections were satisfied, the void generation rate was 0% without being influenced by the number of the projecting sections. Further, in comparison example 1 with no projecting section, the void generation rate was 39%, and hence, it is hard to say that the quality of comparison example 1 is stable.
With this configuration, when an electrode is joined to a semiconductor component which includes a semiconductor element, and a joining layer made from a joining material containing Bi as an essential ingredient and provided on one surface of the semiconductor element, and in which a projecting section having a height of 5 μm or more to 30 μm or less is formed on the surface of the joining layer on the side opposite to the surface in contact with the semiconductor element, an air passage is occurred around the projecting section and thereby the generation of a void which is the air surrounded by the oxide of Bi can be prevented.
Since an air passage occurs around the projecting section and thereby the generation of a void which is the air surrounded by the oxide of Bi is prevented, it is also conceivable that the size of the projecting section for preventing the generation of a void relates to the volume of the projecting section. This is because, when a fixed volume of space is maintained around the projecting section, the space serves as an air passage.
Further, in the above-described embodiment, a case where the number of the projecting section 103 is one is mainly described. However, the embodiment according to the present invention is not limited to this, and a plurality of projecting sections 103 may also be provided. Particularly, in the case where three or more projecting sections 103 are formed so as to support the semiconductor element 101, it is possible to prevent the semiconductor component 100 from inclining at the time when the semiconductor component 100 is mounted on the electrode.
Further, in the above-described embodiment, a case where the material of the projecting section 103 has the same composition as the material of the joining layer 102 is described. However, the embodiment according to the present invention is not limited to this, and a material whose composition is different from the composition of the material of the joining layer 102 and whose melting point is the melting start temperature or lower of the material of the joining layer 102 may also be used as the material of the projecting section 103. For example, a material, such as a Bi—Sn alloy (melting start temperature: 139° C.), a Sn—In alloy (melting start temperature: 120° C.), or a Bi—In alloy (melting start temperature: 73° C.), can be used as the material of the projecting section 103. Thereby, the melting can be surely started from the projecting section 103.
Further, in the above-described embodiment, a case where the projecting section 103 is formed in a part of the surface of the joining layer 102 is described. However, the embodiment according to the present invention is not limited to this, and for example, the whole surface of the joining layer 102 on the side of the electrode 201 may also be formed into a pyramid shape, such as a quadrangular pyramid shape, and a conical shape, which has the vertex thereof in the center of the surface. Even in this case, the same effect as that described above can be exhibited because the surface of the joining layer 102 on the side of the electrode 201 is inclined toward the outer peripheral side whereby the time difference is generated in the melting timing and also the air passage for releasing the air is secured.
Further, in the above-described embodiment, a configuration is described in which, while the semiconductor component 100 is held by the holding device, the semiconductor component 100 is moved gradually downward in accordance with the spreading state of the molten area. However, the embodiment according to the present invention is not limited to this, and for example, a configuration may also be used in which the semiconductor component 100 is mounted on the electrode 201 by the holding device and then the semiconductor component 100 is released from the holding device. In this case, the semiconductor component 100 is moved gradually downward by its own weight.
Further, in the above-described embodiment, a case where the projecting section is provided on the surface of the joining layer is described. However, the embodiment according to the present invention is not limited to this, and for example, a configuration in which one or more projecting sections are provided on the surface of the electrode may also be used. In this case, the projecting section on the electrode can be easily formed by pressing the electrode with a press die.
Further, a manufacturing method of the joining structure 703 shown in
The semiconductor component, the joining structure, the semiconductor wafer component, the manufacturing method of the semiconductor component, and the manufacturing method of the joining structure, according to the present invention, can reduce the generation of a void in the joining layer consisting of the joining material containing Bi as an essential ingredient, and hence can be applied for use in semiconductor packages of a power semiconductor, a small power transistor, and the like.
Number | Date | Country | Kind |
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2009-172709 | Jul 2009 | JP | national |
This application is a U.S. national phase application of PCT International Patent Application No. PCT/JP2010/004655 filed Jul. 20, 2010, claiming the benefit of priority of Japanese Patent Application No. 2009-172709 filed Jul. 24, 2009, all of which are incorporated by reference herein in their entirety.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2010/004655 | 7/20/2010 | WO | 00 | 10/11/2011 |