SEMICONDUCTOR DEVICE

Abstract

Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing one example of a structure of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is an enlarged partial sectional view showing the structure of A portion shown in FIG. 1;

FIG. 3 is an enlarged partial plan view showing one example of the internal structure of the semiconductor device shown in FIG. 1 as seen through a resinous member;

FIG. 4 is a backside view showing one example of the structure of the semiconductor device shown in FIG. 1;

FIG. 5 is a plan view showing one example of a conductor pattern at the main surface of a wiring board incorporated in the semiconductor device shown in FIG. 1

FIG. 6 is a backside view showing one example of a conductor pattern at the back surface of the wiring board shown in FIG. 5;

FIG. 7 is an enlarged partial plan view showing the structure of B portion shown in FIG. 5;

FIG. 8 is an enlarged partial backside view showing the structure of B portion shown in FIG. 6;

FIG. 9 is a view showing the conductor pattern wherein the conductor patterns at the main surface and at the back surface on the B portion shown in FIG. 5 are overlapped with each other;

FIG. 10 is an enlarged partial plan view showing a structure of C portion shown in FIG. 9;

FIG. 11 is a partial sectional view showing the structure of the cross-section cut along a D-D line in FIG. 10;

FIG. 12 is a conceptual view showing one example of a method of a shock test for the semiconductor device according to the present invention;

FIG. 13 is a conceptual view showing one example of a method of a drop test for the semiconductor device according to the present invention;

FIG. 14 is an enlarged partial plan view showing one example of a positional relationship between bonding leads and through-holes on a conductive pattern of a wiring board incorporated in a semiconductor device according to a comparative example;

FIG. 15 is a partial cross-sectional view showing a structure of a semiconductor device according to a comparative example; and

FIG. 16 is an enlarged partial sectional view showing a structure of a through-hole in FIG. 15.

Claims

1. A semiconductor device comprising: a wiring board having a main surface, a back surface opposite to the main surface, a plurality of wire bonding portions formed over the main surface, a plurality of land portions formed over the back surface, and a plurality of via portions that electrically connect the wire bonding portions and the corresponding land portions;a semiconductor chip mounted over the main surface of the wiring board;a plurality of wires that electrically connect a plurality of electrodes of the semiconductor chip with the wire bonding portions formed over the main surface of the wiring board;a resinous member that encapsulates the semiconductor chip and the wires; anda plurality of external terminals connected to the land portions,wherein the via portions include a first via portion arranged as extended by extension wirings that are connected to the land portions, and a second via portion arranged over the land portions.

2. A semiconductor device according to claim 1, wherein the second via portion is arranged as sandwiched by the first via portions.

3. A semiconductor device according to claim 1, wherein the wire bonding portions are arranged in two rows at the peripheral edge portion and at the inside of the peripheral edge portion over the main surface of the wiring board, and the land portions are arranged in five rows at the outer peripheral portion over the back surface of the wiring board.

4. A semiconductor device according to claim 3, wherein the second via portion is arranged over the land portions over the second row from the outer side among the land portions in five rows.

5. A semiconductor device according to claim 1, wherein the land portions arranged immediately below the wire bonding portions are connected to the first via portion through the extension wirings.

6. A semiconductor device according to claim 1, wherein, of the land portions, the land portions arranged at the outermost periphery are connected to the first via portion via the extension wirings.

7. A semiconductor device according to claim 1, wherein the first via portion is arranged over the extension line of the diagonal line of the semiconductor chip over the wiring board.

8. A semiconductor device according to claim 1, wherein the wiring board has a two-layer wiring structure in which conductive patterns are formed over its main surface and its back surface.

9. A semiconductor device according to claim 1, wherein the via portions have a through-hole and a conductive portion arranged in the through-hole.

10. A semiconductor device according to claim 1, wherein, supposing that the arrangement pitch between the adjacent wire bonding portions over the same row is defined as P, the diameter of the via portion is defined as L, and the diameter of the land portion is defined as M, the relationship of P<L<M is established.

11. A semiconductor device according to claim 1, wherein the external terminals are soldering balls.