Semiconductor Package and Manufacturing Method Therefor

Abstract

A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side view of the entire structure of a semiconductor package according to one embodiment of the present invention;

FIG. 2 is an enlarged cross-sectional view of a multilayer printed wiring board and a bump terminal in FIG. 1;

FIG. 3 is a perspective view of the bump terminal in FIGS. 1 and 2;

FIG. 4 is a plan view of a reverse face wiring pattern to be bonded to the bump terminal in FIG. 3;

FIG. 5 is a diagram showing a modification of the multilayer printed wiring board according to the embodiment;

FIG. 6 is a plan view of a reverse face wiring pattern to be bonded to a bump terminal in FIG. 5;

FIG. 7A is a diagram showing another modification of the multilayer printed wiring board according to the embodiment;

FIG. 7B is a diagram showing an additional modification of the multilayer printed wiring board according to the embodiment;

FIG. 8 is a diagram showing a modification of the reverse face wiring pattern to be bonded to the bump terminals according to the embodiment;

FIG. 9 is a diagram showing a modification of the bump terminal according to the embodiment;

FIG. 10 is a diagram showing another modification of the bump terminal according to the embodiment;

FIG. 11 is a perspective view of a bump terminal molding die used for a method for manufacturing a semiconductor package shown in FIG. 1;

FIG. 12 is a cross-sectional view of the bump terminal molding die shown in FIG. 11;

FIG. 13 is a cross-sectional view of a process for using electroless plating to deposit a copper coating on the bump terminal molding die in FIGS. 10 and 12;

FIG. 14 is a cross-sectional view of a process for using electrolytic plating to form a copper coating following the process in FIG. 13;

FIG. 15 is a cross-sectional view of a resin filling process performed following the process in FIG. 14;

FIG. 16 is a cross-sectional view of a process for removing the copper coating following the process in FIG. 15;

FIG. 17A is a plan view of a mask to be used for the process for applying a solder paste following the process in FIG. 16;

FIG. 17B is a cross-sectional view of the solder applying process;

FIG. 18A is a bottom view of a multilayer printed wiring board used for the method for manufacturing the semiconductor package shown in FIG. 1;

FIG. 18B is a cross-sectional view taken along line X-X;

FIG. 19 is a cross-sectional view of a process for bonding bump terminals following the process in FIG. 17B;

FIG. 20 is a cross-sectional view of a process for removing the bump terminal molding die following the process in FIG. 19;

FIG. 21 is a perspective view of insulating rods used for a semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 22 is a perspective view of a process for forming a copper coating on the insulating rods shown in FIG. 21;

FIG. 23 is a perspective view of a process for cutting off both ends of the insulating rods following the process in FIG. 22;

FIG. 24 is a perspective view of cutting the insulating rods into a plurality of segments following the process in FIG. 23;

FIG. 25A is a bottom view of the multilayer printed wiring board;

FIG. 25B is a cross-sectional view taken along line Y-Y in FIG. 25A;

FIG. 26A is a plan view of a mask to be used for a process for applying a solder paste to the multilayer printed circuit board shown in FIG. 25;

FIG. 26B is a cross-sectional view of the solder applying process in FIG. 26A;

FIG. 27 is a perspective view of a positioning jig used for positioning bump terminals shown in FIG. 24;

FIG. 28 is a cross-sectional view of a process for mounting the positioning jig on the multilayer printed wiring board following the process shown in FIG. 26B;

FIG. 29 is a cross-sectional view of a process for fitting the bump terminals in the through holes of the positioning jig following the process in FIG. 28;

FIG. 30 is a cross-sectional view of a process for removing the positioning jig following the process in FIG. 29;

FIG. 31A is a plan view of a mask to be used for a process for applying a solder paste to a motherboard in order to mount, on the motherboard, a semiconductor package manufactured during the process shown in FIGS. 21 to 30;

FIG. 31B is a cross-sectional view of the solder applying process in FIG. 31A;

FIG. 32 is a cross-sectional view of a process for bonding the semiconductor package to the motherboard following the process in FIG. 31;

FIG. 33 is a cross-sectional view of an underfill filling process following the process in FIG. 32; and

FIG. 34 is a cross-sectional view of the structure for a multilayer printed wiring board and a bump terminal for a conventional semiconductor package.

Claims

1. A semiconductor package comprising: a printed wiring board;an integrated circuit chip mounted on an obverse face of said printed wiring board; anda plurality of bump terminals mounted on a reverse face of said printed wiring board,wherein each of said bump terminals includes an insulating core having a flat face directed toward the reverse face of said printed wiring board, anda conductive coating formed on the outer surface of said bump terminal, except for the flat face of said insulating core, and bonded to the reverse face of said printed wiring board.

2. A semiconductor package according to claim 1, wherein said printed wiring board includes: an insulating board;an obverse face wiring pattern formed on the obverse face of said insulating board and electrically connected to said integrated circuit chip;an internal wiring pattern embedded in said insulating board and fabricated with clearance holes;a reverse face wiring pattern formed on the reverse face of said insulating board and electrically connected to said bump terminals; andvias located into said clearance holes and electrically connected to said reverse face wiring pattern.

3. A semiconductor package according to claim 2, wherein said reverse face wiring pattern includes: via lands, provided at predetermined locations, opposite the flat faces of said insulating cores, and electrically connected to said reverse face wiring pattern, and wherein said vias and said clearance holes are arranged on said via lands.

4. A semiconductor package according to claim 3, wherein said clearance holes are smaller than the flat faces of said insulating cores.

5. A bump terminal, used for a semiconductor package including a printed wiring board and an integrated circuit chip mounted on the obverse face of said printed wiring board, comprising: an insulating core having a flat face to be directed toward a reverse face of said printed wiring board; anda conductive coating formed on the outer surface of said bump terminal, except for the flat face of said insulating core.

6. A manufacturing method for a semiconductor package including a printed wiring board and an integrated circuit chip mounted on an obverse face of said printed wiring board, comprising the steps of: preparing said printed wiring board;preparing a plurality of bump terminals, each including an insulating core, having a flat face to be directed toward the reverse face of said printed wiring board, and a conductive coating, formed on the outer surface of said bump terminal, except for the flat face of said insulating core; andmounting said bump terminals on the reverse face of said printed wiring board.

7. A semiconductor package manufacturing method according to claim 6, wherein said step of preparing said bump terminals includes the steps of: preparing a die having a plurality of recessed portions formed in a main face;depositing a conductive coating on an internal surfaces of said recessed portions; andthereafter, filling said recessed portions with an insulating material.

8. A semiconductor package manufacturing method according to claim 7, wherein said step of mounting said bump terminals includes the steps of: applying solder, at the least, either to the reverse face of said printed wiring board or to the end faces of said conductive coatings that appear on the same plane as the flat faces of said insulating cores;thereafter, aligning the die and said printed wiring board so that the main face of the die is directed toward the reverse face of said printed wiring board;sequentially heating the solder for a predetermined period of time; andafter the solder, melted by the heating, has solidified, removing the die.

9. A semiconductor package manufacturing method according to claim 6, wherein said step of preparing said bump terminals include the steps of: preparing insulating rods;depositing a conductive coating on the side faces of said insulating rods; andthereafter, cutting said insulating rods.

10. A semiconductor package manufacturing method according to claim 9, wherein said step of mounting said bump terminals includes the steps of: applying solder, at the least, either to the reverse face of said printed wiring board or to the end faces of said conductive coatings that appear on the same plane as cut faces of said insulating rods;thereafter, mounting said bump terminals on the reverse face of said printed wiring board so that the cut faces of the insulating rods are directed toward the reverse face of said printed wiring board; andsequentially heating the solder for a predetermined period of time.

11. A semiconductor package manufacturing method according to claim 10, further comprising a step of: preparing a jig having a plurality of through holes,wherein said step of mounting said bump terminals includes the steps of mounting the jig on the reverse face of said printed wiring board, and fitting said bump terminals into the through holes, andwherein a step of removing the jig, after the solder melted by heating has solidified, is also included.