BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a sectional view of a ball grid array package using a conventional wire bonding process;
FIG. 2 is a sectional view of a ball grid array package using a conventional flip chip bonding process;
FIG. 3 is a sectional view of a conventional wafer level package; and
FIGS. 4A to 4D are sectional views illustrating the stepwise manufacturing of a semiconductor package according to an embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the invention shall be described in detail with reference to the accompanying drawings hereinafter.
FIGS. 4A to 4D are sectional views illustrating the stepwise manufacturing of a semiconductor package according to an embodiment of the invention.
With reference to FIG. 4A, metal pads 42 are provided on a semiconductor substrate 41 on which a predetermined element structure to manufacture a semiconductor element is formed. A plurality of the metal pads 42 are made of, for example, aluminum (Al) or copper (Cu), and spaced apart by predetermined intervals. Furthermore, a complex insulating protection film 43 is provided on the entire structure, and then selectively etched away so as to expose a predetermined portion of the metal pads 42. The complex insulating protection film 43 may be formed of a complex multilayered film of an oxide film and a nitride film. After a diffusion prevention film 44 is provided on the entire structure, a portion of the diffusion prevention film 44 except for areas on which bump electrodes are to be formed is removed. The diffusion prevention film 44 is provided in order to prevent a reaction between the metal pads 42 and the bump electrodes to be formed. The diffusion prevention film 44 is formed of one or more selected from a laminate of tantalum nitride (TaN) and tantalum (Ta), a laminate of titanium nitride (TiN) and titanium (Ti), a layer of titanium tungsten (TiW), a laminate of gold (Au) and titanium tungsten (TiW), and a laminate of copper (Cu) and titanium tungsten (TiW). In addition, bump electrodes 45 are formed by using a metal layer so as to be electrically connected to the metal pads 42. The bump electrodes 45 are selected from a single layer of tin (Sn); a laminate of copper (Cu) and tin (Sn); a laminate of copper (Cu) and a metal alloy (alloy of tin (Sn) and silver (Ag); a laminate of chromium (Cr), a metal alloy (alloy of chromium (Cr) and copper (Cu)), and copper (Cu); a laminate of titanium tungsten (TiW) and copper (Cu); and a laminate of a metal alloy (alloy of nickel (Ni) and vanadium (V)), copper (Cu), and tin (Sn). Otherwise, the bump electrode 45 are made of a metal alloy including one or more selected from metal elements such as copper (Cu), tin (Sn), lead (Pb), chromium (Cr), titanium (Ti), titanium tungsten (TiW), nickel (Ni), vanadium (V) and so forth. In this connection, a reflow process is performed at a high temperature of 250° C. or more for improving adhesion strength between substances constituting the bump electrodes 45 and for a bumping process. For example, after an electroplating process to form copper, and a screen printing process to form metal substance provided on copper are performed, the reflow process is performed at a high temperature of 250° C. or more.
With reference to FIG. 4B, the semiconductor substrate 41 on which the pad electrodes 42, the complex insulating protection films 43, the diffusion prevention films 44, and the bump electrodes 45 are formed is sawed so that the bump electrodes 45 may not be damaged. Thereby, individual semiconductor chips 40 are created.
With reference to FIG. 4C, upper surfaces of the bump electrodes 45 of each semiconductor chip 40 are taped with a cover tape 46. In addition, a passivation film 47 is made of a polymer-based substance including polymide or parylene at a room temperature of 30° C. or more. Alternatively, the passivation film 45 may be made of an insulating substance having high dielectric constant, moisture resistance, and thermal conductivity. Thereby, the passivation film 47 is provided on the entire structure other than the upper surfaces of the bump electrodes 45 that are taped with the cover tape 46. Furthermore, moisture resistance and endurance to physical damage of the semiconductor chip 40 are improved. In connection with this, the thickness of the passivation film is controlled according to an operation condition of each of the elements. For example, when an operation voltage is less than 2200 V, the passivation film 47 is formed with a thickness of 50 μm or less. Meanwhile, when the passivation film 47 is provided by using plasma discharging, the passivation film is formed at a low temperature of 150° C. or less. The passivation film 47 may be formed by vacuum deposition processes such as evaporation, chemical vapor deposition (CVD), or plasma enhanced CVD, wherein raw materials constituting the passivation film are vaporized (10E-2 Torr or less) and deposited in a vacuum. Alternatively, the passivation film 47 may be formed by methods including wet adsorption process such as a sol-gel process. Thereby, the passivation film can be formed on a front surface, a rear surface and even on a lateral surface of the small semiconductor chip so that the surfaces can thoroughly be protected from an outside environment.
With reference to FIG. 4D, the cover tape 46 is removed after the passivation film 47 is formed. Thereby, a chip scale package (CSP), where the passivation film 47 is provided on the entire surfaces of the semiconductor chip 40 except the upper surfaces of the bump electrodes 45, is manufactured.
Meanwhile, in the above-mentioned embodiment, a description is specifically given for an exemplification where the metal pads are connected directly to the bump electrodes. However, the invention is not limited thereto, but may be applied to various types of package processes. In another embodiment of the invention, after metal wiring lines are formed to be connected to metal pads, bump electrodes are provided to be connected to the metal wiring lines. A description thereof will be given.
A plurality of metal pads is provided on an upper surface of a semiconductor substrate on which formation of a predetermined structure for elements is completed. After a first complex insulating protection film is formed thereon, a predetermined area of the first complex insulating protection film is removed so as to expose the metal pads. In addition, a metal substance such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or titanium tungsten (TiW) is applied thereonto, and then selectively etched to form metal wiring lines. Next, after a second complex insulating protection film is provided thereon, the second complex insulating protection film is removed from an area on which the bump electrodes are to be formed so as to expose a predetermined portion of the metal wiring lines. After a diffusion prevention film is provided thereon, a predetermined area of the diffusion prevention film is etched so that the diffusion prevention film remains only on the area on which the bump electrodes are to be formed. Furthermore, the bump electrodes are provided to be connected to the metal wiring lines through the diffusion prevention film. After the semiconductor substrate including the resulting structure is sawed to form individual semiconductor chips, upper surfaces of the bump electrodes are covered with a cover tape or any other means. And then a passivation film is provided on the entire structure including an upper surface, a bottom surface, and a lateral surface of the semiconductor chip. Subsequently, the cover tape is removed from the upper surfaces of the bump electrodes.
As described above, in the present invention, after an upper surface of a bump electrode is taped with a cover tape, a passivation film can be formed on an entire surface of a semiconductor chip, which has a small space and small size, including even a lateral surface thereof. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.
In addition, the passivation film is formed of a polymer-based substance including polymide or parylene; or an insulating substance having high dielectric constant, moisture resistance, and thermal conductivity. Further, the passivation film is formed at around room temperature of 30° C. or more, which allows a stable low temperature. Accordingly, reliability of elements is ensured, the scope of the material selection is broadened, and cost reduction is also possible.
Meanwhile, since the thickness of the passivation film can be controlled according to the level of external operation voltage and desired protection voltage, it is possible to perform a package process where a minimum size and high reliability can be ensured at minimum cost.
Patent Application
20070296081
