Patent Application
20110294262
This invention relates to a manufacturing method of semiconductor package. Specifically the invention relates to a semiconductor packaging process with improved die attach method suitable for ultrathin chips package.
In a trend to develop miniature semiconductor chip packages, it is desirable to minimize the thickness of semiconductor wafers to achieve ultrathin chips. This is especially true for vertical semiconductor devices such as vertical power semiconductor devices in that a thick substrate comes with higher substrate resistance therefore increases the overall conduction loss of the device. However, during the package and manufacture process of semiconductor chips, a silicon wafer requires substantial thickness to provide sufficient mechanical strength to avoid wafer or chip breakage during the manufacture process, which could greatly impact the yield in wafer backside processing and in die attach process when grinding the wafer to 100 micron and below.
During die attach process of vertical semiconductor device chip, the semiconductor chips are attached onto a lead frame or a wiring substrate through conductive epoxy; as the epoxy has a very small contact angle with silicon and at the same time due to the migration effect of silver filler, in the traditional packaging process, the conductive epoxy is easy to adhere to the silicon base of the semiconductor chips and climb to the top surface of the semiconductor chip causing short circuit of the integrated circuit, and damaging the electrical performance of the semiconductor chips.
Further, in case the chip is thin, a small movement of the chip during assembly process will cause the conductive epoxy overflow onto the surfaces of the semiconductor chips thereby causing difficulty in the subsequent wire bonding process and resulting in non-stick or incomplete bond . . . In the subsequent molding process, incomplete bond will cause ball lift of the bond wire from the bond pad rendering the device inoperable.
Efforts have been focusing on improving the process to provide ultra thin wafers. For example, in the patent application number US2006/0035443A1 Hsu, et al. disclose a method for partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points then chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Next the method cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. The disclosure helps to provide ultra thin chips but does not provide improvement in die attach. Therefore it is desirable to develop a process that is capable of providing ultra thin wafer and improve the ultra thin chip die attach process.
In order to resolve the technique problems, this invention provides a wafer thinning and die attach method for ultrathin wafers with the advantages of low cost, simple production and manufacture process; moreover, the method effectively improves the product yield and improves the performance of circuit on the chip.
This invention provides a die attach method used on ultrathin wafer technique, which comprises the following steps:
Providing a semiconductor wafer having a wafer frontside and a wafer backside, wherein a plurality of integrated circuit chips (IC chips) formed on the wafer frontside;
Providing a bonding layer;
Providing a supporting substrate and adhering the supporting substrate onto the wafer frontside through the bonding layer;
Grinding the wafer backside with the supporting substrate and the wafer bonded together;
Cutting the wafer and the supporting substrate into the plurality of chip combos each having a substrate piece bonded to a top surface of an IC chip;
Attaching a bottom of the IC chip on a lead frame thereof; and
Removing the substrate piece from the top surface of the IC chip.
In one embodiment the method further comprises a step of wafer backside process after grinding the wafer backside, wherein the wafer backside process includes backside etching, backside evaporating, backside implantation as well as backside laser annealing.
In one embodiment the bonding layer is a thermal release double-side adhesive tape with one side of the thermal release double-side adhesive tape comprises a pressure-sensitive adhesive bonding layer and the other surface comprises a thermal release adhesive bonding layer; wherein the pressure-sensitive adhesive bonding layer being adhered onto the supporting substrate and the thermal release adhesive bonding layer adhered onto the wafer frontside. In anther embodiment the bonding layer is a UV release double-side adhesive tape with one side of the UV release double-side adhesive tape comprises a UV self-releasing adhesive layer and the other side comprises a UV releasing assisted adhesive layer; wherein the UV releasing assisted adhesive layer being adhered onto the supporting substrate and the UV self-releasing adhesive layer adhered onto the wafer frontside.
In one embodiment the step of removing the substrate piece from the top surface of the IC chip further comprising a step of heating the bonding layer to release the bonding layer from the IC chip. In another embodiment the step of removing the substrate piece from the top surface of the IC chip further comprising a step of UV radiating the bonding layer to release the bonding layer from the IC chip.
In another embodiment the step of grinding the wafer backside further grinds the wafer backside to a wafer thickness of less than or equal to 100 micron.
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Compared to the known practice of sticking the semiconductor chips 400a on the lead frame without the supporting substrate, when the thickness of the semiconductor chip 400a is 100 micron or below, the fragility of semiconductor chip 400a alone could cause technical difficulty during the processes of cutting and die attach. The substrate piece 420a of the supporting substrate therefore enhances the mechanical strength of the semiconductor chip 400a so as to avoid the semiconductor chip 400a from cracking during the die attach process.
Further as each of the chip combo 440 comprises the substrate piece 420a of the supporting substrate bonded by the bonding layer piece 410a of the bonding layer to the top surface of the semiconductor chip 400a, when the backside of the semiconductor chip 400a is affixed onto the lead frame 460 through the conductive epoxy areas 450, the substrate piece 420a of the supporting substrate and the bonding piece 410a of the bonding layer cover the integrated circuit disposed at the frontside of the semiconductor chip 400a so as to avoid the conductive epoxy from contacting the integrated circuit area of the semiconductor chip 400a caused by over flow of conductive epoxy due to over supply epoxy or lateral movement of the semiconductor chip 400a in the conductive epoxy areas.
The substrate piece 420a of the supporting substrate and the bonding piece 410a of the bonding layer can be moved from each chip combo 440 after the conductive epoxy areas 450 are cured so as to finish die attach process to obtain an assembly of semiconductor chips 400a attached to die pad of lead frame 460 as shown in
The assembly shown in
Providing a wafer that comprises a wafer frontside and a wafer backside with a plurality of integrated circuit chips formed on the wafer frontside; providing a bonding layer; providing a supporting substrate and attaching the supporting substrate to the wafer frontside through the bonding layer; grinding the wafer backside to reduce wafer thickness with the supporting substrate bonding on top of the wafer; optionally implementing wafer backside processing on the thinned wafer backside so as to form a device backside electrode; adhering the bottom of the wafer onto a cutting film with the supporting substrate bonded on top of the wafer and cutting through the wafer and the supporting substrate so as to form a plurality of die combo each comprising a semiconductor chip with a substrate piece of the supporting substrate sticking on top of the semiconductor chip through a bonding piece of the bonding layer; providing a lead frame with a die pad and adhering a die combo onto the lead frame with the bottomed of the semiconductor chip connected to the die pad; removing the substrate piece and the bonding piece from the top surface of the semiconductor chip; wire bonding the chip to the lead frame and encapsulating the chip with molding compound.
Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.
