Patent Application
20240258276
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0010396, filed in the Korean Intellectual Property Office on Jan. 26, 2023, the entire contents of which are incorporated herein by reference.
The present disclosure relates to semiconductor packages and a method for fabricating the same.
The semiconductor industry has been seeking to improve integration density such that more passive or active devices can be integrated in a given area. However, in the process, the development of technology for dramatically reducing circuit line widths in the semiconductor front-end process gradually faced limitations. For this reason, the semiconductor industry has tended to develop semiconductor packaging technologies capable of realizing high integration density to supplement the limitations of the semiconductor front-end process. As one of the semiconductor packaging technologies developed depending on this tendency, package-on-package (POP) for stacking an upper semiconductor package on top of a lower semiconductor package is well known.
The existing package-on-package (POP) technology is completed through a process of forming a lower semiconductor package by mounting a semiconductor chip on a front side redistribution layer (FRDL) and encapsulating the semiconductor chip (for example, a system-on-chip (SOC)) with a molding material, and forming a back side redistribution layer (BRDL) on the lower semiconductor package, and connecting an upper semiconductor package (for example, a memory package) to the upper part of the lower semiconductor package through the back side redistribution layer (BRDL).
A system-on-chip (SOC) which is included in a lower semiconductor package of the package-on-package (POP) technology is one semiconductor chip having individual semiconductors, such as microprocessors, memory semiconductors, digital signal processing chips, and wireless modems, integrated therein. Since a number of functions are integrated in one semiconductor chip to drive all of the applications and control and manage system devices, a number of interface devices, and so on, if a system-on-chip (SOC) is used, it is possible to reduce the size of a semiconductor package and minimize power which is consumed in the semiconductor package, as compared to when the existing individual semiconductors are used.
However, in the case where individual semiconductors in a system-on-chip (SOC) include any defective semiconductors manufactured at a low manufacturing cost by a relatively old process (for example, a wireless modem), semiconductors manufactured at a high manufacturing cost by a new process (for example, microprocessors and memory semiconductors) must also be discarded together. Therefore, if system-on-chips (SOCs) can be manufactured in a multi-die structure by distinguishing them, the yield of system-on-chips (SOCs) can increase.
Therefore, it is desirable to develop a new semiconductor packaging technology capable of solving the problems of the existing package-on-package (POP) technology.
The present disclosure provides a semiconductor package and a method for fabricating the semiconductor package having advantages of being able to implement a system-on-chip (SOC) as a three-dimensional integrated circuit (3D IC) structure by distinguishing individual semiconductors to be included in a system-on-chip (SOC) included in the package-on-package (POP) technology under a predetermined criterion, and stacking each of the individual semiconductors on a front side redistribution layer (FRDL) in a package-on-package (POP) fabricating process.
Also, the present disclosure provides a semiconductor package and a method for fabricating the semiconductor package having advantages of disposing a 3D IC structure included in the package-on-package (POP) technology inside a cavity of an embedded trace substrate (ETS).
An embodiment of the present disclosure provides a semiconductor package including: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs; a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure; a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure and the printed circuit board; and a back side redistribution layer on the molding material.
The semiconductor package may further include connection members between the first semiconductor chip die and the second semiconductor chip die, and the connection members may include micro bumps.
The first semiconductor chip die may include a plurality of first bonding pads and a first insulating layer, and the second semiconductor chip die may include a plurality of second bonding pads and a second insulating layer.
The plurality of first bonding pads may be directly bonded to the plurality of second bonding pads.
The plurality of first bonding pads and the plurality of second bonding pads may include copper (Cu).
The first insulating layer may be directly bonded to the second insulating layer.
The first insulating layer and the second insulating layer may include silicon oxide.
The second semiconductor chip die may include a plurality of connection terminals, the front side redistribution layer may include a plurality of redistribution vias at an uppermost level thereof, and the plurality of redistribution vias may be directly bonded to the plurality of connection terminals.
The molding material may include an epoxy molding compound (EMC).
The printed circuit board may include an embedded trace substrate (ETS).
The 3D IC structure may include a system-on-chip (SOC).
Another embodiment of the present disclosure provides a semiconductor package including: a front side redistribution layer including a plurality of first redistribution vias; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs; a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure; a plurality of conductive fillers on the printed circuit board; a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure, the printed circuit board, and the plurality of conductive fillers; a back side redistribution layer on the molding material and including a plurality of second redistribution vias; and a third semiconductor chip die on the back side redistribution layer.
A width of an uppermost part of each first redistribution via of the plurality of first redistribution vias may be smaller than a width of a lowermost part of each first redistribution via of the plurality of first redistribution vias, and a width of an uppermost part of each second redistribution via of the plurality of second redistribution vias may be larger than a width of a lowermost part of each second redistribution via of the plurality of second redistribution vias.
Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor package, the method including: forming a cavity in a printed circuit board; forming a three-dimensional integrated circuit (3D IC) structure inside the cavity, the 3D IC structure including a first semiconductor chip die on a second semiconductor chip die having through-silicon vias (TSVs); at least partially encapsulating the printed circuit board and the 3D IC structure with a molding material; forming a front side redistribution layer on a lower surface of the printed circuit board and a lower surface of the second semiconductor chip die, wherein the front side redistribution layer is electrically coupled with the first semiconductor chip die by the TSVs; and forming a back side redistribution layer on the molding material.
The semiconductor package may include a fan-out wafer-level package (FOWLP) or a fan-out panel-level package (FOPLP).
Forming a 3D IC structure inside the cavity may include mounting the 3D IC structure manufactured in advance.
Forming a 3D IC structure inside the cavity may include forming the first semiconductor chip die, and bonding the second semiconductor chip die on the first semiconductor chip die.
Bonding the second semiconductor chip die on the first semiconductor chip die may be performed by hybrid bonding.
Bonding the second semiconductor chip die on the first semiconductor chip die may include bonding the first semiconductor chip die and the second semiconductor chip die by micro bumps.
The method for fabricating the semiconductor package may further include forming a plurality of conductive fillers on an upper surface of the printed circuit board after forming the front side redistribution layer on the lower surface of the printed circuit board and the lower surface of the second semiconductor chip die.
According to some embodiments, in order to prevent the yield of system-on-chips (SOCs) from decreasing due to defects of semiconductors fabricated using old processes at low manufacturing costs, such as wireless modems, system-on-chips (SOCs) in the package-on-package (POP) technology can be implemented as 3D IC structures.
According to some embodiments, the fabricating process of sequentially stacking system-on-chips (SOCs) as 3D IC structures is included in the package-on-package (POP) fabricating process. Therefore, it is not necessarily required to perform a process of separately fabricating 3D IC structures, and it is possible to reduce use of an epoxy molding compound (EMC) for encapsulating 3D IC structures when separately fabricating 3D IC structures.
According to some embodiments, 3D IC structures which are included in the package-on-package (POP) technology may be disposed in cavities of an embedded trace substrate (ETS). Therefore, it is possible to provide a semiconductor package which has improved rigidity, is resistant to warpage, and has high reliability
In the following detailed description, only certain embodiments of the present inventive concepts have been shown and described, simply by way of illustration. The present inventive concepts can be variously implemented and is not limited to the following example embodiments.
The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.
In addition, the size and thickness of each configuration shown in the drawings may be arbitrarily shown for understanding and ease of description, but the present inventive concepts are not limited thereto.
Throughout this specification, when a part is referred to as being “connected” to another part, it may be directly connected to the other part, or may be connected to the other part indirectly with any other elements interposed therebetween. In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
Further, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, when an element is “above” or “on” a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located “above” or “on” in a direction opposite to gravity.
Further, in the entire specification, when it is referred to as “on a plane”, it means when a target part is viewed from above, and when it is referred to as “on a cross-section”, it means when the cross-section obtained by cutting a target part vertically is viewed from the side.
Hereinafter, a semiconductor package and a method for fabricating the semiconductor package according to example embodiments will be described with reference to the drawings.
Referring to
The front side redistribution layer 110 may include a dielectric layer 114, and first redistribution vias 112, first redistribution lines 113, second redistribution vias 116, second redistribution lines 117, and third redistribution vias 118 formed in the dielectric layer 114. In other embodiments, a redistribution layer having fewer or more redistribution lines and redistribution vias is included in the scope of this disclosure.
The dielectric layer 114 may include a photosensitive polymer layer. Photosensitive polymers are materials applicable to a photolithography process to form fine patterns. In an embodiment, the dielectric layer 114 may include photoimageable dielectric (PID) (a photosensitive dielectric) which is used in a redistribution process. As an embodiment, the photoimageable dielectric (PID) may include a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In an embodiment, the photoimageable dielectric (PID) may have a resolution of 3 μm.
The first redistribution vias 112 are disposed between the first redistribution lines 113 and bonding pads 111. The first redistribution vias 112 electrically couple the first redistribution lines 113 with the external connection members 115 connected to the bonding pads 111 in the vertical direction. The first redistribution lines 113 are disposed between the first redistribution vias 112 and the second redistribution vias 116. The first redistribution lines 113 electrically couple the first redistribution vias 112 with the second redistribution vias 116 in the horizontal direction. The second redistribution vias 116 are disposed between the first redistribution lines 113 and the second redistribution lines 117. The second redistribution vias 116 electrically couple the first redistribution lines 113 with the second redistribution lines 117 in the vertical direction. The second redistribution lines 117 are disposed between the second redistribution vias 116 and the third redistribution vias 118. The second redistribution lines 117 electrically couple the second redistribution vias 116 with the third redistribution vias 118 in the horizontal direction. The third redistribution vias 118 are disposed between the second redistribution lines 117 and a first wiring layer 141 of the ETS 140. The third redistribution vias 118 electrically couple the second redistribution lines 117 with the first wiring layer 141 of the ETS 140 in the vertical direction.
The 3D IC structure 180 may include the first semiconductor chip die 130 and the second semiconductor chip die 120. A 3D IC is an integrated circuit implemented as a three-dimensional single chip by a technique of stacking circuits in the vertical direction, not by the existing technique of arranging circuits in the horizontal direction. If the vertical stacking technique is used, it is possible to implement more elements in the same silicon wafer area. Therefore, it becomes possible to reduce the manufacturing cost and improve the performance.
The second semiconductor chip die 120 may include one or more second semiconductor chips 121, through-silicon vias (TSVs) 122, lower bonding pads 123, upper bonding pads 124, and connection terminals 125. In an embodiment, the second semiconductor chips 121 may include a central processing unit (CPU) or a graphic processing unit (GPU). The through-silicon vias (TSVs) 122 are disposed between the lower bonding pads 123 and the upper bonding pads 124. The through-silicon vias (TSVs) 122 electrically couple the lower bonding pads 123 with the upper bonding pads 124.
In the 3D IC structure 180, the first semiconductor chip die 130 is disposed spaced apart from the front side redistribution layer 110 which transmits signals and power. For this reason, the through-silicon vias (TSVs) 122 are disposed between the second semiconductor chips 121 of the second semiconductor chip die 120 and are connected to the first semiconductor chip die 130 so as to increase the speed in receiving and responding signals and power of the first semiconductor chip die 130.
The lower bonding pads 123 are disposed between the through-silicon vias (TSVs) 122 and the connection terminals 125, and electrically couple the through-silicon vias (TSVs) 122 with the connection terminals 125. The upper bonding pads 124 are disposed between the through-silicon vias (TSVs) 122 and the connection members 131. The upper bonding pads 124 electrically couple the through-silicon vias (TSVs) 122 with the first semiconductor chip die 130 connected to the connection members 131. The connection terminals 125 are disposed between the lower bonding pads 123 and the front side redistribution layer 110. The connection terminals 125 electrically couple the lower bonding pads 123 with the front side redistribution layer 110. In an embodiment, the diameter or width of the horizontal cross sections of the connection terminals 125 may be 10 μm to 300 μm in consideration of alignments allowable during exposure.
The first semiconductor chip die 130 may include one or more first semiconductor chips and bonding pads 133. In an embodiment, the first semiconductor chips may include a wireless modem. The bonding pads 133 of the first semiconductor chip die 130 are bonded to the connection members 131 to be electrically coupled with them. In an embodiment, the connection members 131 may include micro bumps. An insulating member 132 may surround the connection members 131 between the first semiconductor chip die 130 and the second semiconductor chip die 120. In an embodiment, the insulating member 132 may include an underfill material.
The ETS 140 may include the first wiring layer 141, first vias 142, a second wiring layer 143, second vias 144, a third wiring layer 146, and an insulating layer 145. The ETS 140 is disposed between the front side redistribution layer 110 and the conductive fillers 151, and electrically couples the front side redistribution layer 110 with the conductive fillers 151. Like this, the 3D IC structure 180 is disposed in a cavity of the ETS 140. Therefore, it is possible to provide a semiconductor package 100 which has improved rigidity, is resistant to warpage, and has high reliability.
The first wiring layer 141 is disposed between the third redistribution vias 118 of the front side redistribution layer 110 and the first vias 142. The first wiring layer 141 electrically couples the third redistribution vias 118 of the front side redistribution layer 110 with the first vias 142. The first vias 142 are disposed between the first wiring layer 141 and the second wiring layer 143. The first vias 142 electrically couple the first wiring layer 141 with the second wiring layer 143. The second wiring layer 143 is disposed between the first vias 142 and the second vias 144. The second wiring layer 143 electrically couples the first vias 142 with the second vias 144. The second vias 144 are disposed between the second wiring layer 143 and the third wiring layer 146. The second vias 144 electrically couple the second wiring layer 143 with the third wiring layer 146. The third wiring layer 146 is disposed between the second vias 144 and the conductive fillers 151. The third wiring layer 146 electrically couples the second vias 144 with the conductive fillers 151. The insulating layer 145 may at least partially surround the first wiring layer 141, the first vias 142, the second wiring layer 143, and the second vias 144.
The molding material 150 at least partially encapsulates the first semiconductor chip die 130, the second semiconductor chip die 120, the ETS 140, and the conductive fillers, on the front side redistribution layer 110. Specifically, the molding material 150 covers the side and upper surfaces of the first semiconductor chip die 130, the side and lower surfaces of the second semiconductor chip die 120, the side and upper surfaces of the ETS 140, the side surface of the connection terminals 125, and the side surfaces of the conductive fillers 151.
The conductive fillers 151 are disposed between the third wiring layer 146 of the ETS 140 and fourth redistribution vias 162 of the back side redistribution layer 160, and electrically couple the third wiring layer 146 of the ETS 140 with the fourth redistribution vias 162 of the back side redistribution layer 160.
The back side redistribution layer 160 may include a dielectric layer 164, and the fourth redistribution vias 162, third redistribution lines 163, fifth redistribution vias 165, fourth redistribution lines 166, and sixth redistribution vias 167 formed in the dielectric layer 164, and bonding pads 168 and an insulating layer 169 disposed on the dielectric layer 164. In embodiments, a redistribution layer having fewer or more redistribution lines, redistribution vias, and bonding pads is included in the scope of this disclosure.
The dielectric layer 164 may include a photosensitive polymer layer. Photosensitive polymers are materials applicable to a photolithography process to form fine patterns. In an embodiment, the dielectric layer 164 may include photoimageable dielectric (PID) (a photosensitive dielectric) which is used in a redistribution process. The photoimageable dielectric (PID) may include a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In an embodiment, the photoimageable dielectric (PID) may have a resolution of 3 μm.
The fourth redistribution vias 162 are disposed between the third redistribution lines 163 and the conductive fillers 151. The fourth redistribution vias 162 electrically couple the third redistribution lines 163 with the conductive fillers 151 in the vertical direction. The third redistribution lines 163 are disposed between the fourth redistribution vias 162 and the fifth redistribution vias 165. The third redistribution lines 163 electrically couple the fourth redistribution vias 162 with the fifth redistribution vias 165 in the horizontal direction. The fifth redistribution vias 165 are disposed between the third redistribution lines 163 and the fourth redistribution lines 166. The fifth redistribution vias 165 electrically couple the third redistribution lines 163 with the fourth redistribution lines 166 in the vertical direction. The fourth redistribution lines 166 are disposed between the fifth redistribution vias 165 and the sixth redistribution vias 167. The fourth redistribution lines 166 electrically couple the fifth redistribution vias 165 with the sixth redistribution vias 167 in the horizontal direction. The sixth redistribution vias 167 are disposed between the fourth redistribution lines 166 and the bonding pads 168. The sixth redistribution vias 167 electrically couple the fourth redistribution lines 166 with the bonding pads 168 in the vertical direction.
The bonding pads 168 are disposed between the sixth redistribution vias 167 and connection members 175. The bonding pads 168 electrically couple the sixth redistribution vias 167 with the connection members 175.
The insulating layer 169 is disposed so as to surround the individual bonding pads 168 in order to help prevent short-circuiting of the bonding pads 168. In an embodiment, the insulating layer 169 may include solder resist.
The shapes of the first, second, and third redistribution vias 112, 116, and 118 in the front side redistribution layer 110 may be symmetrical with the shapes of the fourth, fifth, and sixth redistribution vias 162, 165, and 167 in the back side redistribution layer 160. The width of the uppermost part of each redistribution via of the first, second, and third redistribution vias 112, 116, and 118 in the front side redistribution layer 110 may be smaller than the width of its lowermost part, and the width of the uppermost part of each redistribution via of the fourth, fifth, and sixth redistribution vias 162, 165, and 167 in the back side redistribution layer 160 may be larger than the width of its lowermost part.
This is attributable to the method for fabricating a semiconductor package (a chip-first process) according to this disclosure in which in a fan-out wafer-level package (FOWLP) or a fan-out panel-level package (FOPLP), a 3D IC structure 180 is mounted, and a first carrier 190 is attached to the top of the 3D IC structure 180, whereby a front side redistribution layer 110 is formed (see
The external connection members 115 electrically couple an external component with the front side redistribution layer 110 connected to the bonding pads 111 disposed beneath the front side redistribution layer 110. An insulating layer 119 may have a plurality of openings for soldering. In an embodiment, the insulating layer 119 may include solder resist. The insulating layer 119 helps prevent the external connection members 115 from being short-circuited.
The third semiconductor chip die 170 is disposed on the back side redistribution layer 160. The third semiconductor chip die 170 is electrically coupled with the back side redistribution layer 160 using the connection members 175. The third semiconductor chip die 170 may include an insulating layer 176 provided beneath it to help prevent short-circuiting of the connection members 175. In an embodiment, the insulating layer 176 may include solder resist.
Referring to
The features of the configuration of the semiconductor package 100 of
Referring to
In an embodiment, the bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120 may include copper (Cu). In another embodiment, the bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120 may be a metallic material to which hybrid bonding can be applied. In an embodiment, the silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120 may include silicon oxide. In an embodiment, the silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120 may include SiO2. In other embodiments, the silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120 may be silicon nitride, silicon oxynitride, or other suitable dielectric materials.
The features of the configuration of the semiconductor package 100 of
Referring to
Referring to
The insulating layer 145 surrounds the first wiring layer 141 (e.g., side surfaces of the first wiring layer 141), the first vias 142, the second wiring layer 143, and the second vias 144 (e.g., side surfaces of the second vias 144). In an embodiment, the insulating layer 145 may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of such a resin and an inorganic filler. In an embodiment, the insulating layer 145 may include resin impregnated with a core material, such as glass fiber, glass cloth, and glass fabric, together with an inorganic filler. In an embodiment, the insulating layer 145 may include prepreg, Ajinomoto build-up film (ABF), FR-4, and bismaleimide triazine (BT). In an embodiment, the insulating layer 145 may include photoimageable dielectric (PID) (a photosensitive dielectric).
The first wiring layer 141, the second wiring layer 143, and the third wiring layer 146 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The first vias 142 and the second vias 144 electrically couple the first wiring layer 141, the second wiring layer 143, and the third wiring layer 146 formed in different layers. The first vias 142 and the second vias 144 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.
Referring to
Referring to
Referring to
Since a system-on-chip (SOC) to be included in a package-on-package (POP) is fabricated in the process of fabricating the package-on-package (POP), a separate process for fabricating the system-on-chip (SOC) is unnecessary. Therefore, it is possible to reduce use of a molding material (e.g., EMC) which is typically used when a system-on-chip (SOC) is fabricated in a separate process.
Referring to
Referring to
Through this bonding step using the connection members 131, the first semiconductor chip die 130 is vertically stacked on the second semiconductor chip die 120, and in the process of forming a package-on-package (POP), a system-on-chip (SOC) including the first semiconductor chip die 130 and the second semiconductor chip die 120 is formed as the 3D IC structure 180.
Referring to
The bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120 may be directly bonded by metal-to-metal bonding of the hybrid bonding. By the metal-to-metal bonding of the hybrid bonding, metallic bonds are formed at the interfaces between the bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120. The bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120 may be formed of the same material such that after hybrid bonding, the interfaces between the bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120 disappear. Through the bonding pads 133 of the first semiconductor chip die 130 and the bonding pads 124 of the second semiconductor chip die 120, the first semiconductor chip die 130 and the second semiconductor chip die 120 can be electrically connected to each other.
The silicon insulating layer 136 of the first semiconductor chip die 130 may be directly bonded to the silicon insulating layer 126 of the second semiconductor chip die 120 by nonmetal-to-nonmetal bonding of the hybrid bonding. By the nonmetal-to-nonmetal bonding of the hybrid bonding, a covalent bond is formed at the interface between the silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120. The silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120 may be formed of the same material such that after hybrid bonding, the interface between the silicon insulating layer 136 of the first semiconductor chip die 130 and the silicon insulating layer 126 of the second semiconductor chip die 120 disappears.
Through this bonding step using hybrid bonding, the first semiconductor chip die 130 is vertically stacked on the second semiconductor chip die 120, and in the process of forming a package-on-package (POP), a system-on-chip (SOC) including the first semiconductor chip die 130 and the second semiconductor chip die 120 is formed as the 3D IC structure 180.
Referring to
Referring to
Referring to
Referring to
First, the dielectric layer 114 is formed on the lower surface of the ETS 140 and the lower surface of the 3D IC structure 180. In an embodiment, the dielectric layer 114 is formed of a polymer such as PBO or polyimide. In another embodiment, the dielectric layer 114 is formed of an inorganic dielectric material such as silicon nitride or silicon oxide. In an embodiment, the dielectric layer 114 may be formed by a CVD, ALD, or PECVD process.
After the dielectric layer 114 is formed, the third redistribution vias 118 are formed by selectively etching the dielectric layer 114 to form via holes and filling the via holes with a conductive material. The third redistribution vias 118 are bonded to the connection terminals 125 of the 3D IC structure 180 or the first wiring layer 141.
Subsequently, on the third redistribution vias 118 and the dielectric layer 114, a dielectric layer 114 is further deposited, and the second redistribution lines 117 are formed by selectively etching the additional deposited dielectric layer 114 to form openings and filling the openings with a conductive material.
Then, on the second redistribution lines 117 and the dielectric layer 114, a dielectric layer 114 is further deposited, and the second redistribution vias 116 are formed by selectively etching the additional deposited dielectric layer 114 to form via holes and filling the via holes with a conductive material.
Subsequently, on the second redistribution vias 116 and the dielectric layer 114, a dielectric layer 114 is further deposited, and the first redistribution lines 113 are formed by selectively etching the additional deposited dielectric layer 114 to form openings and filling the openings with a conductive material.
Next, on the first redistribution lines 113 and the dielectric layer 114, a dielectric layer 114 is further deposited, and the first redistribution vias 112 are formed by selectively etching the additional deposited dielectric layer 114 to form via holes and filling the via holes with a conductive material.
In an embodiment, the first redistribution vias 112, the first redistribution lines 113, the second redistribution vias 116, the second redistribution lines 117, and the third redistribution vias 118 may include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In an embodiment, the first redistribution vias 112, the first redistribution lines 113, the second redistribution vias 116, the second redistribution lines 117, and the third redistribution vias 118 may be formed by performing sputtering processes. In another embodiment, the first redistribution vias 112, the first redistribution lines 113, the second redistribution vias 116, the second redistribution lines 117, and the third redistribution vias 118 may be formed by forming a seed metal layer and performing an electroplating process.
Referring to
Referring to
Referring to
The dielectric layer 164 is formed on the molding material 150 having the conductive fillers 151. In an embodiment, the dielectric layer 164 is formed of a polymer such as PBO or polyimide. In another embodiment, the dielectric layer 164 is formed of an inorganic dielectric material such as silicon nitride or silicon oxide. In an embodiment, the dielectric layer 164 may be formed by a CVD, ALD, or PECVD process.
After the dielectric layer 164 is formed, the fourth redistribution vias 162 are formed by selectively etching the dielectric layer 164 to form via holes and filling the via holes with a conductive material. The fourth redistribution vias 162 are bonded to the conductive fillers 151.
Subsequently, on the fourth redistribution vias 162 and the dielectric layer 164, a dielectric layer 164 is further deposited, and the third redistribution lines 163 are formed by selectively etching the additional deposited dielectric layer 164 to form openings and filling the openings with a conductive material.
Then, on the third redistribution lines 163 and the dielectric layer 164, a dielectric layer 164 is further deposited, and the fifth redistribution vias 165 are formed by selectively etching the additional deposited dielectric layer 164 to form via holes and filling the via holes with a conductive material.
Subsequently, on the fifth redistribution vias 165 and the dielectric layer 164, a dielectric layer 164 is further deposited, and the fourth redistribution lines 166 are formed by selectively etching the additional deposited dielectric layer 164 to form openings and filling the openings with a conductive material.
Next, on the fourth redistribution lines 166 and the dielectric layer 164, a dielectric layer 164 is further deposited, and the sixth redistribution vias 167 are formed by selectively etching the additional deposited dielectric layer 164 to form via holes and filling the via holes with a conductive material.
Subsequently, on the sixth redistribution vias 167 and the dielectric layer 164, a dielectric layer 164 is further deposited, and the bonding pads 168 are formed by selectively etching the additional deposited dielectric layer 164 to form openings and filling the openings with a conductive material.
In some embodiments, the fourth redistribution vias 162, the third redistribution lines 163, the fifth redistribution vias 165, the fourth redistribution lines 166, the sixth redistribution vias 167, and the bonding pads 168 may include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In an embodiment, the fourth redistribution vias 162, the third redistribution lines 163, the fifth redistribution vias 165, the fourth redistribution lines 166, the sixth redistribution vias 167, and the bonding pads 168 may be formed by performing sputtering processes. In another embodiment, the fourth redistribution vias 162, the third redistribution lines 163, the fifth redistribution vias 165, the fourth redistribution lines 166, the sixth redistribution vias 167, and the bonding pads 168 may be formed by forming a seed metal layer and performing an electroplating process.
Referring to
Referring to
While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0010396 | Jan 2023 | KR | national |
