In recent years, there have been great advances in the field of machine learning. Much of these advances have been in machine trained networks (e.g., deep neural networks) and algorithms for training such networks. However, there has not been as much advances in circuits for implementing machine-trained networks. This has been primarily due to an over reliance on implementing machine trained networks in datacenters as opposed to in devices in the real world. Therefore, there is a need in the art for innovative circuits for implementing machine trained networks as well as other types of designs.
Some embodiments of the invention provide a three-dimensional (3D) circuit structure that uses latches to transfer signals between two bonded circuit layers. In some embodiments, this structure includes a first circuit partition on a first bonded layer and a second circuit partition on a second bonded layer. It also includes at least one latch to transfer signals between the first circuit partition on the first bonded layer and the second circuit partition on the second bonded layer. In some embodiments, the latch operates in (1) an open first mode that allows a signal to pass from the first circuit partition to the second circuit partition and (2) a closed second mode that maintains the signal passed through during the prior open first mode.
Unlike a flip-flop that releases in one clock cycle a signal that it stores in a prior clock cycle, a transparent latch does not introduce such a setup time delay in the design. In fact, by allowing the signal to pass through the first circuit partition to the second circuit partition during its open mode, the latch allows the signal to borrow time from a first portion of a clock cycle of the second circuit partition for a second portion of the clock cycle of the second circuit partition. This borrowing of time is referred to below as time borrowing. Also, this time borrowing allows the signal to be available at the destination node in the second circuit partition early so that the second circuit can act on it in the clock cycle that this signal is needed. Compared to flip-flops, latches also reduce the clock load because, while flip-flops require at least two different clock transitions to store and then release a value, transparent latches only require one signal transition to latch a value that they previously passed through.
In some embodiments, the 3D circuit has several such latches at several boundary nodes between different circuit partitions on different bonded layers. Each latch in some embodiments iteratively operates in two sequential modes, an open first mode to let a signal pass from one circuit partition (e.g., a first partition or a second partition) to the other circuit partition (e.g., the second partition or the first partition), and a closed second mode to hold the signal passed during the prior open first mode.
Each latch in some embodiments is associated with one pair of boundary nodes, with one node in the first bonded layer and another node in the second bonded layer. Each pair of nodes is electrically interconnected through a conductive interface, such as a through-silicon via (TSV) or a direct bond interface (DBI) connection (also called hybrid bonding). Each latch in some embodiments is defined on just one of the two bonded layers. In some embodiments, each latch on one bonded layer has its output carried to the other bonded layer by interconnect (e.g., wires) and the conductive interface (e.g., TSV or DBI connection) that connects the latch's associated pair of nodes. In other embodiments, each latch on one bonded layer has its input supplied from the other bonded layer by interconnect and the conductive interface that connects the latch's associated pair of nodes. In still other embodiments, a conductive-interface connection can have two latches on the two bonded layers that it connects, and either latch can be used to facilitate time borrowing as a signal travels between the two circuit partitions on the two bonded layers.
The first and second bonded layers are different in different embodiments. In some embodiments, both bonded layers are integrated circuit (IC) dies. In other embodiments, both bonded layers are IC wafers. In still other embodiments, one of these bonded layers is an IC die, while the other bonded layer is an IC wafer. The first and second bonded layers are vertically stacked on top of each other with no other intervening bonded layers in some embodiments, while these two bonded layers have one or more intervening bonded layers between them in other embodiments.
In some embodiments, one bonded layer fully overlaps the other bonded layer (e.g., the two bonded layers have the same size and are aligned such that they overlap each other's bounding shape), or one bonded layer is smaller than the other bonded layer and is completely subsumed by the footprint of the other bonded layer (i.e., has its bounding shape completely overlapped by the bounding shape of the other bonded layer). In other embodiments, the two bonded layers partially overlap. Also, in some embodiments, the first and second circuit partitions on the first and second bonded layers fully overlap (e.g., the two partition have the same size and are aligned such that they overlap each other's bounding shape), or one partition is smaller than the other partition and is completely subsumed by the footprint of the other partition). In other embodiments, the two circuit partitions partially overlap.
Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network.
In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.
In some embodiments, the machine-trained network includes a first sub-network on one bonded layer and a second sub-network on another bonded layer, with these two sub-networks partially or fully overlapping. Alternatively, or conjunctively, the machine-trained network or sub-network on one bonded layer partially or fully overlaps a memory (e.g., formed by one or more memory arrays) on another bonded layer in some embodiments. This memory in some embodiments is a memory that stores machine-trained parameters for configuring the processing nodes of the machine-trained network or sub-network to perform a particular operation. In other embodiments, this memory is a memory that stores the outputs of the processing nodes (e.g., outputs of earlier stage processing node for later stage processing node).
While being vertically aligned with one memory, the machine-trained network's processing nodes in some embodiments are on the same bonded layer with another memory. For instance, in some embodiments, a first bonded layer in a 3D circuit includes the processing nodes of a machine-trained network and a first memory to store machine-trained parameters for configuring the processing nodes, while a second bonded layer in the 3D circuit includes a second memory to store values produced by the processing nodes. In other embodiments, the first bonded layer in the 3D circuit includes the processing nodes of a machine-trained network and a first memory to store values produced by the processing nodes, while the second bonded layer in the 3D circuit includes a second memory to store machine-trained parameters for configuring the processing nodes.
In still other embodiments, the first bonded layer in the 3D circuit includes the processing nodes of a machine-trained network, while the second bonded layer in the 3D circuit includes a first memory to store values produced by the processing nodes and a second memory to store machine-trained parameters for configuring the processing nodes. In yet other embodiments, the processing nodes on one bonded layer partially or fully overlap two memories on two different layers, with one memory storing machine-trained parameters and the other memory storing processing node output values. The 3D circuit of other embodiments has processing nodes on two or more bonded layers with parameter and/or output memories on the same or different bonded layers. In this document, parameter memory is a memory that stores machine-trained parameters for configuring the machine-trained network (e.g., for configuring the processing nodes of the network) to perform one or more tasks, while output memory is a memory that stores the outputs of the processing nodes of the machine-trained network.
Again, in the above-described embodiments, the bonded layers (two or more) that contain a machine-trained network's processing nodes and memories do not have any intervening bonded layer in some embodiments, while they have one or more intervening bonded layers between or among them in other embodiments. Also, in some embodiments, the machine-trained network's processing nodes and memories on different bonded layers are connected to each other through conductive interfaces, such as TSV or DBI connections.
In some embodiments, the IC die on which a neural network is defined is an ASIC (Application Specific IC) and each neuron in this network is a computational unit that is custom-defined to operate as a neuron. Some embodiments implement a neural network by re-purposing (i.e., reconfiguring) one or more neurons used for earlier neural network stages to implement one or more neurons in later neural network stages. This allows fewer custom-defined neurons to be used to implement the neural network. In such embodiments, the routing fabric between the neurons is at least partially defined by one or more output memories that are used to store the outputs of earlier used neurons to feed the inputs of later staged neurons.
In some embodiments, the output and parameter memories of the neural network have different memory structures (i.e., are different types of memories). For instance, in some embodiments, the output memory has a different type of output interface (e.g., one that allows for random access of the output memory's storage locations) than the parameter memory (e.g., the parameter memory's output interface only provides sequential access of its storage locations). Alternatively, or conjunctively, the parameter memory of the neural network is a read-only memory (ROM), while the output memory of the neural network is a read-write memory in some embodiments. The parameter memory in some embodiments is a sequential ROM that sequentially reads out locations in the ROM to output the parameters that configure the neural network to perform certain machine-trained task(s).
The output memory in some embodiments is a dynamic random access memory (DRAM). In other embodiments, the output memory is an ephemeral RAM (ERAM) that has one or more arrays of storage cells (e.g., capacitive cells) and pass transistors like traditional DRAMs, but does not use read-independent refresh cycles to charge the storage cells unlike traditional DRAMs. This is because the values in the ERAM memory are written and read at such rates that these values do not need to be refreshed with separate refresh cycles. In other words, because intermediate output values of the neural network only need to be used as input into the next layer (or few layers) of the neural network, they are temporary in nature. Thus, the output memory can be implemented with a memory architecture that is compact like a DRAM memory architecture without the need for read-independent refresh cycles.
Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant neural network. The neural network has one or more redundant neurons in some embodiments. After the IC is manufactured, a defective neuron in the neural network can be detected through a test procedure and then replaced by a redundant neuron (i.e., the redundant neuron can be assigned the operation of the defective neuron). The routing fabric of the neural network can be reconfigured so that it re-routes signals around the discarded, defective neuron. In some embodiments, the reconfigured routing fabric does not provide any signal to or forward any signal from the discarded, defective neuron, and instead provides signals to and forwards signals from the redundant neuron that takes the defective neuron's position in the neural network.
In the embodiments that implement a neural network by re-purposing (i.e., reconfiguring) one or more individual neurons to implement neurons of multiple stages of the neural network, the IC discards a defective neuron by removing it from the pool of neurons that it configures to perform the operation(s) of neurons in one or more stages of neurons, and assigning this defective neuron's configuration(s) (i.e., its machine-trained parameter set(s)) to a redundant neuron. In some of these embodiments, the IC would re-route around the defective neuron and route to the redundant neuron, by (1) supplying machine-trained parameters and input signals (e.g., previous stage neuron outputs) to the redundant neuron instead of supplying these parameters and signals to the defective neuron, and (2) storing the output(s) of the redundant neuron instead of storing the output(s) of the defective neuron.
One of ordinary skill will understand that while several embodiments of the invention have been described above by reference to machine-trained neural networks with neurons, other embodiments of the invention are implemented on other machine-trained networks with other kinds of machine-trained processing nodes.
The preceding Summary is intended to serve as a brief introduction to some embodiments of the invention. It is not meant to be an introduction or overview of all inventive subject matter disclosed in this document. The Detailed Description that follows and the Drawings that are referred to in the Detailed Description will further describe the embodiments described in the Summary as well as other embodiments. Accordingly, to understand all the embodiments described by this document, a full review of the Summary, Detailed Description, the Drawings, and the Claims is needed. Moreover, the claimed subject matters are not to be limited by the illustrative details in the Summary, Detailed Description, and the Drawings.
The novel features of the invention are set forth in the appended claims. However, for the purpose of explanation, several embodiments of the invention are set forth in the following figures.
In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and described. However, it will be clear and apparent to one skilled in the art that the invention is not limited to the embodiments set forth and that the invention may be practiced without some of the specific details and examples discussed.
Some embodiments of the invention provide a three-dimensional (3D) circuit structure that uses latches to transfer signals between two bonded circuit layers. In some embodiments, this structure includes a first circuit partition on a first bonded layer and a second circuit partition on a second bonded layer. It also includes at least one latch to transfer signals between the first circuit partition on the first bonded layer and the second circuit partition on the second bonded layer. In some embodiments, the latch operates in (1) an open first mode (also called a transparent mode) that allows a signal to pass from the first circuit partition to the second circuit partition and (2) a closed second mode that maintains the signal passed through during the prior open first mode.
Unlike a flip-flop that releases in one clock cycle a signal that it stores in a prior clock cycle, a transparent latch does not introduce such a setup time delay in the design. In fact, by allowing the signal to pass through the first circuit partition to the second circuit partition during its open mode, the latch allows the signal to borrow time from a first portion of a clock cycle of the second circuit partition for a second portion of the clock cycle of the second circuit partition. This borrowing of time is referred to below as time borrowing. Also, this time borrowing allows the signal to be available at the destination node in the second circuit partition early so that the second circuit can act on it in the clock cycle that this signal is needed. Compared to flip-flops, latches also reduce the clock load because, while flip-flops require at least two different clock transitions to store and then release a value, transparent latches only require one signal transition to latch a value that they previously passed through.
The first and second bonded layers are different in different embodiments. In some embodiments, both bonded layers are integrated circuit (IC) dies. In other embodiments, both bonded layers are IC wafers. In still other embodiments, one of these bonded layers is an IC die, while the other bonded layer is an IC wafer. The first and second bonded layers are vertically stacked on top of each other with no other intervening bonded layers in some embodiments, while these two bonded layers have one or more intervening bonded layers between them in other embodiments.
In some embodiments, the 3D circuit has several such latches at several boundary nodes between different circuit partitions on different bonded layers. Each latch in some embodiments is associated with one pair of boundary nodes, with one node in the first bonded layer and another node in the second bonded layer. Each pair of nodes is electrically interconnected through a conductive interface, such as a through-silicon via (TSV) or a direct bond interface (DBI) connection. Each latch in some embodiments is defined on just one of the two bonded layers.
In
For each of several conductive vertical connections between two adjacent dies, one or both of the dies has a latch that electrically connects (through interconnect) to the conductive-interface connection. In some embodiments, each such latch iteratively operates in two sequential modes, an open first mode (also called a transparent mode) to let a signal pass from one circuit partition on one IC die to a circuit partition on the other IC die, and a closed second mode to hold the signal passed during the prior open first mode.
Because the latch was open during its first phase, the signal was allowed to pass through from the first circuit block 120 to the second circuit block in this phase, which, in turn, allowed the signal to reach its destination 138 in the second circuit block 120 sooner in the closed second phase 204 of the latch 132. In this manner, the latch allows the signal to time borrow (e.g., borrow time from the first phase to speed up the operation of the second circuit block during the second phase).
Instead of placing a latch on the IC die layer from which the signal originates, some embodiments place the latch on the IC die layer on which the signal terminates.
As shown in
In other embodiments, a conductive vertical connection can be associated with two latches on the two bonded layers that it connects, and either latch can be used to facilitate time borrowing as a signal travels between the two circuit partitions on the two bonded layers through the conductive vertical connection. Thus, for the examples illustrated in
The outputs of the AND gates 535a and 535b are supplied respectively to XOR gates 540a and 540b. These XOR gates are cross-coupled such that their outputs are fed back to the inputs of each other. The outputs of the XOR gates 540a and 540b represent the output of the latch. When only one latch output is needed, the output of XOR gate 540a presented at the Q terminal 515 of the latch serves as the output of the latch 500. As shown by the truth table 550 in
Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. For instance, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combination of wafers and dies for the different bonded layers. Also, the machine-trained network includes an arrangement of processing nodes in some embodiments. In several examples described below, the processing nodes are neurons and the machine-trained network is a neural network. However, one of ordinary skill will realize that other embodiments are implemented with other machine-trained networks that have other kinds of machine-trained processing nodes.
As further shown, the neural network 605 in some embodiments includes several stages of neurons 610 with routing fabric that supplies the outputs of earlier stage neurons to drive the inputs of later stage neurons. In some embodiments, one or more parameters associated with each neuron is defined through machine-trained processes that define the values of these parameters in order to allow the neural network to perform particular operations (e.g., face recognition, voice recognition, etc.).
In all but the last layer of the feed-forward neural network 605, each neuron 610 receives two or more outputs of neurons from earlier neuron layers (earlier neuron stages) and provides its output to one or more neurons in subsequent neuron layers (subsequent neuron stages). The outputs of the neurons in the last layer represent the output of the network 605. In some embodiments, each output dimension of the network 600 is rounded to a quantized value.
The linear component (linear operator) 620 of each interior or output neuron computes a dot product of a vector of weight coefficients and a vector of output values of prior nodes, plus an offset. In other words, an interior or output neuron's linear operator computes a weighted sum of its inputs (which are outputs of the previous stage neurons that the linear operator receives) plus an offset. Similarly, the linear component 620 of each input stage neuron computes a dot product of a vector of weight coefficients and a vector of input values, plus an offset. Each neuron's nonlinear component (nonlinear activation operator) 625 computes a function based on the output of the neuron's linear component 620. This function is commonly referred to as the activation function.
The notation of
zi(l+1)=(Wi(l+1)·y(l))+bi(l+1). (A)
The symbol · is the dot product. The weight coefficients W(l) are weight values that can be adjusted during the network's training in order to configure this network to solve a particular problem. Other embodiments use other formulations than Equation (A) to compute the output zi(l+1) of the linear operator 620.
The output y(l+1) of the nonlinear component 625 of a neuron in layer l+1 is a function of the neuron's linear component, and can be expressed as by Equation (B) below.
yi(l+1)=ƒ(zi(l+1)), (B)
In this equation, ƒ is the nonlinear activation function for node i. Examples of such activation functions include a sigmoid function (ƒ(x)=1/(1+e−x)), a tanh function, a ReLU (rectified linear unit) function or a leaky ReLU function.
Traditionally, the sigmoid function and the tanh function have been the activation functions of choice. More recently, the ReLU function has been proposed for the activation function in order to make it easier to compute the activation function. See Nair, Vinod and Hinton, Geoffrey E., “Rectified linear units improve restricted Boltzmann machines,” ICML, pp. 807-814, 2010. Even more recently, the leaky ReLU has been proposed in order to simplify the training of the processing nodes by replacing the flat section of the ReLU function with a section that has a slight slope. See He, Kaiming, Zhang, Xiangyu, Ren, Shaoqing, and Sun, Jian, “Delving deep into rectifiers: Surpassing human-level performance on imagenet classification,” arXiv preprint arXiv:1502.01852, 2015. In some embodiments, the activation functions can be other types of functions, like cup functions and periodic functions.
Before the neural network 605 can be used to solve a particular problem (e.g., to perform face recognition), the network in some embodiments is put through a supervised training process that adjusts (i.e., trains) the network's configurable parameters (e.g., the weight coefficients of its linear components). The training process iteratively selects different input value sets with known output value sets. For each selected input value set, the training process in some embodiments forward propagates the input value set through the network's nodes to produce a computed output value set. For a batch of input value sets with known output value sets, the training process back propagates an error value that expresses the error (e.g., the difference) between the output value sets that the network 605 produces for the input value sets in the training batch and the known output value sets of these input value sets. This process of adjusting the configurable parameters of the machine-trained network 605 is referred to as supervised, machine training (or machine learning) of the neurons of the network 605.
In some embodiments, the IC die on which the neural network is defined is an ASIC (Application Specific IC) and each neuron in this network is a computational unit that is custom-defined to operate as a neuron. Some embodiments implement a neural network by re-purposing (i.e., reconfiguring) one or more neurons used for earlier neural network stages to implement one or more neurons in later neural network stages. This allows fewer custom-defined neurons to be needed to implement the neural network. In such embodiments, the routing fabric between the neurons is at least partially defined by one or more output memories that are used to store the outputs of earlier stage neurons to feed the inputs of later stage neurons.
In some embodiments, the neural network includes a first sub-network on one bonded layer and a second sub-network on another bonded layer, with these two sub-networks partially or fully overlapping.
As further shown in
In some embodiments, the sub-network 705 are the neurons that are used to implement the odd layer neurons in the multi-layer neuron arrangement (e.g., the multi-layer arrangement shown in
In some embodiments, the vertical connections 710 connect the output of neurons of sub-network 705 on the first IC die to an output memory on the second die that connects to the sub-network 707, so that these values can be stored in the output memory. From this memory, the stored output values are supplied to neurons of the sub-network 707 on the second die so that these neurons can perform computations based on the outputs of the neurons of the sub-network 705 that implement an earlier stage of the neural network's operation.
In some of these embodiments, the outputs of the neurons of the sub-network 707 are then passed through the vertical connections 710 to an output memory on the first die 702 that connects to the sub-network 705. From the output memory on the first die 702, the outputs of the neurons of the sub-network 707 of the second die are supplied to the neurons of the sub-network 705 of the first die once these neurons have been configured to perform the operation of later stage neurons of the neural network. Based on these outputs, the neurons of the sub-network 705 can then perform computations associated with the later stage neurons of the neural network. In this manner, the output values of the neurons of the sub-networks 705 and 707 can continue to pass back and forth between the two IC dies 702 and 704 as the neurons of each sub-network 705 and 707 are reconfigured to perform successive or successive sets (e.g., pairs) of stages of operation of the neural network.
Alternatively, or conjunctively, the neural network or sub-network on one bonded layer partially or fully overlaps a memory (e.g., formed by one or more memory arrays) on another bonded layer in some embodiments. This memory in some embodiments is a parameter memory that stores machine-trained parameters for configuring the neurons of the neural network or sub-network to perform a particular operation. In other embodiments, this memory is an output memory that stores the outputs of the neurons (e.g., outputs of earlier stage neurons for later stage neurons).
While being vertically aligned with one memory, the neural network's neurons in some embodiments are on the same bonded layer with another memory.
As further shown in
The neurons 805 connect to the output memory 812 through one or more interconnect layers (also called metal layers or wiring layers) of the IC die 804. As known in the art, each IC die is manufactured with multiple interconnect layers that interconnect the circuit components (e.g., transistors) defined on the IC die's substrate. Through its connection with the output memory, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network.
As further shown in
The neurons 905 connect to the parameter memory 915 through one or more interconnect layers of the IC die 904. Through its connection with the parameter memory, the neurons receive the machine-trained parameters (e.g., weight values for the linear operators of the neurons) that configure the neural network to perform a set of one or more tasks (e.g., face recognition) for which the neural network has been trained. When neurons are placed on both face-to-face mounted dies, some embodiments also place parameter memories on both dies in order to provide machine-trained parameters to neurons on the same IC die or to neurons on the other IC die.
As further shown in
In some embodiments, the neurons on one bonded layer partially or fully overlap two memories on two different layers, with one memory storing machine-trained parameters and the other memory storing neuron output values.
As further shown in
As shown, numerous such connections 1110 and 1111 are used to electrically connect nodes of the neurons 1105 on the IC die 1104 to either nodes of the output memory 1112 on the IC die 1102, or to nodes of the parameter memory 1115 on the IC die 1106. Through the connections 1110 with the output memory 1112, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network. Also, through the connections 1111 with the parameter memory 1115, the neurons receive the machine-trained parameters that configure the neural network to perform a set of one or more tasks (e.g., face recognition) for which the neural network has been trained.
One of ordinary skill will realize that other permutations of 3D circuit structures are also possible. For instance, in some embodiments, the 3D circuit has neurons on two or more bonded layers with parameter and/or output memories on the same or different bonded layers. Also, in the above-described embodiments, the bonded layers (two or more) that contain a neural network's neurons and memories do not have any intervening bonded layer in some embodiments. In other embodiments, however, these bonded layers have one or more intervening bonded layers between or among them.
In some embodiments, the output and parameter memories of the neural network have different memory structures (i.e., are different types of memories). For instance, in some embodiments, the output memory (e.g., memory 812, 912, 1012, or 1112) has a different type of output interface than the parameter memory (e.g., the memory 815, 915, 1015, or 1115). For example, the output memory's output interface allows for random access of this memory's storage locations, while the parameter memory's output interface only supports sequential read access.
Alternatively, or conjunctively, the parameter memory (e.g., the memory 815, 915, 1015, or 1115) of the neural network is a read-only memory (ROM), while the output memory (e.g., memory 812, 912, 1012, or 1112) of the neural network is a read-write memory in some embodiments. The parameter memory in some embodiments is a sequential ROM that sequentially reads out locations in the ROM to output the parameters that configure the neural network to perform certain machine-trained task(s).
The output memory (e.g., memory 812, 912, 1012, or 1112) in some embodiments is a dynamic random access memory (DRAM). In other embodiments, the output memory is an ephemeral RAM (ERAM) that has one or more arrays of storage cells (e.g., capacitive cells) and pass transistors like traditional DRAMs. However, unlike traditional DRAMs, the ERAM output memory does not use read-independent refresh cycles to charge the storage cells. This is because the values in the ERAM output memory are written and read at such rates that these values do not need to be refreshed with separate refresh cycles. In other words, because intermediate output values of the neural network only need to be used as input into the next layer (or few layers) of the neural network, they are temporary in nature. Thus, the output memory can be implemented with a compact, DRAM-like memory architecture without the use of the read-independent refresh cycles of traditional DRAMs.
Using different dies for the output memory 1112 and parameter memory 1115 allows these dies to be manufactured by processes that are optimal for these types of memories. Similarly, using a different die for the neurons of the neural network than for the output memory and/or parameter memory also allows each of these components to be manufactured by processes that are optimal for each of these types of components.
As shown, the 3D IC 1205 includes a case 1250 (sometimes called a cap or epoxy packaging) that encapsulates the dies 1202 and 1204 of this IC in a secure housing 1215. On the back side of the die 1204 one or more interconnect layers 1206 are defined to connect the 3D IC to a ball grid array 1220 that allows this to be mounted on a printed circuit board 1230 of the device 1200. In some embodiments, the 3D IC includes packaging with a substrate on which the die 1204 is mounted (i.e., between the ball grid array and the IC die 1204), while in other embodiments this packaging does not have any such substrate.
Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant neural network. The neural network has one or more redundant neurons in some embodiments. After the IC is manufactured, a defective neuron in the neural network can be replaced by a redundant neuron (i.e., the redundant neuron can be assigned the operation of the defective neuron). The routing fabric of the neural network can be reconfigured so that it re-routes signals around the discarded, defective neuron. In some embodiments, the re-configured routing fabric does not provide any signal to or forward any signal from the discarded, defective neuron, and instead provides signals to and forwards signals from the redundant neuron that takes the defective neuron's position in the neural network.
In the embodiments that implement a neural network by re-purposing (i.e., reconfiguring) one or more individual neurons to implement neurons of multiple stages of the neural network, the IC discards a defective neuron by removing it from the pool of neurons that it configures to perform the operation(s) of neurons in one or more stages of neurons, and assigning this defective neuron's configuration(s) (i.e., its machine-trained parameter set(s)) to a redundant neuron. In some of these embodiments, the IC would re-route around the defective neuron and route to the redundant neuron, by (1) supplying machine-trained parameters and input signals (e.g., previous stage neuron outputs) to the redundant neuron instead of supplying these parameters and signals to the defective neuron, and (2) storing the output(s) of the defective neuron instead of storing the output(s) of the defective neuron.
The machine-trained circuit 1300 has two parameter memories 1315a and 1315b that respectively store machine-trained parameters for the neuron sets 1305 and 1310. These machine-trained parameters iteratively configure each neuron set to implement a different stage in the multi-stage network. In the example illustrated in
The machine-trained circuit 1300 also has an output memory 1312. The output of each neuron is stored in the output memory 1312. With the exception of the neurons in the first neuron stage, the inputs of the neurons in the other stages are retrieved from the output memory. Based on their inputs, the neurons compute their outputs, which again are stored in the output memory 1312 for feeding the next stage neurons (when intermediate neurons compute the outputs) or for providing the output of the neural network (when the final stage neurons compute their outputs).
In some embodiments, all the components 1305, 1310, 1312, and 1315 of the circuit 1300 are on one bonded layer (e.g., one IC die or wafer). In other embodiments, different components are on different layers. For instance, the neurons 1305 and 1310 can be on a different IC die than the IC die that includes one of the memories 1312 or 1315, or both memories 1312 and 1315. Alternatively, in some embodiments, the neurons 1305 are on one IC die while the neurons 1310 are on another IC die. In some of these embodiments, the IC die of neurons 1305 or neurons 1310 also include one or both of the parameter and output memories.
In the example illustrated in
To address this defect, a defect-curing process that configures the circuit 1400 removes the defective neuron 1405 from the first neuron set and replaces this defective neuron with the redundant neuron 1325 of this set. The defect-curing process assigns to the redundant neuron the machine-trained parameters that would have been assigned to the defective neuron, in order to allow this neuron to implement one of the neurons in the odd stages of the neural network 1450. This process also changes the storage and retrieval logic of the machine-trained circuit 1400 to ensure that the redundant neuron 1325 receives the desired input from and stores its output in the output memory 1312.
When the setting does not identify any defective neuron, the process 1500 loads (at 1515) the settings that allow the neurons to be configured with a user-design that has been provided in order to configure the neural network to implement a set of operations. After 1515, the process ends. On the other hand, when the setting identifies a defective neuron, the process 1500 removes (at 1520) the defective neuron from the pool of neurons, and replaces (at 1520) this defective neuron with the redundant neuron. The defect-curing process then assigns (at 1525) to the redundant neuron the machine-trained parameters that would have been assigned to the defective neuron to allow this neuron to implement operations of the defective neuron that are needed to implement the neural network. At 1530, the process changes the storage and retrieval logic of the machine-trained circuit to ensure that the redundant neuron receives the desired input from and stores its output in the output memory. Finally, at 1535, the process 1500 directs the neural network to start operating based on the new settings that were specified at 1525 and 1530. After 1335, the process ends.
While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For instance, one of ordinary skill will understand that while several embodiments of the invention have been described above by reference to machine-trained neural networks with neurons, other embodiments of the invention are implemented on other machine-trained networks with other kinds of machine-trained processing nodes.
The 3D circuits and ICs of some embodiments have been described by reference to several 3D structures with vertically aligned IC dies. However, other embodiments are implemented with a myriad of other 3D structures. For example, in some embodiments, the 3D circuits are formed with multiple smaller dies placed on a larger die or wafer. Also, some embodiments are implemented in a 3D structure that is formed by vertically stacking two sets of vertically stacked multi-die structures. Therefore, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
This application is a continuation of U.S. application Ser. No. 15/859,551, filed on Dec. 31, 2017, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 62/541,064 filed Aug. 3, 2017, the disclosure of which is incorporated herein by reference.
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