Patent Application
20120199960
Disclosed embodiments relate to integrated circuit (IC) devices, and more particularly to IC devices that include interposers.
Low cost, high performance, high yield and quality (reliability) are all goals for packaged IC devices. Conventional electrical connections between the IC die to a substrate/workpiece is thru wirebond or flip chip. Flip chip and multi-chip modules (MCMs) generally provide high performance, but due to the packaging process flow complexity are not low cost, and may be subject to yield and quality issues. Such assembly flows may also pose problems for applications that require fine pitch die connections. What is needed is a new interconnection methodology scalable to a wide variety of package types that provides a relatively simple packaging process flow that is low cost, provides high yield and quality, and is suitable for fine pitch die connections.
Disclosed embodiments describe connective arrangements for integrated circuit (IC) devices that provide both physical and electrical connection where a metal tape (e.g., copper tape, referred to herein as a metal trace or simply a “trace”) interposer provides the connections for an IC die flip chip bonded to the interposer and from the interposer to substrate/workpiece inputs/outputs (I/Os). Wirebonds (bond wires or stud bumps) can be used to provide interconnects to both the IC die and workpiece sides of the interposer. Cut-out region(s) in the interposer dielectric allow close metal trace approach to bond pads on IC die, which allows short lengths for the bonding interconnects. Overhang portions of the metal trace that extend over the edge of the interposer dielectric on one or both the IC die and workpiece sides can be part of interconnect(s).
The tape interposer can include both an inner aperture (cut-out) region and an outer aperture region. The inner aperture region can be used for IC die that have core bond pads for core connections, and can be in addition to periphery connections provided by the outer aperture region for conventional periphery bond pads. Disclosed embodiments can utilize a conventional wirebond machine to form bond wires or stud bumps to connect the IC die to the tape interposer, and then the tape interposer to the workpiece without the use of a complex bonding layout/sequence, such as conventional flip chip mounting of the IC die to the workpiece and multi-chip modules (MCMs), thus being low cost compared to the cost of such high performance package options. Moreover, due to the relative assembly process simplicity disclosed, disclosed embodiments solve yield and quality issues associated with the high packaging process flow complexity of the current high performance packages. Moreover, since the tape interposer can also provide fine pitch metal traces, disclosed embodiments provide a solution to fine pitch connections to the IC die.
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Interposer 120 has a first side 126, a second side 127, and a plurality of electrically conductive traces 128 that are on the first side 126. The electrically conductive traces 128 can comprise copper or other metal or metal alloy. Interposer 120 can be regarded as a universal interposer since the disclosed metal trace interconnection methodology can be used to first create the IC die 110 to interposer 120 connection, and then later, the interposer 120 itself can be used to bond to a workpiece (tape, laminate, leadframe, ceramic, etc.) to create the routing to the package's input/outputs (IO's), such as solder ball, leads, etc, for a wide variety of workpieces including different packages (e.g., ball grid arrays (BGAs such as MICROSTAR BGA (single flexible polyimide layer substrate), Fine-Pitch Ball Grid Array (FBGA), Flip Chip Ball Grid Array (FCBGA), Plastic Ball Grid Array (PBGA), Quad Flat No-Lead (QFN), Quad Flat Package (QFP), and Wafer Level Chip Scale Package (WLCSP), etc.), and IC die having different IC die layouts (e.g., different die sizes, die shapes, different pad layouts, etc.).
Bond pads 108 of the IC die 110 on the topside semiconductor surface 106 are revealed through inner aperture 121 and optional second innermost aperture 122 of the interposer 120. As noted above, optional second innermost aperture 122 is for access to core bond pads 108 on the IC die, while inner aperture 121 is for access to periphery bond pads 108 on the IC die 110.
The dielectric substrate 124 for interposer 120 can include an organic dielectric polymer such as a polyimide or other organic dielectric tape materials. The interposer 120 can be fabricated by positioning an adhesive material layered between a polyimide or other flexible dielectric polymer single layer and a metal layer (e.g., copper foil, or aluminum foil). As known in the art, at a first step, a surface of the dielectric polymer layer is covered with a film adhesive that is protected by a removable, protective plastic sheet. After punching apertures/through-holes at desired locations to form inner aperture 121 and optional innermost aperture 122 based on the layout of the IC die to be bonded thereto, the protective sheet covering the adhesive layer is peeled off, thereby exposing the adhesive surface. A thin copper foil is laminated to the adhesive surface, thereby creating a dielectric polymer/adhesive/copper flexible tape interposer precursor having multiple holes in the polymer layer and no holes in the metal foil, such a 3-layer polyimide/adhesive/copper flexible tape substrate. Such tape interposer precursors can be provided by the 3M Company, St. Paul, Mn 55144. When the polymer tape substrate provides sufficient adhesion to the metal foil, the adhesive layer can be excluded.
The metal foil may then be patterned to form the plurality of traces 128 thru pholithographic techniques such as masking and etching, with the pattern based on the layout of the pads to be contacted. The trace overhang portions can be formed or defined by extending a length of the metal trace 128 to match the position of the pads to be contacted.
First wirebond interconnects 141 shown as stud bumps 141 in
The IC die 110 can comprise as single IC die or a die stack. In one embodiment the IC can comprise a through-substrate via die, commonly referred to as a through-silicon via (TSV) die. In one particular embodiment the TSV die includes protruding TSV tips (e.g., copper tips) that extend out 5 to 15 microns from the bottomside surface 107 of the IC die 110 that enable bonding thereto. For example, in this particular embodiment, the TSV die can comprise a processor die having a memory die bonded to the protruding TSV tips of the processor die.
Second interconnects 149 shown as stud bumps 149 couple outer overhang portions 128B of respective traces 128 to respective contact pads 237 on the first side 232 of the workpiece 230. Although second interconnects 149 are shown as stud bumps 149, the second interconnect 149 may also comprise bond wires, TAB-like bonding, electroplating, solder dispensing or mechanical riveting.
In arrangement 300 shown in
In arrangement 320 shown in
The distal end of the overhang portion 128A can also include a hole (analogous to hole 137 shown in
Since disclosed embodiments can utilize a conventional wirebond machine to form bond wires and/or stud bumps to physically connect the IC die to the tape interposer, and then tape interposer to the workpiece without the use of a complex bonding layout/sequence, such as flip chip mounting of the IC die to the workpiece and multi-chip modules (MCMs), disclosed embodiments are low cost compared to the cost of such high performance package options. Moreover, due to relative simplicity of the disclosed assembly processes, disclosed embodiments solve yield and quality issues associated with the high packaging process flow complexity of the current high performance packages. Moreover, since the tape interposer can provide fine pitch metal traces, disclosed embodiments also provide a solution to fine pitch connections to closely spaced bond pads or other bonding features on the IC die. Moreover, disclosed embodiments are generally scalable to all packages types (e.g., various BGA packages, QFN, QFP, WLCSP, etc.).
The active circuitry formed on the IC die comprise circuit elements that may generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect the various circuit elements to provide an IC circuit function. As used herein “provide an IC circuit function” refers to circuit functions from ICs, that for example may include an application specific integrated circuit (ASIC), a digital signal processor, a radio frequency chip, a memory, a microcontroller and a system-on-a-chip or a combination thereof. Disclosed embodiments can be integrated into a variety of assembly process flows using a variety of workpieces to form a variety of devices and related products.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
