The present invention relates to a combing bump structure and a manufacturing method thereof.
Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits (ICs) that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.
The Redistribution Layer (RDL) process is to take the original designed IC's I/O pad and use wafer-level metal wiring process and bumping process to change the IC's contact point position. Bumping is an advanced wafer level process technology where “bumps” or “balls” made of solder are formed on the wafers in a whole wafer form before the wafer is being diced into individual chips.
Nowadays, low cost RDL/Bumping solution popularly processed, but incapable of processing fine-pitch product. PI beneath the bump upon passivation can be good buffer layer, but the weakness of PI is low adhesive strength to others like passivation itself or the metals. Thus, PI sometime easily peels off from the wafer when process is improperly controlled.
An embodiment of the present disclosure is related to a combing bump structure including a semiconductor substrate; a pad disposed on the semiconductor substrate; a conductive layer disposed on the pad; a solder bump disposed on the conductive layer; and at least two metal side walls disposed along opposing laterals of the solder bump respectively.
Another embodiment of the present disclosure is related to a combing bump structure including a first semiconductor substrate; a first pad disposed on the first semiconductor substrate; a first conductive layer disposed on the first pad; a first solder bump disposed on the first conductive layer; at least two first metal side walls disposed along opposing laterals of the first solder bump respectively; a second semiconductor substrate; a second pad disposed on the second semiconductor substrate; a second conductive layer disposed on the second pad; a second solder bump disposed on the second conductive layer; and at least two second metal side walls disposed along opposing laterals of the second solder bump respectively, and the second solder bump configured to form a solder joint with the first solder bump when the first and second solder bumps are brought together and a reflow process is performed.
Yet another embodiment of the present disclosure is related to a manufacturing method of combing bump structure, the manufacturing method includes providing a semiconductor substrate; forming a pad on the semiconductor substrate; forming a conductive layer on the pad; forming a solder bump on the conductive layer; and forming at least two metal side walls disposed along opposing laterals of the solder bump respectively.
The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes reference to the plural unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the terms “comprise or comprising”, “include or including”, “have or having”, “contain or containing” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. As used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In
In structure, a top of any of the metal side walls 160 is higher than a top of the solder bump 160. In other words, a vertical distance H1 between the top of the solder bump 150 and the top surface of the passivation layer 130 is lower than a vertical distance H2 between the top of the metal side wall 160 and the top surface of the passivation layer 130.
In some embodiments, the conductive layer 140 is or includes an under solder bump metallurgy (UBM) layer. For example, the UBM layer may be a composite layer of metal such as chromium followed by copper followed by gold in order to promote improved adhesion (with the chromium) and to form a diffusion barrier layer or to prevent oxidation (the gold over the copper).
In
Furthermore, metal pins 270 are disposed in the solder bump 250 and are protruded from the conductive layer 240 for further enhancing joint strength in follow-up processes. In some embodiments, a melting temperature of the metal side walls 260 is higher than a melting temperature of the metal pins 270.
In structure, a top of any of the metal pins 270 is higher than a top of the solder bump 250. In other words, a vertical distance H3 between the top of the solder bump 150 and the top surface of the passivation layer 130 is lower than a vertical distance H4 between the top of the metal pin 270 and the top surface of the passivation layer 130. Moreover, the top of any of the metal pins 270 can be lower than the top of any of the metal side walls 260.
Moreover, In
The second solder bump 352 is configured to form a solder joint 356 (shown in
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The second solder bump 452 is configured to form a solder joint 456 (shown in
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It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
This Application is a Divisional of U.S. application Ser. No. 15/592,181, filed on May 10, 2017.
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Number | Date | Country | |
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Parent | 15592181 | May 2017 | US |
Child | 16048357 | US |