Patent Application
20250006590
The present invention relates to the electrical, electronic, and computer arts, and more specifically, to integrated circuit structures and fabrication processes.
As very large scale integrated (VLSI) circuits have become more complex, with transistor feature sizes and pitches getting smaller, the number and density of wire traces in the metal layers has increased. Recently, metal layers have become density limited by physical limits to circuit performance (e.g., leakage currents and parasitic capacitances). In order to continue packing in more transistors, technology has advanced to use double-sided integrated circuit structures. As used herein, “double-sided integrated circuit structures” refers to integrated circuit structures in which an active device layer is located between a frontside structure (which includes multiple metal and dielectric layers) and a backside structure (which also includes multiple metal and dielectric layers). The sandwich or double-sided integrated circuit structure permits more metal traces to be formed, consistent with the physical limits of metal and dielectric materials. Another aspect of having wiring on both sides is to allow dedication of function to front versus back so that the wiring levels are equal at each side. This dedication avoids conflicts in use and simplifies the function on each side. For example: frontside is primary for circuit (signal) interconnection and backside is for power delivery.
Principles of the invention provide techniques for a double-sided integrated circuit with stabilizing cage.
In one aspect, an exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The metal body includes a first portion that is embedded in the plurality of first dielectric layers, wherein the first portion comprises a first layer of first metal; a second portion that is embedded in the plurality of second dielectric layers, wherein the second portion comprises a first layer of second metal; and a plurality of vias that interconnect the first portion to the second portion through the active device layer, wherein the first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.
In another aspect, a structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers, wherein the first portion comprises a first layer of first metal; a second portion that is embedded in the plurality of second dielectric layers, wherein the second portion comprises a first layer of second metal; and a third portion within the active device layer, wherein the third portion comprises a first layer of third metal. Also included are a first plurality of vias that interconnect the first portion to the third portion; and a second plurality of vias that interconnect the third portion to the second portion. The first layer of the first portion mechanically connects the first plurality of vias and the first layer of the second portion mechanically connects the second plurality of vias.
In still another aspect, a structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The metal body includes a first portion that is embedded in the plurality of first dielectric layers, wherein the first portion comprises a plurality of layers of first lines that are interconnected by a plurality of first via bars; a second portion that is embedded in the plurality of second dielectric layers, wherein the second portion comprises a plurality of layers of second lines that are interconnected by a plurality of second via bars; and a plurality of third via bars that interconnect the first portion to the second portion through the active device layer. The first and second lines and via bars of the metal body surround the perimeter of the structure and extend vertically from the semiconductor substrate to a top side of the structure.
In a further aspect, a method for making a structural enhancement for an integrated circuit structure includes: building an active device layer on a substrate; building smaller metal features at a frontside of the active device layer; building larger metal features onto the smaller metal features; inverting the structure; building smaller metal features adjacent to the backside of the active device layer; and building backside vias from the backside of the active device layer through the active device layer to smaller and larger metal features at the frontside of the active device layer. The steps of building the smaller metal features at the frontside of the active device layer; building the larger metal features onto the smaller metal features; building the smaller metal features adjacent to the backside of the active device layer; and building the backside vias from the backside of the active device layer through the active device layer to smaller and larger metal features at the frontside of the active device layer are carried out to form a continuous crackstop around the active device layer.
In a still further aspect, a method for making a structural enhancement for an integrated circuit structure includes: building a structure from a plurality of first metal features adjacent a substrate; building a plurality of second metal features on the first metal features, the second metal features being smaller than the first metal features; building an active device layer outward of the second metal features; building third metal features on the active device layer; building fourth metal features on the third metal features, to obtain an intermediate structure, the fourth metal features being larger than the third metal features; and completing a stack including the intermediate structure. The steps of building the structure and building the second, third, and fourth metal features are carried out to form a continuous crackstop around the active device layer.
In view of the foregoing, techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of:
A double-sided integrated circuit with improved durability of the active device layer.
A double-sided integrated circuit with improved resistance to cracking.
A double-sided integrated circuit with improved dissipation of electrostatic charges.
A double-sided integrated circuit with improved detection of cracks.
A double-sided integrated circuit with improved detection of moisture penetration.
A three dimensional mechanically bolting staple fill structure that can compensate for weaknesses in semiconductor structures using nanosheet transistors with backside power distribution networks (BSPDN).
Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
In developing methods for fabricating double-sided integrated circuit structures, we have discovered that these structures present certain challenges that were not appreciated earlier in their development. For example, the act of dicing a semiconductor wafer (typically, a 300 mm wide disc) into separate chips or dice presents challenges of mechanical cracking and electrostatic discharge.
The active device layer 202 includes a plurality of active devices 708, which are shown generally in this exemplary embodiment as nanosheet gate-all-around (GAA) field effect transistors (FETs). However, the GAA FETs are illustrative of only some embodiments: aspects of the invention are equally applicable to fin-type field effect transistors (FinFETs) or to other metal-oxide-semiconductor (MOS) transistor technologies. The FETs have gates, drains, sources, and channel regions as is known to the skilled artisan. Non-limiting exemplary aspects of gate pitch are discussed elsewhere herein.
In the chip 200, several protective devices (e.g., 300, 1400, 1600, 1900, 2100) are formed in the frontside structure 204 and in the backside structure 206. Each of these devices typically bridge across the active device layer 202 from the frontside structure 204 to the backside structure 206. Some of the protective devices can be connected to external circuitry via contacts 220 and controlled collapse chip connectors (C4 connectors) 222. C4 bumps are a non-limiting example of connecting the chip to a board or another chip, could also use pillars and pads, wire binding, etc. While
As mentioned above, double-sided integrated circuits present certain challenges in fabrication.
One challenge is a tendency for such circuits to crack or “unzip” across the active device layer, which incorporates many small structures at finer feature sizes that make it relatively weak compared to the sturdier frontside and backside structures with their coarser feature sizes. Although crack propagation in itself is a well-known problem of integrated circuit fabrication, crack propagation specifically through an active device layer, which is located between frontside and backside layers, is a novel problem. One or more embodiments of protective devices that are discussed in this disclosure (the crack stops, the crack sensor, the moisture sensor, and the fill structure (e.g., 3D)) address the cracking challenge in specific ways as described herein.
Another challenge is electrostatic discharge during fabrication and particularly during dicing and later chip handling. Electrostatic discharge is not a new problem, and there are design rules to address it by including conductive features to mitigate capacitive charges. However, conductive features have not previously been expected to bridge across an active device layer. Exemplary embodiments of one of the protective devices, the electrostatic guard ring, advantageously address the electrostatic discharge challenge, and electrically isolate individual chips from neighboring chips. Indeed, one or more embodiments advantageously provide electrical isolation of an active device layer located in middle of the BEOL stack.
As mentioned, the example chip 200 includes at least one crack stop 300, an electrostatic guard ring 1400 or 1500 (described below with reference to
In one or more embodiments, the crack stop 300 is in the form of a metal body, which is embedded into the frontside structure 204 and the backside structure 206. In one or more embodiments, the crack stop is a purely mechanical wall barrier (with no electrical connections) that extends throughout a semiconductor build stack. In one or more embodiments, the crack stop retards crack growth and/or inhibits moisture ingress into the active device region. Accordingly, in one or more embodiments the crack stop is in the form of a continuous ring that surrounds the perimeter of the active device region of the semiconductor die builds. The crack stop is also known as a Die Seal, Seal Ring, Moisture Barrier (MOB), Edge Seal, Edge Ring, etc. Each crack stop 300 incorporates a frontside or first portion 304 that includes a plurality of interconnected layers of frontside metal (“first metal,” to encompass embodiments in which the wafer is flipped as well as embodiments in which the wafer is not flipped) that are embedded in the dielectric layers of the frontside structure 204, a backside or second portion 306 that includes a plurality of interconnected layers of backside metal (“second metal,” to encompass embodiments in which the wafer is flipped as well as embodiments in which the wafer is not flipped) that are embedded in the dielectric layers of the backside structure 206, and a plurality of vias 302 that interconnect the frontside portion to the backside portion through the active device layer 202. In order to perform the functions of a crack stop, which include blocking, diverting, or stopping crack growth and propagation by dissipating crack growth and propagation energy, the crack stop 300 is formed as a continuous ring of interconnected line and via bars that entirely surround the perimeter of the semiconductor substrate in a “fishnet” type of structure (better seen in the plan view of
In one or more embodiments, the crack stop 300 includes bumper features 308, 310, 312, by which layers of metal are laterally offset and extended further out from the rest of the metal body (neighboring levels). For example, layers of metal may be offset toward a dicing edge or perimeter of a chip. Desirably, the bumper features guide crack propagation away from relatively fragile portions of the structure such as the active device layer or the interface between the substrate and the dielectric stack.
Referring to
At 604, the frontside structure 204 is completed by conventional methods to form intermediate structure 800 (as shown in
Another option for building the crack stop 300 is to start from the substrate with relatively large features, build on layers of increasingly smaller or finer features up to the active device layer, and then build on further layers of increasingly larger or coarser features up to the top of the stack. This method can advantageously enhance alignment of features across layers by avoiding the step(s) of flipping the wafer one or more times.
In the context of this patent application, “structural dielectric” includes tetraethylorthosilicate (TEOS), fluorinated TEOS (FTEOS), silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), and carbonitride (CN) materials as well as other similarly rigid and tough materials that will be apparent to the skilled worker. Generally, any type of dielectric that is presently used in semiconductor builds, including but not limited to so-called “low-K” dielectrics, can act as a structural dielectric that is tough and strong by comparison to the active device layer.
The via bars 1104, 1106 bridge across and reinforce the mechanically weaker active device layer 202. The via bars 1104, 1106 have larger via bar widths terminating above and below the active device layer 202, which advantageously provides increased metal density and larger metal to metal surface contact at the interface between the via bars 1104, 1106 and their corresponding frontside and backside structures 204, 206. The larger metal to metal surface contact increases adhesive and mechanical strength and robustness. The via bar width at the interface is varied by mixing the via bar orientations, which strengthens the interfaces between via bars and metal lines at each side of the active device layer by providing uniform density of via bar widths in the crack's growth path trajectory.
The embodiments of
In one or more embodiments, the electrostatic guard ring 1400 or 1500 can look very similar to a crack stop but does not necessarily need to be continuous and can have electrical properties. It can also be significantly smaller or have a smaller overall footprint. In one or more embodiments, the guard ring connects and grounds to the semiconductor build's substrate through an active device or trench structure. The guard ring electrically isolates the central active device region of the semiconductor build from neighboring devices due to its structure being grounded to the semiconductor substrate. In one or more embodiments, its primary function is to electrically isolate an active device semiconductor die from neighboring die or semiconductor builds. Its presence assists in mitigating charging and arcing events as well as attracting any present ionic or electrical defects towards its structure and away from the active devices. Either of the guard rings 1400 or 1500 incorporates a frontside structure 1404 in the frontside layers 204 and a backside structure 1406 in the backside layers 206, which are mechanically and electrically connected by a plurality of vias 1402 that penetrate the active device layer 202 so that the guard ring bridges across the active device layer. The frontside structure 1404 is grounded by electrical connections to patterns 212 (shown in
In the guard ring 1400, the frontside structure or first portion 1404 connects to the carrier patterns 212 by way of a plug 1412. The plug 1412 may be metal or polysilicon. Alternatively, in the guard ring 1500, the frontside structure or first portion 1404 connects to the carrier patterns 212 by way of a region 1512 of semiconductor that is irradiated or doped to be more conductive than surrounding bulk semiconductor.
The electrostatic guard ring 1400 or 1500 can be built according to similar methods as the crack stops 300, 1100, 1200, or 1300.
In one or more embodiments, each of the structures 1902, 1904 includes a plurality of vias 1908 with horizontally-extending fingers 1906 protruding from the vias of each structure toward the vias of the other structure so that the fingers of the two structures are interleaved/interlocked with each other.
In one or more embodiments, the moisture sensor 1900 is located inside an active prime region of a chip. In one or more embodiments, the moisture sensor 1900 is located outside of an active prime region in a kerf/frame/dicing channel portion of a wafer. In one or more embodiments, the moisture sensor 1900 is disposed in at least one of the substrate, the frontside structure 204, the active device layer 202, or the backside structure 206. In one or more embodiments, the moisture sensor 1900 is disposed in at least two of substrate, frontside structure, active device layer, and/or backside structure. The moisture sensor 1900 can be electrically tested from bump pads or bumps 1918 that are electrically connected to a first sense pad 1920 and a second sense pad 1922.
Referring to
It will accordingly be appreciated that semiconductor fill, in general, is quite pertinent in semiconductor processing and device manufacturing to ensure uniform processing and construction. One or more embodiments advantageously provide a novel fill structure that can be leveraged to: 1. Increase mechanical stability/rigidity of weak materials and layers located in middle and in-between tougher/stronger BEOL dielectric layers; and/or 2. Prevent delamination/peeling apart of this weaker nanosheet layer region. Nanosheet BSPDN device construction will generally use traditional fill. But the introduction of this mechanically weak region introduces into the BEOL chip-package interaction (CPI) related vulnerabilities, which can advantageously be overcome with mechanical enhancement in accordance with aspects of the invention.
Now continuing, note the substrate 3201, buried oxide (BOX) 3203, and nanosheet stack region 3205 typically including alternating layers of Si and sacrificial SiGe, in a known manner. The nanosheets are patterned in
In one or more non-limiting exemplary embodiments, the crackstop can be configured as a single continuous ring/perimeter wall around the perimeter of the die, on the order of tens to hundreds of nanometers (nm), and can be formed, for example, using all the BEOL, metal, and via levels. In contrast, in one or more non-limiting exemplary embodiments, the fill structure can include hundreds or tens of thousands of discrete individual “bolts” with critical dimension on the order of 10-1000 nm and can make use, for example, of 3-10 BEOL levels, 2-5 metal levels, 1-5 via levels, and can be, for example, discrete individual squares. In terms of the die build, in one or more non-limiting exemplary embodiments, both fill and crackstop structures provide mechanical strength with being electrically connected to the circuit; the fill structures can be located anywhere, while the crackstop structures can be located on the perimeter. In terms of purpose and function, the crackstop structure can be configured, for example, to resist lateral (shear) forces, to block cracks (and moisture), and/or to provide a hermetic seal. The fill structure can be configured, for example, to resist vertical (tensile) forces and/or to facilitate processing uniformity, and typically, as a plurality of discrete bolts, does not provide a hermetic seal. Other embodiments could have different dimensions, configurations, and/or functionality.
It is worth noting that, as used herein, The “active region” is the region of a chip that includes power and signal wiring and active devices such as transistors. The active region or active device layer (ADL) can contain transistors, such as field effect transistors, contacts, and other well-known front end of line (FEOL)/middle of line (MOL) features. One or more embodiments include vias through the device region; embodiments with wires or vias and wires in the device region are also possible. One or more embodiments are useful in semiconductor circuits with gate pitch less than 100 nm.
Thus, referring now to
As used herein, note that “via bars” unless otherwise specified can include multilayer structures thereof. Furthermore, sensors, such as crack sensors and/or moisture sensors, can be built in the top, bottom, across the active region, or combination. In addition, considering, e.g., crack sensors and methods for fabrication same, in one or more embodiments, the metal body metal body electrically interconnecting first and second sense pads can be, for example, any of the p-line stitch (crack sensor) embodiments disclosed herein. Furthermore, in various moisture sensing embodiments, a capacitor that couples a first sense pad to a second sense pad does so via capacitive coupling.
As noted, and as will be appreciated by the skilled artisan given the teachings herein, structures described herein can be made in various ways. For example, referring to the crack stops and to the guard ring, such structures can be formed in a “backside first” manner 2300 (as shown in
One or more embodiments accordingly provide a structure including brittle regions disposed between two substrates, each substrate having a side in contact with the brittle region and each substrate have a side not in contract with the brittle region; and a through via extending from the sides of each substrate in contact with the brittle region and extending through the brittle region. This structure can be in an active or non-active (e.g., “fill”) region.
In one or more embodiments, the structure further includes, and/or the previously recited elements are incorporated into, an element selected from the group consisting of a crackstop, a guard ring and a crack sensor.
Some embodiments include a capacitive structure as moisture sensor.
Some embodiments include a guard ring that passes through the brittle region and also into at least one of each substrate.
In some embodiments, the through via has a non-uniform cross-sectional dimension along the length of the through via.
Some embodiments include relatively “tall” vias through weak/brittle region(s).
Some embodiments include vias of varying height, starting, and/or terminating locations; for example, encompassing a plurality of through vias of varying length/height between a plurality of locations in the structure.
Some embodiments provide a crackstop with a bumper structure on the front and/or backside.
Given the discussion thus far, and referring, for example, to the general description of the crack stops, it will be appreciated that, in general terms, an exemplary structure, according to an aspect of the invention, includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The metal body includes a first portion that is embedded in the plurality of first dielectric layers, wherein the first portion comprises a first layer of first metal; a second portion that is embedded in the plurality of second dielectric layers, wherein the second portion comprises a first layer of second metal; and a plurality of vias that interconnect the first portion to the second portion through the active device layer, wherein the first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.
In one or more embodiments, the first portion has diffusion barrier liners on surfaces of its metal lines and vias that face toward the active device layer and the second portion has diffusion barrier liners on surfaces of its metal lines and vias that face toward the active device layer.
In some instances, the plurality of vias is a first plurality of vias, and the structure further includes a second layer of the first portion; a second layer of the second portion; and a second plurality of vias that interconnect the second layer of the first portion to the second layer of the second portion, wherein the second layer of the first portion mechanically connects the second plurality of vias and the second layer of the second portion mechanically connects the second plurality of vias.
The plurality of vias can be, for example, via bars.
Optionally, the first portion comprises a plurality of layers of first metal and a plurality of first portion vias that interconnect the layers of first metal, wherein the first portion extends from the active device layer through the plurality of first dielectric layers to the semiconductor substrate.
Optionally, the second portion comprises a plurality of layers of second metal and a plurality of second portion vias that interconnect the layers of second metal, wherein the second portion extends from the active device layer through the plurality of second dielectric layers to a top side of the structure.
The first metal and the second metal can optionally be the same metal.
In some embodiments, the metal body is electrically grounded to the semiconductor substrate.
Some embodiments further include a ground pad at a top side of the structure, wherein the metal body is electrically grounded to the ground pad.
In some cases, the first layer of first metal is a first metal plate and the first layer of second metal is a second metal plate.
Optionally, a wiring level is provided in the active device layer.
Referring, for example, to
Referring again, for example, to the general description of the crack stops, it will be appreciated that another exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The metal body includes a first portion that is embedded in the plurality of first dielectric layers, wherein the first portion comprises a plurality of layers of first lines that are interconnected by a plurality of first via bars; a second portion that is embedded in the plurality of second dielectric layers, wherein the second portion comprises a plurality of layers of second lines that are interconnected by a plurality of second via bars; and a plurality of third via bars that interconnect the first portion to the second portion through the active device layer. The first and second lines and via bars of the metal body surround the perimeter of the structure and extend vertically from the semiconductor substrate to a top side of the structure.
In some cases, a first group of the plurality of third via bars are disposed with wider ends of the first group of via bars toward the first portion and a second group of the plurality of third via bars are disposed with wider ends of the second group of via bars toward the second portion. Optionally, the first group of via bars is intermingled with the second group of via bars in an alternating fashion.
Optionally, the first portion has diffusion barrier liners on surfaces of its metal lines and vias that face toward the active device layer and the second portion has diffusion barrier liners on surfaces of its metal lines and vias that face toward the active device layer.
In some instances, a first via bar of the plurality of third via bars extends from a first layer of the first portion to a first layer of the second portion and a second via bar of the plurality of third via bars extends from a second layer of the first portion to a second layer of the second portion.
In some embodiments, at least one of the plurality of third via bars extends from one of the layers of the first portion through at least another of the layers of the first portion, through the active device layer, and through at least one of the layers of the second portion to another of the layers of the second portion.
In some cases, the metal body incorporates a bumper feature by which a layer of the first portion that is nearest to the active device layer is laterally offset from other layers of the first portion.
In some cases, the metal body incorporates a bumper feature by which a layer of the second portion that is nearest to the active device layer is laterally offset from other layers of the second portion.
In some instances, the metal body incorporates a bumper feature by which a layer of the first portion that is nearest to the substrate is laterally offset from other layers of the first portion.
Optionally, the metal body incorporates bumper features by which layers of the first portion that are nearest to the active device layer and nearest to the substrate are laterally offset from other layers of the first portion, and by which a layer of the second portion that is nearest to the active device layer is laterally offset from other layers of the second portion. For example, the bumper features are laterally offset toward an outer edge of the structure.
In some embodiments, a bottom end of the first portion is embedded into the substrate.
Optionally, a layer of structural dielectric is located adjacent to the substrate, and a bottom end of the first portion is embedded into the layer of structural dielectric.
Optionally, active devices are embedded into the active device layer among the plurality of third via bars.
In some instances, the first portion comprises a first group of features that have smaller critical dimensions adjacent to the active device layer and comprises additional groups of features that have increasingly larger critical dimensions toward the substrate.
In some cases, the second portion comprises a first group of features that have smaller critical dimensions adjacent to the active device layer and comprises additional groups of features that have increasingly larger critical dimensions away from the active device layer.
In one or more embodiments, the plurality of first lines and the plurality of first via bars are interconnected in a first fishnet pattern, and the plurality of second lines and the plurality of second via bars are interconnected in a second fishnet pattern.
Now, referring to the “backside last” manner 2400 as shown in
Some embodiments further include building a first via through the active device layer into the substrate; and stripping the substrate to reveal a backside of the active device layer. Optionally, one or more of: the first via, the frontside smaller metal features, the larger metal features, the backside smaller metal features, and the backside vias are created using a damascene process. Optionally, one or more of: the first via, the frontside smaller metal features, the larger metal features, the backside smaller metal features, and the backside vias are created using a subtractive process.
In one or more embodiments, the steps of building the first via and building the backside vias are carried out such that at least one via selected from a group consisting of the first via and the backside vias is tapered in a first direction and at least one other via selected from the group consisting of the first via and the backside vias is tapered in a second direction opposite the first direction.
Now, referring to the “backside first” manner 2300 as shown in
Optionally, one or more of the first, second, third, and fourth metal features are created using a damascene process. Optionally, one or more of the first, second, third, and fourth metal features are created using a subtractive process.
In one or more embodiments, the steps of building the structure and building the second, third, and fourth metal features are carried out such that at least one metal feature selected from a group consisting of the first, second, third, and fourth metal features is tapered in a first direction and at least one other via selected from the group consisting of the first the first, second, third, and fourth metal features is tapered in a second direction opposite the first direction.
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.
Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. For example, the skilled artisan will be familiar with epitaxial growth, self-aligned contact formation, formation of high-K metal gates, and so on. The term “high-K” has a definite meaning to the skilled artisan in the context of high-K metal gate (HKMG) stacks, and is not a mere relative term. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products.
An integrated circuit in accordance with aspects of the present inventions can be employed in essentially any application and/or electronic system. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments disclosed herein.
The illustrations of embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. It should also be noted that, in some alternative implementations, some of the steps of the exemplary methods may occur out of the order noted in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may sometimes be executed in the reverse order, depending upon the functionality involved. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Terms such as “bottom”, “top”, “above”, “over”, “under” and “below” are used to indicate relative positioning of elements or structures to each other as opposed to relative elevation. If a layer of a structure is described herein as “over” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. If a layer is described as “directly on” another layer, direct contact of the two layers is indicated. As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.
The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit thereof. The embodiments were chosen and described in order to best explain principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.76(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, the claimed subject matter may lie in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
Indeed, the descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
