Patent Application
20100288525
This application is directed, in general, to electronic device packaging and, more specifically, to a sealed electronic device package, and, to methods of manufacturing such packages.
This section introduces aspects that may help facilitate a better understanding of the inventions. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
For many electrical applications, it is desirable to package an electronic device inside a sealed chamber. It is still necessary, however, to provide external electrical connections between the device and other devices that are external to the sealed device package. Some processes to manufacture sealed device package are material intensive and time consuming thereby increasing the cost of the resulting sealed device package. Moreover, the external electrical connections may not be properly sealed or may lose their seal causing the entire chamber to lose its seal. This, in turn, can cause the device to malfunction or fail earlier than its expected product lifetime.
One aspect of the disclosure provides an apparatus that comprises an electronic device package. The package includes an electronic device on a first planar substrate, and, a second planar substrate bonded to the first planar substrate so as to form an interior chamber housing the electronic device. The package includes a plurality of electrically conductive pins, each of the pins passing through a hole in one of the first and second planar substrates. A first end of each pin is located in the interior chamber and is electrically coupled to the electronic device. A second end of each pin is located on an exterior side of the one of the first and second substrates. An inorganic sealant surrounds at least one of the first end or the second end for each of the pins.
Another embodiment is a method. The method comprises providing a first planar substrate with a plurality of electronic devices thereon. The method comprises providing a second planar substrate, one of the first and second substrates having a plurality of holes there through. The method comprises forming electrically conductive pins that traverse the holes such that a portion of each pin is surrounded by an inorganic sealant. The method comprises bonding the second substrate to the first substrate to form a chamber housing one or more of the electronic devices, first ends of the pins protruding to an exterior of the chamber and second ends of the pins making electrical contact with the one or more the electronic devices.
The various embodiments can be understood from the following detailed description, when read with the accompanying figures. Various features may not be drawn to scale and may be arbitrarily increased or reduced in size for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The present disclosure presents an electronic device package that may be formed while electronic devices are coupled to a common single substrate. It was discovered that the cost and reliability of a sealed electronic device package can be improved by performing packaging steps while several electronic devices are still coupled to the same substrate. This is in contrast with certain labor and time consuming packaging processes that package individual electronic devices after they have been made and separated from each other on the substrate.
Additionally, as part of the disclosed packaging process, electrical connections from the package to devices external to the package include electrically conductive pins and an inorganic sealant. The pins provide a reliable conductive path, and, the inorganic sealant facilities forming and retaining a sealed package (e.g., hermetically sealed package). This is in contrast with certain packaging processes that use an electrochemical process to form electrical connections. Such an electrochemical process to form external electrical connections can include metal seed layer deposition followed by the electro-deposition of metal into through-holes. In addition to being costly and time consuming, the electrochemical process can result in some holes being partially filled. Thus, the chamber's vacuum or special atmosphere can be lost due to gases being able to leak through voids in the holes that are not sealed, when electro-deposited metal is used to form such through-substrate electrical connections.
One embodiment is an apparatus comprising a sealed electronic device package. The electrical apparatus could be an electrical apparatus component of a telecommunications system that uses a sealed electronic device package. Non-limiting examples of other electrical apparatus include magnetometers, light sensors (e.g., infrared sensors, visible light sensors), accelerometers, spatial light modulators, microelectromechanical system (MEMS) and/or optoelectronic (OE) devices of integrated circuits (IC), that could include the device package.
As illustrated in
The electronic device 105 could include one or more devices that are manufactured on or in the substrate (e.g., the first substrate 110). In some embodiments, the devices 105 are separately manufactured on a separate substrate 141 and then mounted on the single common substrate 110. The electronic device 105 could be an IC, a MEMS device, OE element (e.g., photon detectors, infrared detectors), or, combinations thereof. At least a portion of the substrate 110 forms part of the package 102.
At least one of the substrates 110, 112 is composed of a solid material that is conducive to the manufacture or mounting of the device 105 thereon. Additionally, both substrates 110, 112 are composed of solid materials that can form a gas-impervious or vacuum seal. In some preferred embodiments, the substrates 110, 112 are composed of materials that can be molded, patterned or implanted with dopants to facilitate fabricating the device 105 on or in the substrate 110. Such materials can also facilitate shaping or patterning one or both of the substrates 110, 112 to define the chamber 115 or form the holes 125. Example substrate materials include metals (e.g., aluminum, or brass), inorganic semiconductors (e.g., silicon, gallium arsenide), or inorganic insulators (e.g., silicon oxide, lithium niobate). Substrates composed only of metal may not be desirable in some embodiments where electrical connection could contact the substrate. In such cases, however, an electrically insulated metal substrate could be used. Certain porous materials or organic materials, such as plastics, are generally excluded as substrates because gases (e.g., air) can pass through them. It is possible to use such materials, however, if their outer surface can be entirely covered with a gas-impervious material (e.g., a plastic layer coated with a metal foil). In some cases it is desirable for the substrates 110, 112 to be composed of the same material because this minimizes thermal mismatches that otherwise impart stress that could detrimentally affect the performance of the device 105.
As noted above, in some preferred embodiments, portions of the first substrate 110 are components of the electronic device 105. That is, parts of the first substrate 110 are used to fabricate component parts that are necessary to the operation of the electronic device 105. Some of these embodiments have the advantage of facilitating package's 102 formation as a part, or an extension, of substrate-level (e.g., wafer-level) device processing. Some of these embodiments of the device 105 components and substrate 110 have the same the same thermal expansion coefficient. This is in contrast to the ceramic packaging a silicon-based device 105, where it can be difficult to find a ceramic material with matching thermal characteristics. A sufficient mismatch in the thermal expansion coefficient device 105 and substrate 110 can cause the device to become separated from the substrate 110 during thermal stresses experienced during the package's 102 manufacture, handing or end use.
In other cases, however, the electronic devices 105 are separately made and then mounted to one of the substrates 110, 112. This may be an advantage when processes to construct the device 105 on or in the substrate 110 are incompatible with other steps in the packaging process. E.g., in some cases, high temperature process steps used to form the holes 125, or, to seal the pins 120 in the holes 125, may damage an IC, MEMS or OE device 105. To avoid this, the holes 125 can be formed and the pins 125 sealed, before the devices 105 are mounted on the substrate 110. Alternatively, as illustrated for the embodiment shown in
As illustrated in
In some cases, instead of using a separate spacer substrate, one of the substrates is configured to have spacer structures built-in. For example,
It can be important for the bond between substrates 110, 112, 142 to be a gas-impervious bond so that a sealed chamber 115 is formed. In some preferred embodiments, a bonding agent is used to seal the substrates together. For instance,
In some cases, it is advantageous for one of the first or seconds substrates 110, 112 to be, or include, a semiconductor layer, and, the other of the first or second substrate 110, 112, to be, or include, a glass layer. For instance, using a transparent glass substrate allows the packaged device 105 to be inspected for proper functioning. For instance, the device 105 (e.g., configured as a light sensor) communicates with other devices external to the package through the glass substrate.
The combination of semiconductor and glass substrates 110, 112, can sometimes also be conducive to forming an anodic bond between the substrates. Forming an anodic bond can remove the need to use a bonding agent. For instance,
In some preferred embodiments, the interior chamber 115 is vacuum-sealed or hermetically-sealed from an external environment (e.g., air or water) surrounding the package 105. In some cases, a vacuum or hermetic seal is necessary for the proper function of the electronic device 105 over the length of its intended life-time. For the purposes of the present disclosure, a vacuum-sealed interior chamber 115 is defined as having a pressure of about 1 mTorr or lower. A hermetically-sealed interior chamber 115 is defined as in MIL-Std-883 document, which is incorporated by reference herein in its entirety. One of ordinary skill in the art would be familiar with the equipment and procedures to measure the extent of vacuum or hermeticity present in a sealed chamber. A gas impervious material permits the retention of the vacuum or hermetic seal of the chamber 115 for the lifetime of the package 102.
As shown in
The pin's head diameter 160 is carefully selected to provide one or more beneficial features. The head diameter 160 is large enough to prevent the pins 120 from passing entirely through the holes 125. In some cases, the head diameter 160 large enough to provide bonding locations for the sealant 140 on the head surface 164 that faces the substrate 110 that the pin 120 is passed through, and, to provide locations for the electrical connections to be formed to the device 105 or external devices, on the head surface 164 that faces away from the substrate 110 that it passes through. The head diameter 160 is small enough to not cover up a substantial amount of the substrate 110 because this would provide to accommodate the device 105 and the package's 102 size could be unnecessarily large.
Having the pin's ends 132 above the substrate's surface 135 can facilitate forming an electrical connection to the pin 120. In some embodiments, the pin 120 bodies 152 are long enough to pass entirely through the substrate 110 so that the end (e.g., second end 132 in
In some cases, at least one of the pins 120 passes through a hole 125 of the first substrate 110 (
In some embodiments, it is preferable for the inorganic sealant 140 to be substantially free of organic material. The presence of certain organic material (e.g., plastics) could permit atmosphere to exchange through the sealant 140 and thereby not permit a sealed chamber 115 to be formed or retained. The term organic material as used herein refers to carbon-containing molecules. The term substantially free as used herein refers to less than about 10 wt % of the organic material.
Some preferred embodiments of the electrically conductive pins 120 are composed of, or include, metal pins. In some cases, the metal pins 120 include copper or bronze plated with nickel, gold, a nickel-gold alloy, or other metals that can facilitate forming a bond when using a metal containing solder as the inorganic sealant. As an example, Au—Ni plated phosphor-bronze pins (e.g., Mill-Max Mfg. Corp., Oyster Bay, N.Y.), and, a gold-tin alloy can be used as the pins 120 and inorganic sealant 140, respectively. In other cases, such as when a melted sintered glass (e.g., glass sponge or glass frit) is used as the inorganic sealant 140, the metal pins 120 are preferable composed a high melting point metal (e.g., melting point of about 1000° C. of higher). In still other cases, however, are low temperature glass seals (e.g., DM2700 glass seal by Dimat, Byfield, Massachusetts, with a melting point of about 320° C.) can be used as the inorganic sealant 140. As an example, tungsten metal pins 120 can be used with a sintered glass inorganic sealant 140 (e.g., Schott Hermes™; NEC Schott Components Corp, Japan) which is melted to form a gas-impervious seal between the pin 120 and the hole 125.
When the first or second substrate 110, 112 is composed of a semi-conducting or conducting material (e.g., silicon or a metal layer) the electrically conductive pins 120 or an electrically conductive inorganic sealant 140 can cause an electrical short-circuit in certain types of electronic devices 105 (e.g., ICs). In these instances, it is desirable for the package 102 to further include an insulating layer 170 (
In some embodiments, the insulating layer 170 is or includes silicon oxide, silicon nitride, or silicon oxynitride. In some preferred embodiments the insulating layer 170 conformally coats the entire substrate 110, 112, including the sidewalls 172 of the holes 125 (
As illustrated for the embodiment shown in
In some cases, the package 105 can be the entire apparatus 100. In other cases, the apparatus 100 can include other components that the package 105 is directly or indirectly coupled to. For instance, the apparatus 100 can further include a mounting board 180 (e.g., a printed circuit board) having contact structures 182 (e.g. solder balls), and, the second ends 132 of the pins 120 can be electrically coupled to the contact structures 182. Conductive lines or pads 184 on the mounting board 180 can run from the contact structures 182 to other electrical components on the boards 180 (e.g., other device packages, not shown), or, to receptacles 186 to facilitate plugging the apparatus into other electrical apparatuses. Wire bonds, plugs, ball grid arrays 187 or other conventional bonding structures could be used to facilitate electrically coupling.
Still another embodiment is a method. In some cases the method comprises manufacturing a sealed electronic device package. Any of the embodiments the apparatuses 100, 300 and packages 102 discussed in the context of
In some embodiments, providing the plurality of electronic devices on the first substrate includes mounting prefabricated electronic devices 105 to the first substrate 110. That is, the devices 105 are fabricated in a separate process and then mounted to the substrate 110 (see e.g.,
For example, in some embodiments, a mask (e.g., a photoresist layer, not shown) can be deposited on the substrate 110 and then patterned using conventional lithographic techniques so that only those portions of the substrate 110 in the vicinity of the holes 125, are exposed through the mask. The exposed portion of the substrate can then be covered with a sealant such as solder by spray coating dip coating or other conventional techniques. Alternatively, the entire surface of the substrate 110 can be cover with the sealant, and then a mask layer is deposited and patterned to remove the mask over all portions of the substrate except in the vicinity of the holes 125. Remaining portions of the mask can then be removed by conventional thermal or chemical methods.
The method can include forming electrically conductive pins that traverse the holes such that a portion of each pin is surrounded by the inorganic sealant.
Based on the present disclosure, one skilled in the art would appreciate that variations in the above sequence of steps are possible. For example,
Bonding the second substrate 112 to the first substrate 110 can include heating the substrates 110, 112 to melt bonding agents 150 (e.g., composed of solder or sintered glass) deposited on one or both substrates 110, 112. One skilled in the art would understand how to use different types of solder, with different melting points, as the sealant 140 and bonding agent 150, e.g., so that an already formed seal 140 is not disturbed by melting the bonding agent 150. In some embodiments, the substrates 110, 112 are directly bonded together. For instance, in some cases the first and second substrates are anodically bonded together. For example, consider the case when the second substrate 112 is composed of glass, such as Pyrex® glass or other high sodium-content glass, and, the first substrate 110 (or spacer substrate 142 of
In some preferred embodiments, treating the sealant 140, and, bonding the substrates 110, 112 together, as discussed in the context of
With continuing reference to
One skilled in the art would be familiar with additional steps to complete the manufacture of the apparatus. For instance, the method can include further including attaching the package 102 to a mounting board 180 by solder bonding 132 second ends of the pins (e.g., exposed ends of the pins) to contact pads 177 on the board 180 (
Although some embodiments of the disclosure have been described in detail, those of ordinary skill in the art should understand that they could make various changes, substitutions and alterations herein without departing from the scope of the disclosure.
