The present invention relates to an IC substrate with over voltage protection functions, more particularly, to an IC substrate provided with a structure having multiple over voltage protection devices.
A conventional over voltage protection device is installed near I/O ports on a printed circuit board to protect internal IC devices according to demands by each IC device. However, such design requires installing independent over voltage protection devices in accordance with requirements of respective circuits to prevent respective IC devices from being damaged by surge pulses.
Please refer to
In order to protect the IC device, several over voltage protection devices are frequently proposed. However, those over voltage protection devices need to install individual protection devices on a printed circuit board according to actual demands after the IC device was manufactured and installed near the I/O ports on the printed circuit board. Therefore, such design has the disadvantages of high design costs, wasting limited space, and providing incomplete protection for the IC device.
Therefore, there is a need to provide an IC substrate with over voltage protection functions. In this substrate, a plurality of over voltage protection devices are provided simultaneously to solve the problems with the prior arts that are unable to provide the over voltage protection or to eliminate the inconvenience in the prior arts that needs to install individual protection devices on a printed circuit board. The present invention provides an IC substrate with over voltage protection functions to eliminate such inconvenience.
An object of the present invention is to provide an IC substrate with over voltage protection functions and a method for manufacturing the same and thus, the IC device can be protected against the presence of surge pulses.
Another object of the present invention is to provide an IC substrate with over voltage protection functions and a method for manufacturing the same, wherein the grounding lines are disposed on a lower surface of a substrate and thus, the space is saved and the costs are reduced.
Still another object of the present invention is to provide a substrate having a plurality of over voltage protection devices, so that the design costs are reduced, the space is saved and the unit costs need for installing protection device on the IC circuits are reduced.
Further still another object is to provide an IC substrate with over voltage protection functions and a method for manufacturing the same, wherein the substrate can be designed by all kinds of IC packaging methods, such as DIP and SMD.
Another object of the present invention is to provide an IC substrate with over voltage protection functions and a method for manufacturing the same, wherein the protection circuits are installed after the IC is packaged.
In order to accomplish the above objects, the IC substrate comprises a substrate, and a grounding conductor layer for forming a grounding terminal. The grounding terminal is disposed on the lower surface of the substrate and extending to an upper surface of the substrate, thereby to expose one or more terminals on the upper surface of the substrate. One or more variable resistance material layers are disposed on exposed terminals of the grounding conductor layer. The grounding conductor layer terminals are electrically connected with the variable resistance material layers. A plurality of conductor layers form electrode terminals. Each conductor layer is disposed on the substrate and overlays on each of the variable resistance material, so as to form a connection with each of the variable resistance material layers. In practical application, the substrate is made of ceramic substrate or PCB.
In order to understand the technical contents and features of the present invention with ease, the present invention is described by referring to the accompanying drawings.
The present invention will be illustrated according to the following drawings, wherein:
a is a top view of an IC device disposed on a conventional substrate;
b is a sectional view of an IC device disposed on a conventional substrate;
a, 2b and 2c are sectional views of an IC substrate formed with over voltage protection functions according to an embodiment of the present invention;
d and 2e are top views of an IC substrate formed with over voltage protection functions according to the embodiment of the present invention;
a and 6b are top views of a multi-layer IC substrate formed with over voltage protection functions according to an embodiment of the present invention;
a, 7b and 7c are sectional views of a multi-layer IC substrate formed with over voltage protection functions according to an embodiment of the present invention;
a, 8b, 8c, 8d and 8e are sectional views of a BGA IC package formed with over voltage protection functions according to an embodiment of the present invention;
f is a top view of a BGA IC package formed with over voltage protection functions according to an embodiment of the present invention;
a and 9b are sectional views of the IC substrate with over voltage protection functions according to an embodiment of the present invention; and
a, 10b, 10c, 10d, 10e and 10f are sectional views of an IC substrate formed with over voltage protection functions according to an embodiment of the present invention.
The embodiments of the present invention are described with reference to the drawings. The same elements in the drawings have the same reference numerals.
a, 2b and 2c are sectional views of an IC substrate formed with over voltage protection functions according to an embodiment of the present invention. As shown in
When a surge pulse occurs, the energy of the surge pulse will enter the electrode terminals (51) to propagate to the grounding terminal (53) through the variable resistance material layers (54). Because the nature of the variable resistance materials and its structure, the energy of the surge pulse will be released evenly to the grounding lines and thus, the IC device (50) will not be damaged and the object to protect the IC device is achieved.
a and 6b are top views of a multi-layer IC substrate formed with over voltage protection functions according to an embodiment of the present invention. As shown in
As shown in
a, 7b and 7c are sectional views of forming a multi-layer IC substrate formed with over voltage protection functions according to an embodiment of the present invention. As shown in
As shown in
As shown in
Please note that the variable resistance material layers can be made of non-linear resistance materials.
a, 8b, 8c, 8d and 8e are sectional views of a Ball Grid Array (BGA) IC package formed with over voltage protection functions according to an embodiment of the present invention.
As shown in
a and 9b are sectional views of the IC substrate with over voltage protection functions according to an embodiment of the present invention.
a, 10b, 10c, 10d, 10e and 10f are sectional views of an IC substrate formed with over voltage protection functions according to an embodiment of the present invention.
According to an embodiment of the present invention, a method for forming an IC substrate with over voltage protection functions comprises the following steps. As shown in
Although the invention has been disclosed in terms of preferred embodiments, the disclosure is not intended to limit the invention. The invention still can be modified or varied by persons skilled in the art without departing from the scope and spirit of the invention which is determined by the claims below.
Number | Date | Country | Kind |
---|---|---|---|
91113365 A | Jun 2002 | TW | national |
Number | Name | Date | Kind |
---|---|---|---|
4959505 | Ott | Sep 1990 | A |
4993142 | Burke et al. | Feb 1991 | A |
5831510 | Zhang et al. | Nov 1998 | A |
5884391 | McGuire et al. | Mar 1999 | A |
6013358 | Winnett et al. | Jan 2000 | A |
6160695 | Winnett et al. | Dec 2000 | A |
6162159 | Martini et al. | Dec 2000 | A |
6166914 | Sugiyama et al. | Dec 2000 | A |
6223423 | Hogge | May 2001 | B1 |
6242997 | Barrett et al. | Jun 2001 | B1 |
6285275 | Chen et al. | Sep 2001 | B1 |
6297722 | Yeh | Oct 2001 | B1 |
6429533 | Li et al. | Aug 2002 | B1 |
6431456 | Nishizawa et al. | Aug 2002 | B1 |
6498715 | Lee et al. | Dec 2002 | B1 |
6556123 | Iwao et al. | Apr 2003 | B1 |
6573567 | Nishizawa et al. | Jun 2003 | B1 |
6587008 | Hatanaka et al. | Jul 2003 | B1 |
6657532 | Shrier et al. | Dec 2003 | B1 |
6667546 | Huang et al. | Dec 2003 | B1 |
6693508 | Whitney et al. | Feb 2004 | B1 |
6849954 | Lee | Feb 2005 | B1 |
20010000658 | Barrett et al. | May 2001 | A1 |
20020050912 | Shrier et al. | May 2002 | A1 |
20020072147 | Sayanagi et al. | Jun 2002 | A1 |
20020139578 | Alcoe et al. | Oct 2002 | A1 |
20030038345 | Lee | Feb 2003 | A1 |
20030123205 | Ashiya | Jul 2003 | A1 |
20040041277 | Kimura et al. | Mar 2004 | A1 |
Number | Date | Country |
---|---|---|
9-260106 | Oct 1997 | JP |
377504 | Dec 1988 | RO |
Number | Date | Country | |
---|---|---|---|
20040000725 A1 | Jan 2004 | US |