Patent Application
20140291818
1. Field
Embodiments described herein generally relate to integrated circuit (IC) device packaging technology.
2. Background Art
Conventional array-type packages have the drawbacks of (1) poor thermal performance, (2) no EMI protections, (3) thick top mold and overall package profile height, (4) small ratio of die-to-package size since the mold cap must be clamped to the package substrate for molding, and (5) large package body size. Both the resin substrate and the plastic molding compound materials have low thermal conductivity values (around 0.19˜0.3 W/m·° C. for BT or FR4 type substrate and 0.2˜0.9 W/m·° C. for the molding compound). Since the die is surrounded entirely by materials with poor heat conduction properties, the heat generated on the IC die is trapped within the PBGA package. The temperature of the IC die has to rise to very high values above the environment temperature in order to release the trapped heat to the environment.
Both the resin substrate and the plastic molding compound materials are transparent to electromagnetic radiation. Consequently, electromagnetic radiation generated from the IC die will escape from the package and enter the electronic system and interfere with other electronic components. The IC die is also unprotected from electromagnetic radiation emitted from other components inside as well as outside the electronic system.
In conventional stacked packages, the package-to-package interconnection is facilitated by mounting a top package to the substrate of the bottom package. The bottom package can have exposed land pads on the substrate top surface Which provide contact with the solder balls on the top package. The exposed solder ball land pads are located along the periphery of the substrate top and surround the package molding compound. The top package can be attached to the bottom package using conventional reflow surface mount processes. Because the solder ball land pads on the bottom package substrate top must be exposed for stacking the top package, the IC die of the bottom package must be encapsulated with a mold cavity (mold cap) to define the extent of the mold and prevent the mold compound from covering or contaminating the ball pads. Consequently, the die size in the bottom package cannot be too large in order for both the die and bond wires to fit into the mold.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the disclosed subject matter and, together with the description, further serve to explain the principles of the contemplated embodiments and to enable a person skilled in the pertinent art to make and use the contemplated embodiments.
The disclosed subject matter will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the disclosure. References in the Detailed Description to “one exemplary embodiment,” “an exemplary embodiment,” “an example exemplary embodiment,” etc., indicate that the exemplary embodiment described can include a particular feature, structure, or characteristic, but every exemplary embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the relevant art(s) to affect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.
The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications can be made to the exemplary embodiments within the spirit and scope of the disclosure. Therefore, the Detailed Description is not meant to limit the disclosure. Rather, the scope of the disclosure is defined only in accordance with the following claims and their equivalents.
The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
Furthermore, it should be understood that spatial descriptions (e.g., “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein may be spatially arranged in any orientation or manner.
Embodiments disclosed herein include an integrated circuit (IC) package. The IC package can include a substrate, one or more IC dies, an interposer, and first and second pluralities of conductive elements. The substrate can have opposing first and second surfaces. For example, the first surface can be the bottom surface of the substrate and the second surface can be top surface of the substrate. The first IC die can be coupled to the first surface of the substrate. The first plurality of conductive elements can also be coupled to the first surface of the substrate. The interposer can have opposing, the first and second surfaces. For example, the first surface can be the top surface of the interposer and the second surface can be the bottom surface of the interposer. The second plurality of conductive elements can be coupled to the first surface of the interposer. Respective ones of the first and second pluralities of conductive elements can be electrically coupled. For example, the first and second pluralities of conductive elements can be joined using a reflow process, in an embodiment, the first IC die can be electrically coupled to the interposer through the first and second pluralities of conductive elements.
One or more devices can be coupled to the second surface of the substrate. For example, the devices can include one or more of a lead frame package, a ball grid array (BGA) package, passive components (e.g., a balun, a capacitor, or an inductor), or an antenna. For example, an IC package including a second IC die can be coupled to the second surface of the substrate. The substrate can electrically interconnect the first and second IC dies to facilitate coma between them. For example, the first IC die can include a processor and the second IC die can include a memory. The processor included in the first IC die can be configured to store data in the memory included in the second IC die.
Moreover, the package can also include an encapsulation material that encapsulates the first IC die and at least a portion of the first plurality of conductive elements. A gap can be present between the outer surface of the encapsulation material and the first surface of the interposer.
The first and second pluralities of conductive elements can include a variety of different types of conductive elements. For example, solder balls, copper posts, and/or copper posts having solder caps can be included in the first and second pluralities of conductive elements.
Furthermore, the interposer, the substrate and specific ones of the first and second pluralities of conductive elements can together form a Faraday cage. The Faraday cage can prevent electromagnetic interference of the first IC the and can prevent radiation emanating from the first IC die from exiting the IC package. For example, the substrate and the interposer can each include a patterned metal layer that can be electrically coupled through the first and second pluralities of conductive elements. A loop can thus be formed around the first IC die. This loop can then be coupled to a ground potential to form a Faraday cage.
As shown in
Conductive regions 112 and 150 are formed on first and second surfaces 102a and 102b of substrate 102, respectively. Conductive regions 112 and/or 150 can be formed by patterning a metal layer. Conductive regions 112 can be configured to be coupled to respective ones of first plurality of conductive elements 106. Conductive regions 150 can be configured to be coupled to conductive elements of packages 160 and 140. In an embodiment, conductive regions 112 and/or conductive regions 150 can include bond pads.
IC die 104 is coupled to first surface 102a of substrate 102 in a flip chip configuration. For example, as shown in
First plurality of conductive elements 106 are coupled to respective ones of conductive regions 112. In the embodiment of
Conductive regions 114 and 118 are formed on first and second surfaces 108a and 108b of interposer 108. Conductive regions 114 can be configured to be coupled to respective ones of second plurality of conductive elements 110. Further, conductive regions 118 can be configured to be coupled to respective ones of third plurality of conductive elements 116. In an embodiment, conductive regions 114 and/or conductive regions 118 can include bond pads.
In the embodiment of
Third plurality of conductive elements 116 can facilitate communication between IC package 100 and a printed circuit board (PCB) (not shown). For example, third plurality of conductive elements 116 can be configured to contact conductive regions on the PCB. These conductive regions can be coupled to elements, e.g., traces, that provide electrical coupling to other devices coupled to the PCB. In the embodiment of
Packages 140 and 160 are coupled to conductive regions 150 of substrate 102. Package 140 is a lead frame package that includes an IC die (not shown) and leads 142. Package 160 is a fan out includes an IC die 162 coupled to second surface 102b of substrate 102 through solder balls 164. In an embodiment, substrate 102 can electrically couple IC die 104 to package 140 and/or package 160. Moreover, substrate 102 can also electrically couple packages 140 and 160. Although the embodiment of
For example, IC die 104 can include a processor and IC die 162 can include a memory. In such an embodiment, IC die 104 can be configured to store data in the memory of IC die 162. Because the signal path between IC die 104 and IC die 162 is relatively short, e.g., as opposed to different devices on a PCB, communications between IC dies 104 and 162 can be enhanced. These enhanced communications may, for example, enable high speed data exchanges between IC dies 104 and 162. Moreover, the relatively short distance also reduces the likelihood that electromagnetic interference will corrupt data exchanges between IC dies 104 and 162.
In a further embodiment, all or substantially all of the devices (e.g., memories, transceivers, antennas, processors, etc.) that constitute an electronics system (e.g., a cellular phone) can be mounted on first surface 102a and/or second surface 102b of substrate 102. In such an embodiment, most or all communications between devices of the system benefit from the shortened signal paths provided by substrate 102. Communications with devices mounted to a PCB can be provided through interposer 108.
Substrate 102 can also be configured to couple IC die 104 to first plurality of conductive elements 106. Through first plurality of conductive elements 106, IC die 104 can be coupled to second plurality of conductive elements 110. Moreover, interposer 108 can be configured to electrically couple second and third pluralities of conductive elements 110 and 116. Thus, IC die 104 can be electrically coupled to third plurality of conductive elements 116, e.g., to allow for communications to a PCB.
Encapsulation material 120 encapsulates IC die 104, solder bumps 105, and a least a portion of first plurality of conductive elements 106. As shown in
Moreover, as shown in
Moreover, as shown in
Moreover, to form a Faraday cage, this loop can be coupled to a ground potential. Faraday cage 1101 can prevent electromagnetic interference from affecting die 104. Faraday cage 1101 can also prevent radiation produced by IC die 104 from escaping package 1100 and affecting other devices.
In step 1402, an IC die is mounted to a first surface of substrate. For example, in
In step 1404, a first plurality of conductive elements is coupled to the first surface of the substrate. For example, in
In step 1406, the first surface of the substrate in the IC die is encapsulated. For example, in
In step 1408, an outer surface of the encapsulation material is ablated. For example, in
In step 1410, a second plurality of conductive elements is coupled to a surface of an interposer. For example, in
In step 1412, each of the first plurality of conductive elements is coupled to a respective one of the second plurality of conductive elements. For example, as shown in
In step 1414, a device is coupled to a second surface of the substrate. The second device can be, e.g., a package including an IC die, an antenna, or a passible component (e.g., a capacitor, resistor, inductor, or balun). For example, as shown in
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
