Patent Grant
11043258
The present invention generally relates to integrated circuit devices, high speed signaling of such devices, memory devices, and memory systems.
Some contemporary trends predict that processors, such as general purpose microprocessors and graphics processors, will continue to increase system memory and data bandwidth requirements. Using parallelism in applications such as multi-core processor architectures and multiple graphics pipelines, processors should be able to drive increases in system bandwidths at rates some predict will be doubled every three years for the next ten years. There are several major trends in dynamic random access memory (“DRAM”) that may make it costly and challenging to keep up with increasing data bandwidth and system memory requirements. For example, transistor speed relative to feature size improvements in a given DRAM technology node, and the rising costs of capital investment required to move DRAM technology to greater memory densities for a given DRAM die adversely affect the rate at which DRAM technology can keep pace with the increasing data bandwidth and system capacity requirements.
Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Systems, among other embodiments, include topologies for transferring data and/or control/address information between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. Other topology types may include forked, star, fly-by, segmented and topologies used in SIP or MCP embodiments.
An integrated circuit buffer device enables configurable effective memory organization of a plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. For example, control/address information may be provided to the buffer device from a memory controller that expects a memory organization having a predetermined number of memory devices and memory banks as well as page size and peak bandwidth, but the actual memory organization coupled to the buffer device is different. The buffer device segments and/or merges the data transferred between the memory controller that expects a particular memory organization and the actual memory organization. The integrated circuit buffer device may merge read data from separate memory devices into a stream of read data. Likewise, the integrated circuit memory device may segment a write data into write data portions that are stored on a plurality of memory devices.
An integrated circuit buffer device may include data path, address translation, data path router, command decode and control (or register set) circuits. The buffer device also includes an interface that may be configured into at least three different segmentation modes: 1) Four 4-bit interfaces (4×4), 2) Two 4-bit interfaces (2×4) or 3) Two 8-bit interfaces (2×8). The different configurations allow flexibility in memory module or memory stack configurations. The buffer device may also include a pattern generator and internal memory array circuit to emulate storing and retrieving data from the plurality of integrated circuit memory devices.
The buffer device may increase memory system performance by; for example, eliminating a “time bubble” or idle time for a signal path (bus) turnaround between memory transactions to different ranks of integrated circuit memory devices coupled to segmented data signal paths. A memory rank may also include a single integrated circuit memory device. Eliminating the need for the memory controller to track memory rank access and inserting time bubbles may reduce memory controller complexity. Memory modules or memory rank capacity may be expanded using segmented data signal paths without decreasing bandwidth caused by bubble time insertion. Memory modules may include more memory devices or dies while still emulating a single rank memory module.
According to embodiments, a system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via an integrated circuit buffer device) on a first signal path to the master and a second memory module simultaneously provides read data from its plurality of integrated circuit memory devices (via another integrated circuit buffer device on the second module) on a third signal path coupled to the master device. In a second mode of operation, the first memory module provides first read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on the first signal path and second read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on a second signal path that is coupled to a second memory module. An integrated circuit buffer device in the second memory module then bypasses the second read data from the second signal path and provides the second read data on a third signal path coupled to the master device. The first memory module may have a larger address space or capacity, such as twice as large, as compared to the second memory module.
Similarly, write data may be provided from the master device to the first and second memory modules during the first and second modes of operation.
According to embodiments, the second memory module includes a bypass circuit (such as in the integrated circuit buffer device, interface or in continuity memory module) to transfer the second read data from the second signal path to the third signal path. The bypass circuit may include a jumper, signal trace and/or semiconductor device. The bypass circuit may also include delay circuits for adding delay in outputting the read data (or levelizing) from a memory module.
According to embodiments, a system includes a master device and at least four memory modules wherein at least two memory modules have different capacities than the other two memory modules. The four memory modules are coupled to a plurality of signal paths. The system may operate in a bypass mode in which one or more memory modules use a bypass circuit to provide read data from at least one larger capacity memory module to a master device.
According to embodiments, a system includes a master and a plurality of memory modules that may be disposed in a variety of topologies, such as point-to-point or daisy chain topologies. Memory modules may include a plurality of integrated circuit buffer devices that are coupled using a variety of topologies to receive control information, such as dedicated, fly-by, stub, serpentine or tree topologies, singly or in combination.
According to embodiments, a method determines a mode of operation of a system including a master and a plurality of memory modules. In a bypass mode of operation, delays are provided to read data from at least one memory module to levelize or ensure that read data from different capacity memory modules using different signal paths arrive at the master at approximately the same time.
According to embodiments, a memory module includes a plurality of signal paths that provide data to a memory module connector from a plurality of respective integrated circuit buffer devices (or dies) that access the data from an associated plurality of integrated circuit memory devices (or dies). In a specific embodiment, each integrated circuit buffer device is also coupled to a bussed signal path that provides control and/or address information that specifies an access to at least one integrated circuit memory device associated with the respective integrated circuit buffer device.
According to embodiments, a memory module connector includes a control/address interface portion and a data interface portion. A control/address bus couples a plurality of integrated circuit buffer devices to the control/address interface portion. A plurality of data signal paths couple the plurality of respective integrated circuit buffer devices to the data interface portion. Each integrated circuit buffer device includes 1) an interface to couple to at least one integrated circuit memory device, 2) an interface to couple to the control/address bus and 3) an interface to couple to a data signal path in the plurality of data signal paths.
According to embodiments, a memory module may include a non-volatile memory location, for example using an electrically erasable programmable read only memory (“EEPROM”) (also known as a Serial Presence Detect (“SPD”) device), to store information regarding parameters and configuration of the memory module. In embodiments, at least one integrated circuit buffer device accesses information stored in the SPD device.
In a package embodiment, a package houses an integrated circuit buffer die and the plurality of integrated circuit memory dies. In the package, a plurality of signal paths transfer data (read and/or write data) between the integrated circuit buffer die and the plurality of integrated circuit memory dies. The integrated circuit buffer die provides control signals from an interface of the package to the plurality of integrated circuit memory dies. Data stored in memory arrays of the plurality of integrated circuit memory dies is provided to a signal path disposed on the memory module via the integrated circuit buffer die in response to the control signals. In an embodiment, the package may be a multichip package (“MCP”). In an embodiment, the plurality of integrated circuit memory dies may be housed in common or separate packages. In an embodiment described below, the memory module may include a series of integrated circuit dies (i.e., memory die and buffer die) stacked on top of one another and coupled via a signal path.
As described herein, an integrated circuit buffer device is also referred to as a buffer or buffer device. Likewise, an integrated circuit memory device is also referred to as a memory device. A master device is also referred to as a master.
In an embodiment, an integrated circuit memory device is distinguished from a memory die in that a memory die is a monolithic integrated circuit formed from semiconductor materials for storing and/or retrieving data or other memory functions, whereas an integrated circuit memory device is a memory die having at least some form of packaging or interface that allows the memory die to be accessed.
Likewise in an embodiment, an integrated circuit buffer device is distinguished from a buffer die in that a buffer die is a monolithic integrated circuit formed from semiconductor materials and performs at least one or more buffer functions described herein, whereas an integrated circuit buffer device is a buffer die having at least some form of packaging or interface that allows communication with the buffer die.
In the embodiments described in more detail below,
In an embodiment, a data slice is a portion of the memory module data signal path (or bus) that is coupled to the respective integrated circuit buffer device. The data slice may include the full data path or portions of data paths to and from a single memory device disposed on the memory module.
Integrated circuit memory devices may be considered as a common class of integrated circuit devices that have a plurality of storage cells, collectively referred to as a memory array. A memory device stores data (which may be retrieved) associated with a particular address provided, for example, as part of a write or read command. Examples of types of memory devices include dynamic random access memory (“DRAM”), including single and double data rate synchronous DRAM, static random access memory (“SRAM”), and flash memory. A memory device typically includes request or command decode and array access logic that, among other functions, decodes request and address information, and controls memory transfers between a memory array and signal path. A memory device may include a transmitter circuit to output data, for example, synchronously with respect to rising and falling edges of a clock signal, (e.g., in a double data rate type of memory device). Similarly, the memory device may include a receiver circuit to receive data, for example, synchronously with respect to rising and falling edges of a clock signal or outputs data with a temporal relationship to a clock signal in an embodiment. A receiver circuit also may be included to receive control information synchronously with respect to rising and falling edges of a clock signal. In an embodiment, strobe signals may accompany the data propagating to or from a memory device and that data may be captured by a device (e.g., memory device or buffer, or controller) using the strobe signal.
In an embodiment, an integrated circuit buffer device is an integrated circuit that acts as an interface between a memory module connector interface and at least one integrated circuit memory device. In embodiments, the buffer device may store and/or route data, control information, address information and/or a clock signal to at least one integrated circuit memory device that may be housed in a common or separate package. In an embodiment, the buffer isolates, routes and/or translates data, control information and a clock signal, singly or in combination, between a plurality of memory devices and a memory module connector interface. An embodiment of a memory module connector interface is described below and shown in
At least one signal path 121, as shown in
In an embodiment, clock signals and/or clock information may be transferred on at least one signal line in signal path 121. These clock signal(s) provide one or more clock signals having a known frequency and/or phase. In an embodiment, a clock signal is synchronized with or travels along side the control/address information. In an embodiment, an edge of the clock signal has a temporal relationship with an edge of a control/address signal representing the control/address information. In an embodiment, a clock signal is generated by a clock source, master device (e.g., controller device) and/or buffer device.
In an embodiment, a clock signal and/or clock information may be transferred on at least one signal line in respective signal paths 120a-d. Buffer devices 100a-d may receive and/or transmit a clock signal with data on signal paths 120a-b. In an embodiment, write data is provided to buffer devices 100a-d on signal paths 120a-d and a clock signal is provided on signal paths 120a-d along side write data. In an embodiment, a clock signal (such as a clock-to-master (“CTM”)) is provided from buffer devices 100a-d on signal paths 120a-d along side read data on signal paths 120a-d. In an embodiment, a clock signal is synchronized with or travels along side the write and/or read data. An edge of the clock signal has a temporal relationship or is aligned with an edge of a data signal representing write and/or read data. Clock information can be embedded in data, eliminating the use of separate clock signals along with the data signals.
In an embodiment, a read, write and/or bidirectional strobe signal may be transferred on at least one signal line in respective signal paths 120a-d. Buffer devices 100a-d may receive and/or transmit a strobe signal with data on signal paths 120a-b. In an embodiment, write data is provided to buffer devices 100a-d on signal paths 120a-d and a strobe signal is provided on signal paths 120a-d along side write data. In an embodiment, a strobe signal is provided from buffer devices 100a-d on signal paths 120a-d along side read data on signal paths 120a-d. In an embodiment, a strobe signal is synchronized with or travels along side the write and/or read data. An edge of the strobe signal has a temporal relationship or is aligned with an edge of a data signal representing write and/or read data.
In an embodiment, addresses (for example, row and/or column addresses) for accessing particular memory locations in a particular integrated circuit memory device and/or commands are provided on signal path 121 from a memory module connector interface. In an embodiment, a command relates to a memory operation of a particular integrated circuit memory device. For example, a command may include a write command to store write data at a particular memory location in a particular integrated circuit memory device and/or a read command for retrieving read data stored at a particular memory location from a particular integrated circuit memory device. Also, multiple memory devices in different data slices can be accessed simultaneously. In embodiments, a command may include row commands, column commands such as read or write, mask information, precharge and/or sense command. In an embodiment, control information is transferred on signal path 121 over a common set of lines in the form of a time multiplexed packet where particular fields in the packet are used for including command operation codes and/or addresses. Likewise, packets of read data may be transferred from integrated circuit memory devices via buffers 100a-d on respective signal paths 120a-d to a memory module connector interface. In an embodiment, a packet represents one or more signals asserted at particular bit windows (or a time interval) for asserting a signal on particular signal lines.
In an embodiment, chip select information may be transferred on one or more signal lines in signal path 121. In an embodiment, chip select information may be one or more chip select signals on respective signal lines having predetermined voltage values or states (or logic values) that select and enable operation of a “chip” or integrated circuit memory device/buffer device.
In embodiments, memory module 100 communicates (via a memory module connector interface) with a master device (e.g., a processor or controller).
Referring to
Referring to
In an embodiment, memory module 900 includes pairs of memory devices 101a-b and buffer devices 100a-d disposed on a first side of substrate 910. In alternate embodiments, more or less memory devices and buffer devices are used. In an embodiment, pairs of memory devices 101c-d are also disposed on a second side of memory module 900 as shown in a side and bottom view of memory module 900 in
Memory module 900 includes connector interface 920 that has different interface portions for transferring data and control/address/clock signals. For example, a first side of memory module 900 includes connector interface portions 920a-d used to transfer data signals and a connector interface portion 930a used to transfer control/address signals. In an embodiment, connector interface portion 930a also transfers a clock signal and/or clock information. In an embodiment, a second side of memory module 900 including connector interface portions 920e-h are used to transfer data signals and a connector interface portion 930b is used to transfer control/address signals. In an embodiment, connector interface portion 930b also transfers a clock signal and/or clock information.
In an embodiment, connector interface 920 is disposed on an edge of substrate 910. In an embodiment, a memory module 900 is inserted into a socket 940 disposed on substrate 950. In an embodiment, substrate 950 is a main board or PCB with signal paths 960a-b for transferring signals on substrate 950. In an embodiment, signal paths 960a and 960b are signal traces or wires. In an embodiment, signal paths 960a and 960b are coupled to other sockets disposed on substrate 950 that may have another memory module inserted and/or coupled to a master.
In an embodiment, connector interface portions include at least one contact or conducting element, such as a metal surface, for inputting and/or outputting an electrical signal. In alternate embodiments, a contact may be in the form of any one of or a combination of a ball, socket, surface, signal trace, wire, a positively or negatively doped semiconductor region and/or pin, singly or in combination. In an embodiment, a connector interface as described herein, such as connector interface 920, is not limited to physically separable interfaces where a male connector or interface engages a female connector (or socket 940) or interface. A connector interface also includes any type of physical interface or connection, such as an interface used in a system-in-a-package (“SIP”) where leads, solder balls or connections from a memory module are soldered to a circuit board.
In an alternate embodiment, memory module 900 is included in an embedded memory subsystem, such as one in a computer graphics card, video game console or a printer. In an alternate embodiment, memory module 900 is situated in a personal computer or server.
In an embodiment, a master communicates with memory modules illustrated in
In an embodiment, a master, memory modules and signal paths are in one or more integrated monolithic circuits disposed in a common package or separate packages.
In an embodiment, buffer 100a communicates with a serial presence detect (“SPD”) device to store and retrieve parameters and configuration information regarding device 1000 and/or memory module 900. In an embodiment, an SPD 1002 is a non-volatile storage device. Signal path 1004 couples SPD 1002 to buffer 100a. In an embodiment, signal path 1004 is an internal signal path for providing bidirectional signals between SPD 1002 and buffer 100a.
In an embodiment, SPD 1002 is an EEPROM device. However, other types of SPD 1002 are possible, including but not limited to a manual jumper or switch settings, such as pull-up or pull-down resistor networks tied to a particular logic level (high or low), which may change state when a memory module is added or removed from a system.
In an embodiment, SPD 1002 is a memory device that includes registers that stores configuration information that can be easily changed via software during system operation, allowing a high degree of flexibility, and making configuration operations that are transparent to an end user.
In an embodiment illustrated in
In an embodiment illustrated by
In an embodiment, SPD configuration information includes timing information or parameters for accessing memory devices, such as a time to access a row or the memory device, a time to access a column of the memory device, a time between a row access and a column access, a time between a row access and a precharge operation, a time between a row sense applied to a first bank of a memory array and a row sense applied to a second bank of the memory array and/or a time between a precharge operation applied to a first bank in a memory array and a precharge operation applied to a second bank of the memory array.
In an embodiment, the stored timing information may be expressed in terms of time units where a table of values maps specific time units to specific binary codes. During an initialization or calibration sequence, a master or a buffer may read SPD configuration information and determine the proper timing information for one or more memory devices. For example, a master may also read information representing the clock frequency of a clock signal from an SPD 1002, and divide the retrieved timing information by a clock period of a clock signal. (The clock period of the clock signal is the reciprocal of the clock frequency of the clock signal). Any remainder resulting from this division may be rounded up to the next whole number of clock cycles of the clock signal.
Signal paths 120a and 121, as shown in
In an embodiment, device 1000 has two separate power sources. Power source V1 supplies power to one or more memory devices (memory devices 101a-d) on memory module 900. Power source V2 supplies power to one or more buffers (buffer 100a) on memory module 900. In an embodiment, the buffer 100a has internal power regulation circuits to supply power to the memory devices 101a-d.
In a memory read operation embodiment, buffer 100a receives control information (including address information) that may be in a packet format from a master on signal path 121 and in response, transmits corresponding signals to one or more, or all of memory devices 101a-d on one or more signal paths 1005. One or more of memory devices 101a-d may respond by transmitting data to buffer 100a which receives the data via one or more signal paths 1006 and in response, transmits corresponding signals to a master (or other buffer). A master transmits the control information via one or more signal paths 121 and receives the data via one or more signal paths 120a.
By bundling control and address information in packets, protocols required to communicate to memory devices 101a-d are independent of the physical control/address interface implementation.
In a memory write operation embodiment, buffer 100a receives control information (including address information) that may be in a packet format from a master on signal path 121 and receives the write data for one or more memory devices 101a-d that may be in a packet format from a master on signal path 120a. Buffer 100a then transmits corresponding signals to one or more, or all of memory devices 101a-d on one or more signal paths 1006 so that the write data may be stored.
A master transmits the control/address/clock information via one or more signal paths 121 and transmits the write data via one or more signal paths 120a.
In an embodiment, simultaneous write and/or read operations may occur for different memory devices in memory devices 101a-d.
In an embodiment, control information that is provided to buffer 100a causes one or more memory operations (such as write and/or read operations) of one or more memory devices 100a-d, while the same control information may be provided to buffer 100b which causes the same memory operations of one or more memory devices 100a-d associated with buffer 100b. In another embodiment, the same control information may be provided to buffer 100a and buffer 100b, yet different memory operations occur for the one or more memory devices 100a-d associated with each buffer 100a-b.
In an embodiment, buffer interface 1103a couples signal paths 121 and 120a to buffer 100a as shown in
In an embodiment, termination 1880 is disposed on buffer 100a and is connected to transceiver 1875 and signal path 120a. In this embodiment, transceiver 1875 includes an output driver and a receiver. Termination 1880 may dissipate signal energy reflected (i.e., a voltage reflection) from transceiver 1875. Termination 1880, as well as other termination described herein, may be a resistor or capacitor or inductor, singly or a series/parallel combination thereof. In alternate embodiments, termination 1880 may be external to buffer 100a. For example, termination 1880 may be disposed on a substrate 910 of a memory module 900 or on a package used to house buffer 100a.
Interface 1820a includes at least one transmitter circuit 1893 coupled to signal path 1005 to transmit control/address/clock information to one or more memory devices. In an embodiment, interface 1820a includes a transceiver that may transfer control/address/clock information between buffers disposed on a common memory module or different memory modules.
Interface 1820b includes a transceiver 1894 coupled to signal path 1006 to transfer data between buffer 100a and one or more memory devices 101a-d as illustrated in
According to an embodiment, multiplexer 1830 may perform bandwidth-concentrating operations between buffer interface 1103a and interface 1820b as well as route data from an appropriate source (i.e. target a subset of data from memory devices, internal data, cache or write buffer). The concept of bandwidth concentration involves combining the (smaller) bandwidth of each data path coupled to a memory device in a multiple data signal path embodiment to match the (higher) overall bandwidth utilized by buffer interface 1103a. In an embodiment, multiplexing and demultiplexing of throughput between the multiple signal paths that may be coupled to interface 1820b and buffer interface 1103a is used. In an embodiment, buffer 101a utilizes the combined bandwidth of multiple data paths coupled to interface 1820b to match the bandwidth of interface buffer interface 1103a.
In an embodiment, data cache and tags circuit 1860 (or cache 1860) may improve memory access time by providing storage of most frequently referenced data and associated tag addresses with lower access latency characteristics than those of the plurality of memory devices. In an embodiment, cache 1860 includes a write buffer that may improve interfacing efficiency by utilizing available data transport windows over an external signal path to receive write data and address/mask information. Once received, this information is temporarily stored in a write buffer until it is ready to be transferred to at least one memory device over interface 1820b.
Computations circuit 1865 may include a processor or controller unit, a compression/decompression engine, etc., to further enhance the performance and/or functionality of buffer 100a. In an embodiment, computations circuit 1865 controls the transfer of control/address/clock information and data between buffer interface 1103a and interfaces 1820a-c.
Clock circuit 1870 may include a clock generator circuit (e.g., Direct Rambus® Clock Generator), which may be incorporated onto buffer 101a and thus may eliminate the need for a separate clock generating device.
In an alternate embodiment, clock circuit 1870 include clock alignment circuits for phase or delay adjusting an internal clock signal with respect to an external clock signal, such as a phase lock loop (“PLL”) circuit or delay lock loop (“DLL”) circuit. Clock alignment circuits may utilize an external clock from an existing clock generator, or an internal clock generator to provide an internal clock, to generate internal synchronizing clock signals having a predetermined temporal relationship with received and transmitted data and/or control information.
In an embodiment, clock circuit 1870 receives a first clock signal having a first frequency via signal path 121 and generates a second clock signal (via interface 1820a) to memory device 101a using the first clock signal and also generates a third clock signal (via interface 1820a) to memory device 101b using the first clock signal. In an embodiment, the second and third clock signals have a predetermined temporal (phase or delay) relationship with the first clock signal.
In an embodiment, a transmit circuit (such as in transceivers 1875, 1896 and 1894 shown in
In an embodiment, a transceiver 1875 transmits and receives a first type of signal (for example, a signal having specified voltage levels and timing), while transceivers 1894 (and/or transmit circuit 1893) transmits and receives a second different type of signal. For example, transceiver 1875 may transmit and receive signals for a DDR2 memory device and transceivers 1894 may transmit and receive signals for a DDR3 memory device.
In an embodiment, the control information and/or data that is provided to buffer 100a (by way of signal paths 121 and 120) may be in a different protocol format or have different protocol features than the control information and/or data provided to one or more memory devices 100a-d from buffer 100a. Logic (for example computation circuit 1865) in buffer 100a performs this protocol translation between the control information and/or data received and transmitted. A combination of the different electrical/signaling and control/data protocol constitute an interface standard in an embodiment. Buffer 100a can function as a translator between different interface standards—one for the memory module interface (for example connector interface 920) and another for one or more memory devices 100a-d. For example, one memory module interface standard may require reading a particular register in a particular memory device disposed on the memory module. Yet, a memory module may be populated with memory devices that do not include the register required by the memory module interface standard. In an embodiment, buffer 100a may emulate the register required by the memory module interface standard and thus allow for the use of memory devices 100a-d that operate under a different interface standard. This buffer functionality, combined with the module topology and architecture, enables a memory module to be socket compatible with one interface standard, while using memory devices with a different interface standard.
In an embodiment, buffer 100a includes a redundancy and repair circuit 1883 to test and repair the functionality of memory cells, rows or banks of a memory device, entire memory devices (or periphery circuits) and/or signal paths between buffer 100a and memory devices 101a-d. In an embodiment, redundancy and repair circuit 1883 periodically, during a calibration operation and/or during initialization, tests one or more of memory devices 101a-d by writing a predetermined plurality of values to a storage location in a selected memory device (for example, using transceiver 1894 and a look-up table storing the predetermined values) using a selected data path and then reading back the stored predetermined plurality of values from the selected memory device using the selected data path. In an embodiment, when the values read from the storage location of the selected memory device do not match the values written to the storage location, redundancy and repair circuit 1883 eliminates access by buffer 100a to the selected memory device and/or selected signal path. In an embodiment, a different signal path to a different memory device may be selected and this testing function may be performed again. If selecting the different signal path results in an accurate comparison of read predetermined values to the predetermined values in redundancy and repair circuit 1883 (or a pass of the test), the different memory address to a different memory location, within or to another memory device, is selected or mapped thereafter. Accordingly, future write and/or read operations to the defective memory location will not occur.
In an embodiment, any multiplexed combination of control information (including address information) and data intended for memory devices 101a-d coupled with buffer 100a is received via buffer interface 1103a, which may, for example extract the address and control information from the data. For example, control information and address information may be decoded and separated from multiplexed data on signal path 120a and provided on signal path 1895 to request and address logic circuit 1840 from buffer interface 1103a. The data may then be provided to configurable serialization/deserialization circuit 1891. Request and address logic circuit 1840 generates one or more control signals to transmitter circuit 1893.
Interfaces 1820a and 1820b include programmable features in embodiments. A number of control signal lines and/or data signal lines between buffer 100a and memory devices 101a-d are programmable in order to accommodate different numbers of memory devices. Thus, more dedicated control signal lines are available with an increased number of memory devices. Using programmable dedicated control lines and/or data lines avoids any possible load issues that may occur when using a bus to transfer control signals between memory devices and a buffer 100a. In another embodiment, additional data strobe signals for each byte of each memory device may be programmed at interface 1820b to accommodate different types of memory devices, such as legacy memory devices that require such a signal. In still a further embodiment, interfaces 1820a and 1820b are programmable to access different memory device widths. For example, interfaces 1820a and 1820b may be programmed to connect to 16 “×4” width memory devices, 8 “×8” width memory devices or 4 “×16” width memory devices. Likewise, buffer interface 1103a has a programmable width for signal path 120a.
Configurable serialization/deserialization circuit 1891 performs serialization and deserialization functions depending upon a stored serialization ratio. As a memory device access width is reduced from its maximum value, memory device access granularity (measured in quanta of data) is commensurately reduced, and an access interleaving or multiplexing scheme may be employed to ensure that all storage locations within memory devices 101a-d can be accessed. The number of signal paths 1006 may be increased or decreased as the memory device access width changes. Signal path 1006 may be subdivided into several addressable subsets. The address of the transaction will determine which target subset of signal path 1006 will be utilized for the data transfer portion of the transaction. In addition, the number of transceiver, transmitter and/or receiver circuits included in interfaces 1820a and 1820b that are employed to communicate with one or more memory devices 101a-d may be configured based on the desired serialization ratio. Typically, configuration of the transceivers may be effectuated by enabling or disabling how many transceivers are active in a given transfer between one or more memory devices 101a-d and buffer interface 1103a. In an embodiment, a data rate of transferring data at buffer interface 1103a is a multiple or ratio of a data rate of transferring data on one or more signal paths 1006 coupled to memory devices 101a-d.
Buffer 100a provides a high degree of system flexibility. New interface standards of memory devices may be phased in to operate with a master or a memory system that supports older interface standards by modifying buffer 100a. In an embodiment, a memory module may be inserted using an older memory module interface or socket, while newer generation memory devices may be disposed on the memory module. Backward compatibility with existing generations of memory devices may be preserved. Similarly, new generations of masters, or controllers, may be phased in which exploit features of new generations of memory devices while retaining backward compatibility with existing generations of memory devices. Similarly, different types of memory devices that have different costs, power requirements and access times may be included in a single common package for specific applications.
Memory interface 1900a includes at least one transmitter and/or receiver for transferring signals between memory device 1900 and signal paths 1950a-b, 1951a-b, 1952 and 1953. Write demultiplexer (“demux”) 1920 and read multiplexer (“mux”) 1922 are coupled to signal path 1950a, while write demux 1921 and read mux 1923 are coupled to signal path 1950b. Write demux 1920-21 provide write data from signal paths 1950a-b to memory core 1900b (in particular sense amplifiers 0-2a and 0-2b). Read mux 1922-23 provide read data from memory core 1900b to signal paths 1950a-b (in particular sense amplifiers Na and Nb).
Demux and row packet decoder 1910 is coupled to signal path 1951a and Demux and column packet decoder 1913 is coupled to signal path 1951b. Demux and row packet decoder 1910 decodes a packet and provides a row address to row decoder 1914. Demux and Column packet decoder 1913 provides a column address and mask information to column and mask decoder 1915.
Control registers 1911 are coupled to signal path 1952 and provide control signals to row decoder 1914 and column and mask decoder 1915 in response to register values.
A clock circuit is coupled to signal path 1953 to provide a transmit clock signal TCLK and a receive clock signal RCLK in response to one or more clock signals transferred on signal path 1953. In an embodiment, write demux 1920 and 1921 provide write data from signal paths 1950a-b to memory core 1900b in response to an edge of receive clock signal RCLK. In an embodiment, read mux 1922 and 1923 provide read data from memory core 1900b to signal paths 1950a-b in response to an edge of a transmit clock signal TCLK. In an embodiment, the clock circuit generates a clock signal on signal path 1953 (to a buffer device) that has a temporal relationship with read data that are output on signal paths 1950a-b.
Row decoder 1914 and column and mask decoder 1915 provide control signals to memory core 1900b. For example, data stored in a plurality of storage cells in a memory bank is sensed using sense amplifiers in response to a row command. A row to be sensed is identified by a row address provided to row decoder 1914 from demux and row packet decoder 1910. A subset of the data sensed by a sense amplifier is selected in response to a column address (and possible mask information) provided by demux and column packet decoder 1913.
A memory bank in memory banks 0-N of memory core 1900b includes a memory array having a two dimensional array of storage cells. In embodiments, memory banks 0-N include storage cells that may be DRAM cells, SRAM cells, FLASH cells, ferroelectric RAM (“FRAM”) cells, magnetoresistive or magnetic RAM (“MRAM”) cells, or other equivalent types of memory storage cells. In an embodiment, integrated circuit memory device 1900 is a DDR integrated circuit memory device or later generation memory device (e.g., DDR2 or DDR3). In an alternate embodiment, integrated circuit memory device 1900 is an XDR™ DRAM integrated circuit memory device or Direct Rambus® DRAM (“DRDRAM”) memory device. In an embodiment, integrated circuit memory device 1900 includes different types of memory devices having different types of storage cells housed in a common package.
In an embodiment, the number of transceiver points along a signal line may distinguish between a point-to-point link and a bus. For example, a point-to-point link generally includes only two transceiver connection points while a bus generally includes more than two transceiver points. In some instances a point to point link can be mixed with bussed signal lines, where the bussed single lines may be used to provide sideband functionality such as maintenance, initialization or test.
Several embodiments of point-to-point links include a plurality of link topologies, signaling, clocking and signal path types. Embodiments having different link architectures include simultaneous bi-directional links, time-multiplexed bi-directional links and multiple unidirectional links. Voltage or current mode signaling may be employed in any of these link topologies.
In an embodiment, a clock signal or clock information is provided on signal paths 2122 and 2123, on a separate signal path from a clock source or master 2101, or along the data signal paths 2121a-b.
Signal path 2311 is terminated by termination 2350a and signal path 2310 is terminated by termination 2350b. In an embodiment, the impedance of termination 2350a matches the impedance of a portion of the signal path 2311 (multi-drop bus 2320a) on memory module 2310a, (Z0) and the impedance of termination 2350b approximately matches the impedance of a portion of the signal path 2310 (multi-drip bus 2320b) on memory module 2301b (Z1). In an embodiment, impedance Z0 approximately equals impedance Z1. In embodiments, terminations 2350a and 2350b, singly or in combination, are disposed on memory module, buffer devices or packages used to house buffer devices.
In embodiments, termination may be disposed on buffers 101a-d, memory modules 2401a-b and/or elsewhere in a system, such as on a PCB.
In a first mode of operation (or a non-bypass mode) illustrated in
In a second mode of operation (or a bypass mode) illustrated in
Write data from master 2101 may be provided to memory modules 2601 and 2602 similar to how read data is obtained during a first and second mode of operation.
In embodiments, modes of operation are determined in response to a control signal from master 2101, or other circuit or in response to reading configuration information stored in a separate storage circuit in a device, such as an SPD device or register on the buffer or controller device, disposed on system 2600. Modes of operation may be determined at initialization, periodically or during calibration of system 2600.
In embodiments, bypass circuits 2630a-b (as well as bypass circuits 2630c-d shown in
Master 2101 is coupled to memory module 2701 by signal path 2710. Signal path 2711 couples memory module 2701 to memory module 2704. In an embodiment, bypass circuit 2630a allows read and write data to be transferred between signal paths 2711 and 2710 either to or from master device 2101 in response to control/address information provided to memory module 2704.
Master 2101 is coupled to memory module 2702 by signal path 2712. Signal path 2713 couples memory module 2702 to memory module 2703. Signal path 2714 couples memory module 2703 to memory module 2704. In an embodiment, bypass circuits 2630b and 2630c allow read and write data to be transferred between signal paths 2712 and 2713, as well as signal paths 2713 and 2714, either to or from master device 2101 in response to control/address information provided to memory modules 2702-04.
Master 2101 is coupled to memory module 2703 by signal path 2714. Signal path 2716 couples memory module 2703 to memory module 2704. In an embodiment, bypass circuit 2630c allows read and write data to be transferred between signal paths 2714 and 2716 either to or from master device 2101 in response to control/address information provided to memory modules 2703-04.
Master 2101 is coupled to memory module 2704 by signal path 2717. In an embodiment, read and write data is transferred on signal path 2717 to or from master device 2101 in response to control/address information provided to memory module 2704.
In a first mode of operation (non-bypass mode) as illustrated by
Table 2820 illustrates how different sized memory modules may be disposed in respective interfaces 2701a-d during a second mode of operation (bypass mode). For example, interfaces 2701c-d may be coupled to “small” sized memory modules and interfaces 2701a-b include bypass circuits 2802 and 2801 as indicated by the first row of Table 2820. Alternatively, interface 2701c may be coupled to a “large” sized memory module; and interface 2701d may be coupled to a “small” sized memory module. Interfaces 2701a-b include bypass circuits 2802 and 2801, as indicated by Table 2820.
In a second mode of operation (bypass mode) as illustrated by
In embodiments, bypass circuits 2801 and/or 2802 are disposed in a continuity module, integrated circuit buffer device, interface (for example a socket) and/or memory module. In an embodiment, bypass circuits 2801 and 2802 are conductive elements, such as metal traces or wires that may be disposed manually on an interface or memory module. In an embodiment, bypass circuits 2801 and 2802 correspond to bypass circuit 2900 shown in
Receiver circuits 2901a-d receive write data signals from signal paths DQ[0:3] and provide write data to data width translator circuit 2950 and/or back out to a signal path by way of transmitters 2902a-d and bypass elements 2905-2910. Receiver circuit 2901e receives write address signals from signal path RQ and provides write addresses to data width translator circuit 2950. Receiver circuit 2901a is coupled to bypass elements 2906 and 2908 to reroute received data signals to transmitter circuits 2902b and 2902c in response to control signals (not shown) provided to bypass elements 2906 and 2908. Receiver circuit 2901b is coupled to bypass elements 2905 and 2910 to reroute received data signals to transmitter circuits 2902a and 2902d in response to control signals (not shown) provided to bypass elements 2905 and 2910. Receiver circuit 2901c is coupled to bypass element 2907 to reroute received data signals to transmitter circuit 2902a in response to control signals (not shown) provided to bypass element 2907. Receiver circuit 2901d is coupled to bypass element 2909 to reroute received data signals to transmitter circuit 2902b in response to control signals (not shown) provided to bypass element 2909.
As can be seen, write data may be rerouted from a single signal path DQ0 to another single signal path DQ1. Write data may be also rerouted from two signal paths DQ0 and DQ1 to signal paths DQ2 and DQ3.
In an embodiment, bypass elements 2905-2910 function independently as respective switches to allow a signal (represented by a voltage level) to be passed from a receiver circuit to a transmitter circuit. In an embodiment, bypass elements 2905-2910 are semiconductors such as negative and/or positive-channel metal-oxide (NMOS/PMOS) semiconductors with a control signal (such as a voltage) provided to a gate of the semiconductor while a source and/or a drain is coupled to a transmitter and/or receiver circuit. In an alternate embodiment, other types of semiconductors or switches may be used. In an embodiment, control signals (not shown) provided to bypass elements 2905-2910 are provided by master 2101 or from a programmable register, such as an SPD device. In an embodiment, control signals are provided by a master after reading memory capacity information of memory modules stored in one or more SPD devices. In an embodiment, control signals provided to bypass elements may be provided in response to a manual jumper, programmable fuse or register. In an embodiment, control signals provided to bypass elements may be provided by one or more integrated circuit buffer devices in response to one or more integrated circuit buffer devices reading a received address/control information. For example, when an address is received that identifies a memory location that is not provided on a particular memory module (non-overlapping address space or smaller capacity memory module), control signals are provided to bypass elements from the integrated circuit buffer device that received the address/control information (in a bypass mode) to enable data to be rerouted from the larger capacity memory module to another destination, such as a master.
In an embodiment, bypass elements 2905-2910 may be disposed before or left of receiver and transmitter circuits 2901a-d and 2902a-d as well as in or after (right of) data width translator circuit 2950 (for example, after a clock barrier or boundary). Bypass elements 2905-2910 may be disposed in a master, an interface (such as a socket) and/or a memory module (outside of a buffer device). Bypass elements 2905-2910 may also be disposed internal to an integrated circuit buffer, as opposed to an interface of an integrated circuit buffer device, or in an integrated circuit memory device.
In an embodiment, rerouted write data may be resynchronized by a transmitter circuit using a different or the same clock signal that is used by the receiver circuit in receiving the read data. Also, write data that has been rerouted by bypass elements may be transmitted in a fast analog mode.
Stored read data from integrated circuit memory devices disposed on a memory module are provided on signal paths DQ_DRV[0:3] by way of an integrated circuit buffer device. Read data is levelized or delays are provided to the read data by a selector circuit, such as multiplexers (mux) 2903a-d, and delay circuits 2904a-d in response to DELAY[0:3] control signals. Signal paths DQ_DRV[0:3] are input to delay circuits 2904a-d and a first input (“0 input”) of mux 2903a-d, while an output of delay circuits 2904a-d is provided to a second input (“1 input”) of mux 2903a-d. DELAY[0:3] control signals select an output of mux 2903a-d or whether a delay is introduced into read data on signal paths DQ_DRV[0:3]. In an embodiment, delay circuits 2904a-d may introduce a programmable delay in response to a control signal (not shown). Control signals provided to delay circuits 2904a-d as well as DELAY[0:3] control signals may be provided similar to control signals provided to bypass elements 2905-2910 as described above.
In an embodiment, delay circuits 2904a-d are inverters, registers and/or a series of inverters and/or registers that may introduce programmable delay to a read signal on signal paths DQ_DRV[0:3]. The amount of delay provided to read data by delay circuits 2904a-d may be longer than the amount of time for providing read data to delay circuits 2904a-d, or longer than a data cycle time.
In an embodiment, multiplexers 2903a-d and delay circuits 2904a-d may be disposed before or left of receiver and transmitter circuits 2901a-d and 2902a-d. For example, multiplexers 2903a-d and delay circuits 2904a-d may be disposed in a master, interface (such as a socket) and/or memory module. In an embodiment, multiplexers 2903a-d and delay circuits 2904a-d may be disposed in data width translator circuit 2950 and/or left of data width translator circuit 2950. For example, multiplexers 2903a-d and delay circuits 2904a-d may be disposed internal to an integrated circuit buffer, as opposed to an interface of an integrated circuit buffer device, or in an integrated circuit memory device.
Levelization or the amount of delay (if any) provided to read data on signal paths DQ_DRV[0:3] is dependent upon the signal path (between a memory module and a master) used by a system to provide the read data to the master (or flight time or amount of time to transfer read data from a memory module to a master and/or another memory module). For example in a system 2600 shown in
Data width translator circuit 2950 may be configurable to translate data of various widths into data suitable for a fixed-width memory die or device disposed on a memory module. Data width translator circuit 2950, in accordance with some embodiments, uses a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides physical address locations of the memory die into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a particular memory die. As used herein, the term “width” refers to the number of bits employed to represent data.
A data width translator circuit 2950 allows memory modules, such as memory modules 2601 and 2602, to vary the effective width of their external memory module interfaces without varying the width of the internal memory device/die interfaces. A memory system thus may support a first mode of operation and a second mode of operation (bypass mode). In the bypass mode of operation, memory module 2601 uses both signal path 2610 and signal paths 2611 and 2612 (via memory module 2602).
In accordance with an embodiment, data width translator circuit 2950 can translate data of width one, two, or four on signal paths DQ[0:3] into four-bit-wide data on signal path IDQ[0:3]. Address translator circuit 2970 translates address signals on signal path RQ to signal path IRQ which is coupled to one or more memory devices. This flexibility allows one or a combination of memory modules to be used in an extensible point-to-point memory topology. Similarly, data width translator circuit 2950 can translate data of width one, two, or four on signal paths IDQ[0:3] into four-bit-wide data on signal path DQ[0:3].
Data width translator circuit 2950 includes a data translator circuit 2960, an address translator circuit 2970, and a DLL 2980. DLL 2980 produces an internal differential clock signal ICLK locked (or having a temporal relationship) to a like-identified incoming differential clock signal CLK, typically from an associated master or a clock-generator device. Though not shown, a memory device disposed on a memory module may receive the same or a similar clock signal CLK from data width translator circuit 2950 or a master. Data translator circuit 2960 and address translator circuit 2970, responsive to a configuration signal CFG, translate the data on one, two, or four of data signal paths DQ[0:3] into four-bit-wide data on signal paths IDQ[0:3] for write cycles; and conversely translate four-bit-wide data on signal paths IDQ[0:3] into one, two, or four-bit-wide data on one or more of external signal paths DQ[0:3] for read cycles. In one embodiment, plugging a second memory module into a two-connector mother board automatically asserts configuration signal CFG, causing each of two memory modules to configure themselves as half-width (e.g., two bits instead of four) modules. In other embodiments, configuration signal CFG comes from a register on a memory module (e.g., within data width translator circuit 2950) that is addressable by a master and is set, such as via the BIOS, at boot time. In other embodiments, a configuration signal CFG is provided after reading values stored in a SPD device. In general, an external memory module interface conveys data signals of data-width N, an internal memory device interface conveys signals of data-width M, and configuration signal CFG is indicative of the ratio of N to M. Some embodiments use a PLL instead of DLL 2980.
A fixed-width memory device disposed on a memory module may include a mask line/signal path or pin that can be used in support of partial-write operations. For example, double data rate “DDR” memory die include a data-mask pin DM and single data rate “SDR” memory die include a data-mask pin DQM. Memory modules detailed herein may employ data-mask functionality to create variable-width modules using fixed-width memory devices. In an embodiment, a data-mask signal DM is output from data translator circuit 2960 to one or more memory devices in order to synchronize write operations.
In an embodiment, bypass circuit 2900 includes bypass elements 2905-2910 and not multiplexers 2903a-d and delay circuits 2904a-d. In an alternate embodiment, bypass circuit 2900 includes multiplexers 2903a-d and delay circuits 2904a-d and not bypass elements 2905-2910. For example, memory module 2601 shown in
In an embodiment, data width translator circuit 2950 uses mask signal DM to divide the addressed physical locations in a fixed-width memory device into subsets of memory locations addressed separately in the time domain, a process that may be referred to as “time slicing.” For example, a most significant bit(s) (MSB(s)), or any other bits in address A, causes data translator circuit 2960 (via a signal from address translator circuit 2970 to data translator circuit 2960) to assert a mask signal DM (DM=1) to block writes to a first set of locations having address A, and then de-asserts mask signal DM (DM=0) to allow writes to the second set of locations having address A. This process then may repeat.
In an embodiment, the address space in memory module 2704 (i.e. memory devices) is bisected in the time domain. One of the external address bits of address A is employed to assert mask signal DM every other time slot. In this embodiment, the MSB of the external address A is zero, so mask signal DM is deasserted for every time slot MSB=0 to allow writes during those time slots.
Method 3100 begins at logic block 3101 where a determination is made whether to levelize or adjust delays to read and write data in a memory system. In an embodiment, this determination may be made at initialization, periodically or during calibration (testing). If levelization is not desired, method 3100 ends. Otherwise, integrated circuit buffer devices are set to a typical or first mode of operation as illustrated by logic block 3102. In an embodiment, a control signal from a master, such as master 2101 shown in
Logic block 3103 illustrates levelizing read data or providing delays to read data to take into account different flight times or distances the read data must travel on different signal paths in reaching a master. For example, signal path 2612 has a longer signal path than signal path 2610. Therefore, in order for read data 2601a and 2602a from both memory modules 2601 and 2602 to reach master 2101 at the approximate same time, a delay should be introduced into the read data 2601a to account for the longer flight time or distance of signal path 2612. In an embodiment, delays are provided in response to delay values stored in registers on the integrated circuit memory devices and programmed by the master. In alternate embodiments, delays corresponding to respective memory modules are provided and programmed in the master. Test symbols or test data may be written and read from the integrated circuit memory devices to determine the programming of the delay values.
A determination is then made whether a memory system includes different capacity memory modules as illustrated by logic block 3104. If different capacity memory modules are not present, control transitions to logic block 3107. Otherwise, control transitions to logic block 3105. In an embodiment, the determination illustrated by logic block 3104 may be completed by a master reading configuration information of a system stored in an SPD.
Integrated circuit buffer devices are then set to a second mode of operation (bypass mode) as illustrated in logic block 3105. In an embodiment, the bypass mode of operation is set by providing control signals to a bypass circuit in an integrated circuit buffer device, for example bypass elements 2905-2910 in a bypass circuit 2900 as illustrated in
Read data from a larger capacity memory module is then levelized as illustrated by logic block 3106. For example, delays are added to read data 2601b of memory module 2601 (larger capacity) as illustrated in
Integrated circuit buffers in a smaller capacity memory module are set to a first mode of operation (or a non-bypass mode) as illustrated by logic block 3109. For example, memory module 2602 in
Read data levelization for the smaller capacity memory module is then performed as illustrated by logic block 3108.
Write data levelization for data written to memory modules is performed in logic block 3107.
A determination is then made whether a memory system includes different capacity memory modules as illustrated by logic block 3110. If different capacity memory modules are not present, method 3100 ends. Otherwise, control transitions to logic block 3111. In an embodiment, the determination illustrated by logic block 3110 may be completed by a master reading configuration information of a system stored in a SPD.
Integrated circuit buffer devices are then set to a second mode of operation (bypass mode) as illustrated in logic block 3111. In an embodiment, the bypass mode of operation is set by providing control signals to a bypass circuit in an integrated circuit buffer device, for example bypass elements 2905-2910 in a bypass circuit 2900 as illustrated in
Write data to larger capacity memory modules is then levelized (in addition to the write data levelization illustrated in logic block 3107) as illustrated by logic block 3112. In an embodiment, additional write delays are added, in response to stored write delay values, to the write data at a master, integrated circuit buffer device and/or memory device. Delays to write data may be selected based on whether write data is transferred through a memory module having an integrated circuit buffer device in a bypass mode of operation. For example, write data provided to memory module 2601 on signal path 2610 from master 2101 may be delayed compared to write data provided to memory module 2601 on signal paths 2612 and 2611 (by way of bypass circuit 2630b) from master 2101 so that the write data may arrive at approximately the same time.
While topologies are illustrated with memory modules 3200a-e, 3300a-b and 3400, these illustrated topologies in
In embodiments, a master, such as master 2101 may provide control/address information and data to one or more integrated circuit buffer devices 3201 in a topology illustrated in
In embodiments, termination may be disposed on buffer 3201, memory modules 3200a-e, 3300a-b and 3400, signal paths, memory devices 101a-d and/or elsewhere in a system, such as on an PCB or substrate. In embodiments, termination for the signal paths in the topologies shown in
In a memory read operation, buffer device 3600 operates similar to buffer 100a shown in
In an embodiment, memory devices 101a-d are configured into memory ranks having segmented (point-to-point) signal paths 1006 and a shared fly-by bus signal path 1005 as illustrated in
In a memory write operation embodiment, buffer 3600 operates similar to buffer 100a. Buffer 3600 receives control information (including address information) that may be in a packet format from a master on signal path 121 and receives the write data for one or more memory devices 101a-d that may be in a packet format from a master on signal path 120a. In an embodiment, command decode 3607 and address translation 3608 output control signals to data path 3606, data path router 3610 and interface 3611 so that received write memory commands and received write addresses are decoded and translated to corresponding control/address signals output on signal path 1005. Buffer 3600 then transmits corresponding signals to one or more, or all of memory devices 101a-d on one or more signal paths 1006 so that the write data may be stored. In an embodiment, data path 3606 and data path router 3610 (in response to control signals) segments or parses received write data into two or more write portions and directs the write portions to the appropriate signal paths 1006 (via interface 3611) so that the write portions will be stored in two or more memory devices. Accordingly, buffer 3600 may receive write data having an associated write address to a particular memory device and parses/segments the received write data into a plurality of different write data portions which are then routed to a plurality of different memory devices at a plurality of different write addresses for storage.
Interfaces 3601 and 3611 correspond to portions of interfaces 1103a and interfaces 1820a-b shown in
In an embodiment, interface 3611 can be segmented into at least three different configurations or segmentation modes: 1) Four 4-bit interfaces (4×4), 2) Two 4-bit interfaces (2×4) or 3) Two 8-bit interfaces (2×8). The different configurations allow flexibility in memory module or memory stack configurations. Accordingly, buffer 3600 may interface with high-capacity or lower-capacity entry level memory modules or in particular memory devices. A four 4-bit interface may be used in high capacity memory modules. A two 8-bit interface may be used for low-cost memory modules. A two 4-bit interface may be used for low-cost memory modules that still support ECC.
The assignment of strobe pins to data pin groupings is adjusted depending upon the segmentation mode:
4×4 segmentation mode:
2×4 segmentation mode:
2×8 segmentation mode:
Interface 3601 enters segmentation modes in response to bit values stored in register set 3605 and/or one or more control signals from address translation 3608.
Data path router 3610 routes read and write data between data path 3606 and interface 3611. Control signals from command decode 3607 and address translation 3608 determine the routing of read/write data. Data path router also receives signals from pattern generator 3609 and internal memory array 3612. In a mode of operation that emulates operation with a memory device, all memory transactions are routed to and from internal memory array 3612 rather than interface 3611. Interface 3611 may be disabled during this mode of operation. In an embodiment, pattern generator 3609 is used as an alternate source of data (or test pattern of data) as well as a source for injecting ECC errors in modes of operation. The test pattern of data may be transmitted on either interface 3601 or interface 3611 or some portion of both simultaneously. Similarly, pattern generator 3609 may insert ECC errors on either interface 3601 or interface 3611 or some portion of both simultaneously. In an embodiment, data path router 3610 includes XOR logic used for ECC error injection. In embodiments, read and write data may proceed through data path 3606 in both directions simultaneously. Modes of operation of buffer 3600 may be entered by setting one or more bit values in multi-bit register set (or storage circuit) 3605.
Data path router 3610 includes a write data router 3610a and read data router 3610b. In an embodiment, write data router 3610a outputs write data in response to a WCLK clock signal while the read data router 3610b outputs read data in response to a RCLK clock signal (either the positive or negative edge of RCLK clock signal). The use of two clock domains may enable the buffer 3600 to reduce latency and/or operate at a higher data rate.
During a typical mode of operation, write data router 3610a receives write data and mask information from data path 3606 and then routes the write data (or portion of the write data) to one of four signal paths 1006 coupled to interface 3611. Similarly during a read operation, read data is received from one of four signal paths 1006 coupled to interface 3611 and routed to data path 3606.
Data path router 3610 includes a plurality of signal paths used to merge read data from different memory devices as well as parse write data into write data portions to be stored in multiple memory devices.
Command decode 3607 includes a decoder to output control signals to data path 3606, address translation 3608 and data path router 3610 in response to control information received by interface 3601 from signal path 121. In embodiments, the control information may include memory transaction commands, such as read or write commands. Other control information may include a command to activate a particular memory bank in a particular memory device or access information having a particular page size. In an embodiment, command decode 3607 may remap/translate a received bank address to a different bank address of one or more memory devices coupled to signal paths 1006.
Address translation circuit 3608 receives an address associated with a particular memory transaction command by way of signal path 121 and interface 3601. For example, address translation circuit 3608 receives an address for reading data associated with a read command for a particular memory device in a particular memory organization (for example, number of ranks, number of memory devices, number of banks per memory device, page size, bandwidth). Address translation 3608 then outputs control signals (or a translated address and/or control signals) to interface 3611 (and signal path 1005) so that the read data may be read from different memory devices (via signal paths 1006) because the memory organization coupled to interface 3611 is different than indicated in the read command. In an embodiment, address translation 3608 may include a storage circuit to store a look-up table for translating addresses. Similarly, write addresses associated with a write command are received by address translation 3608 which outputs control signals (translated write addresses) to interface 3611 and signal path 1006 so that the corresponding write data from data path 3606 may be written to one or more translated write addresses of memory devices coupled to signal paths 1006.
In an embodiment, information in a received row address field is used to output chip select signals. Buffer device 3600 outputs chip select information, such as chip select signals, from interface 3611 to one or more integrated circuit memory devices in response to information in a row address field received at interface 3601. One or more row address bit values may be remapped to chip select signals. For example, values of two particular row address bits may be used to generate four one-hot chip select signals from interface 3611 to four or more integrated circuit memory devices.
In an embodiment, information in a received row address field and received chip select signals are used to output chip select signals. Buffer device 3600 receives chip select information, such as chip select signals (via interface 3601) and information in row address fields to generate one or more chip select signals from interface 3611 to a plurality of integrated circuit memory devices. For example, two one-hot chip select signals received at interface 3601 along with two bit values in a row address field may be used to output eight chip select signals at interface 3611 to eight integrated circuit memory devices. Similarly, four received chip select signals may be used with one bit value in a row address field to output eight chip select signals from interface 3611.
In an embodiment, information in a bank address field is used to output chip select signals. Buffer device 3600 outputs chip select information from interface 3611 to one or more integrated circuit memory devices in response to the bank address information received at interface 3601. Unused bank address fields/pins at interface 3601 may be used to provide chip select information at interface 3611. For example, interface 3601 may have 5 bank address pins while four integrated circuit memory devices having 8 banks each are coupled to interface 3611. The lower 3 pins, BA[2:0], would identify a particular bank in a particular memory device while the upper two bits BA[4:3] are used to decode/output chip select signals. The four memory devices and buffer device 3600 then may emulate one large memory die with 32 memory banks rather than 4 memory dies having 8 banks each.
In an embodiment, multiple chip select signals may be output simultaneously from interface 3611 to multiple respective memory devices in response to information in a row address field, chip select information and/or bank address information, singly or in combination.
Address translation circuit 3608 includes one or more multiplexers to receive (via interface 3601) information in a row address field, chip select information and/or bank address information and outputs signals to interface 3611 that in turn outputs chips select signals in an embodiment.
One or more column address bit values may be re-tasked/remapped by buffer 3600 to perform time slicing, as described above, in an embodiment. For example, the functions (or portions thereof) of data width translator 2950 may be performed by address translator 3608, command decode 3607, data path 3606 and data path router 3610, singly or in combination. Also, bit values in a column address field may also be used to initiate memory device functions/operations. When information in a column address field are re-tasked and this re-tasking uses lower order bit values, the remaining address bit values may be shifted to fill the lowest order column address bit values output at interface 3611. For example, when bit values in column address A[4:3] in a column address field are remapped to time slice address bits, column address values in column address A[15:5] are shifted to column address A[13:3] to fill the lowest order column address bits.
In an embodiment, column address bit values may not be shifted when column address bit values are used to initiate a memory device operation. For example, a bit value in column address A[10] may be used to trigger an auto-precharge operation in a DDR3 memory device. When time slicing is used as described above, a bit value in column address bit A[10] would be mapped to column address bit A[10] (or not changed) while bit values in column addresses A[15:11] and A[9:5] are shifted to fill the gap caused by re-tasking bit values in column address A[4:3]. Another similar example of not shifting a particular column address value includes a bit value at column address A[12] used to trigger burst chop on column address cycles in a DDR3 memory device. In a burst chop mode of a DDR3 memory device, a portion of the read data (for example the last 4 bits of 8 bit output data) is masked or not output from an integrated circuit memory device.
Buffer device 3600 may remap column bit values used to initiate a memory device operation (i.e., auto-precharge, burst chop, read sequence ordering) to particular column address bit fields. For example, bit values in column address bits A[2:0] are used to define bit ordering from a DDR memory device. Data on each signal line coupled to an integrated circuit memory device will be returned in a different order depending on the column bit values at column address bits A[2:0]. When buffer device 3600 performs time slicing, these column bit values are reassigned to a different value to match a “time” address used to store data and to efficiently move data from an integrated circuit memory device to buffer device 3600. In an embodiment, data path 3606 rearranges the data (from data path router 3610) in response to control signals from address translation circuit 3608 which receives column bit address values at column address A[2:0].
When less data is needed by buffer device 3600 than expected by an integrated circuit memory device, such as in time slicing, the buffer device 3600 may use burst chop to save I/O power from the integrated circuit memory devices. This would be irrelevant of the value of a column address bit A[12] (BCN). The received BCN bit values may be stored in the data path 3605 or command decode circuit 3607 that outputs signals to chop the data as originally requested by way of interface 3601.
In an embodiment, received chip select information and bit values in a received row address fields may be used by buffer device 3600 to assign/remap column bit values in column addresses output at interface 3611.
Address translation circuit 3608 includes one or more multiplexers to receive (via interface 3601) information in a column address fields and reassign/re-task column address bit values during time slicing and/or otherwise as describe above.
Buffer device 3600 may receive row address values or chip select information that then may be used to configure a memory system that accesses different sized/capacity (address space) memory modules during different modes of operations as described above in regard to
In embodiments, buffer 3600 may include JTAG 3603 and/or 12C 3604 interfaces/circuits for accessing bit values in register set 3605. JTAG 3603 may include a port having test pins used during testing of buffer 3600. An 12C 3604 may be used for outputting or receiving bit values (by way of an 12C bus) for register set 3605 that outputs control signals to buffer device circuit components in response to stored bit values that may represent particular buffer configurations. In an embodiment, bit values in register set 3605 may be accessed (written/read) directly through interface 3601.
In an embodiment, register set 3605 corresponds to configuration register set 1881 shown in
In an embodiment, register set 3605 may store one or more bit values indicating where to obtain information in received control information (i.e. a request packet) that may be used in determining/remapping and outputting chip select information or signals to one or more integrated circuit memory devices. As described below, information in row address fields, column address fields, bank address fields as well as received chip select signals may be used to decode and output predetermined chip select signals from integrated circuit buffer device 3600 to the plurality of integrated circuit memory devices.
In an embodiment, register set 3605 may store one or more bit values to indicate a number of signal paths (i.e. width), type of signal path topology, a number of signal lines per signal path and/or a number (or existence) of data signal strobe signal lines between integrated circuit buffer device 3611 (in particular interface 3611) and a plurality of integrated circuit memory devices.
In an embodiment, register set 3605 may store one or more bit values to indicate how received column, row and/or bank addresses are reordered and output from buffer device 3600.
PLL 3602 is used to synchronize the timing of receiving and/or transmitting read and write data both internally and externally to buffer 3600. In alternate embodiments, PLL 3602 may be another clock alignment circuit that corresponds to clock circuit 1870 shown in
Control information, such as commands to activate a memory rank are illustrated by a shaded block An that represents the amount of time control signals are provided on a control/address signal path (external (Ext.) RQ or internal (Int.) RQ signal paths) during cycles of a Clock signal. For example, shaded block Aa on a row labeled Ext. RQ represents a buffer device receiving a command to activate a memory rank “a” on an Ext. RQ signal path during a first clock cycle of the Clock signal. Similarly a command to read a particular memory bank is illustrated by shaded blocks Rn on signal paths Ext. RQ and Int. RQ. For example, timing chart 3700 illustrates how a read command Ra is received by a buffer device via signal path Ext. RQ and a command Ra is output a clock cycle later onto signal path Int. RQ. In alternate embodiments, more or less memory commands or control signals may be received and generated.
Similarly, read data transferred on signal paths Ext. DQ and Int. DQ to a memory controller or from a memory rank are illustrated by a shaded block labeled Read Datan. Write data may be similarly transferred.
Signal path Ext. RQ refers to a signal path that provides control/address information from a memory controller to the buffer device. Signal path Int. RQ refers to a signal path that provides control/address information from the buffer device to a plurality of integrated circuit memory devices or memory rank. Signal path Ext. DQ refers to a signal path that provides Read Datan from the buffer device to the memory controller. Signal path Int. DQ refers to a signal path that provides Read Datan from a plurality of integrated circuit memory devices or memory rank to the buffer device. In an embodiment, Ext. RQ corresponds to signal path 121 and Int. RQ corresponds to signal path 1005; while Ext. DQ corresponds to signal path 120a and Int. DQ corresponds to signal path 1006.
Timing chart 3700 illustrates that when memory ranks are coupled to the same (or shared/common) signal path that transfers Read Datan, a memory system may have to be more complicated and less efficient. In particular, a shared signal path among memory ranks for transferring Read Datan may require a memory controller to track accesses to memory ranks and insert bubbles when changing access to different memory ranks. A “bubble” or “time bubble” refers to an amount of idle time a memory controller must insert in transferring data when switching between memory transaction to the same memory rank. For example, a memory controller may have to insert a bubble or idle time when switching from accessing different memory ranks so as to allow the shared or common bus to settle (or allow time for tri-state drivers in a transceiver to switch to an alternate state as well as allow time for another preamble signal) or for noise to dissipate before initiating another memory rank access or (in the case of strobed memory devices) to allow for a strobe preamble. This insertion of bubbles reduces signal path utilization and may lower bandwidth on both internal and external signal paths.
A “memory rank” or “rank” refers to a number of integrated circuit memory devices grouped to output a predetermined amount of data bits or blocks of data, such as 72 data bits (64 data bits plus 8 ECC bits provided by an ECC device), onto a signal path during a predetermined period of time. For example a dual rank system (using rank 1 and rank 2 shown in
Buffer device 3600 receives control/address information as well as data from a memory controller via signal paths 120a and 121. In an embodiment, interface 3601 as illustrated in
Interface 3611 is coupled to signal paths 3801-3804 and signal path 3810. Signal paths 3801-3804 are segmented signal paths to transfer read and write data between buffer device 3600 and integrated circuit memory devices in ranks 1-4. Signal path 3801 is coupled to memory devices 101a-n in rank 1. Signal path 3802 is coupled to memory devices 101a-n in rank 2. Signal path 3803 is coupled to memory devices 101a-n in rank 3. Signal path 3804 is coupled to memory devices 101a-n in rank 4. In an embodiment, read and write data is transferred using a segmented topology as illustrated in
In contrast, signal path 3810 provides control/address information to memory ranks 1-4 on a shared/common signal path 3810, such as a fly-by topology shown in
In an embodiment, data segment and merge circuit 3902 operates similar to one or more circuit components in buffer device 3600 shown in
A virtual page size/length may be the size of data or memory block that may be used by a processor or memory controller. For example, if a process requests an operating system to allocate 64 bytes, but the page size is 4 KB, then the operating system must allocate an entire virtual page or 4 KB to the process. In embodiments, a physical page size/length may equal the amount of data provided by a memory rank or the amount of data bits available from a plurality of sense amplifiers in one or more banks of one of more integrated circuit memory devices in the memory rank. A virtual page size may equal a physical page size in an embodiment. A memory controller may be able to adjust the virtual page size but not the physical page size.
Logic blocks 4003 and 4004 illustrate outputting second and third control information to a first signal path coupled to first and second integrated circuit memory devices in the second memory organization.
Logic blocks 4005 and 4006 illustrate receiving first and second data from second and third signal paths coupled to the first and second integrated circuit memory devices in the second memory organization.
Logic block 4007 illustrates merging and output read data that includes the first and second read data from the integrated circuit buffer device in response to the first control information.
In an embodiment, one or more logic blocks 4002-4007 may be repeated.
Logic block 4008 illustrates ending method 4000 when power is removed. In alternate embodiments, method 4000 may end without power removed.
A method of operation of a buffer device that transfers write data performs similar steps illustrated in method 4000. However rather than receiving and outputting read data as illustrated by blocks 4005-4007, write data may be segmented and transferred to second and third signal paths in response to first control information.
Signals described herein may be transmitted or received between and within devices/circuits using signal paths and generated using any number of signaling techniques including without limitation, modulating the voltage or current level of an electrical signal. The signals may represent any type of control and timing information (e.g. commands, address values, clock signals, and configuration/parameter information) as well as data. In an embodiment, a signal described herein may be an optical signal.
A variety of signals may be transferred on signal paths as described herein. For example, types of signals include differential (over a pair of signal lines), non-return to zero (“NRZ”), multi-level pulse amplitude modulation (“PAM”), phase shift keying, delay or time modulation, quadrature amplitude modulation (“QAM”) and Trellis coding.
In an embodiment employing multi-level PAM signaling, a data rate may be increased without increasing either the system clock frequency or the number of signal lines by employing multiple voltage levels to encode unique sets of consecutive digital values or symbols. That is, each unique combination of consecutive digital symbols may be assigned to a unique voltage level, or pattern of voltage levels. For example, a 4-level PAM scheme may employ four distinct voltage ranges to distinguish between a pair of consecutive digital values or symbols such as 00, 01, 10 and 11. Here, each voltage range would correspond to one of the unique pairs of consecutive symbols.
In an embodiment, a clock signal is used to synchronize events in a memory module and/or device such as synchronizing receiving and transmitting data and/or control information. In an embodiment, globally synchronous clocking is used (i.e., where a single clock frequency source is distributed to various devices in a memory module/system). In an embodiment, source synchronous clocking is used (i.e., where data is transported alongside a clock signal from a source to a destination such that a clock signal and data become skew tolerant). In an embodiment, encoding data and a clock signal is used. In alternate embodiments, combinations of clocking or synchronization described herein are used.
In embodiments, signal paths described herein include one or more conducting elements, such as a plurality of wires, metal traces (internal or external), signal lines or doped regions (positively or negatively enhanced), as well as one or more optical fibers or optical pathways, singly or in combination. In embodiments, multiple signal paths may replace a single signal path illustrated in the Figures and a single signal path may replace multiple signal paths illustrated in the Figures. In embodiments, a signal path may include a bus and/or point-to-point connection. In an embodiment, signal paths include signal paths for transferring control and data signals. In an alternate embodiment, signal paths include only signals paths for transferring data signals or only signal paths for transferring control signals. In still other embodiments, signal paths transfer unidirectional signals (signals that travel in one direction) or bidirectional signals (signals that travel in two directions) or combinations of both unidirectional and bidirectional signals.
It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented) as data and/or instructions embodied in various computer-readable media, in terms of their behavior, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to: formats supporting behavioral languages such as C, Verilog, and HLDL; formats supporting register level description languages like RTL; formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.). When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, netlist generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
The foregoing description of several embodiments has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to explain inventive principles and practical applications, thereby enabling others skilled in the art to understand various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
This application is a continuation of U.S. patent application Ser. No. 16/692,043, filed on Nov. 22, 2019, which is a continuation of U.S. patent application Ser. No. 16/214,986, filed on Dec. 10, 2018 (now U.S. Pat. No. 10,535,398), which is a continuation of U.S. patent application Ser. No. 15/832,468 filed on Dec. 5, 2017 (now U.S. Pat. No. 10,381,067), which is a continuation of U.S. patent application Ser. No. 15/389,409 filed on Dec. 22, 2016 (now U.S. Pat. No. 9,865,329), which is a continuation of U.S. patent application Ser. No. 14/801,723 filed on Jul. 16, 2015 (now U.S. Pat. No. 9,563,583), which is a continuation of U.S. patent application Ser. No. 14/015,648 filed on Aug. 30, 2013 (now U.S. Pat. No. 9,117,035), which is a continuation of U.S. patent application Ser. No. 13/149,682 filed on May 31, 2011 (now U.S. Pat. No. 8,539,152), which is a continuation of U.S. patent application Ser. No. 12/703,521 filed on Feb. 10, 2010 (now U.S. Pat. No. 8,108,607) which is a continuation of U.S. patent application Ser. No. 12/424,442 filed on Apr. 15, 2009 (now U.S. Pat. No. 7,685,364) which is a divisional of U.S. patent application Ser. No. 11/697,572 filed on Apr. 6, 2007 (now U.S. Pat. No. 7,562,271) which is a continuation-in-part of U.S. patent application Ser. No. 11/460,899 filed on Jul. 28, 2006 (now U.S. Pat. No. 7,729,151) which is a continuation-in-part of U.S. patent application Ser. No. 11/236,401 filed on Sep. 26, 2005 (now U.S. Pat. No. 7,464,225).
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