1. Field of the Invention
This invention relates generally to the thermally conductive bonding of materials and more particularly thermally conductive bonding of materials that undergo temperature changes where said materials have different coefficients of thermal expansion.
2. Description of the Related Art
In some fields of optical and laser-electronics, and micro-electrical/mechanical devices the component size can be significantly large; e.g. greater than 625 mm2. This is particularly true when dealing with arrayed devices such as imaging sensors, digital liquid crystal displays or attenuators, digital infrared emitters, laser diodes, and deformable mirrors that can be planar, have a curved or a polygonal surface.
Packaging a device typically requires a second component of adequate design and geometry to facilitate a device's operation and provide a means to integrate the device into a product. The device and package component are typically joined or bonded at some level. The bond is required to provide any or all of the following characteristics: mechanical adhesion, bond strength, thermal conductivity, and electrical conductivity; and not induce damage or affect required functionality of the device and package component while being exposed to environmental influences; specifically large changes in temperature during processing and operation.
When large parts are required to be joined using solders, epoxies, adhesives, or any two-phase materials, and thermal or electrical conductivity must be well maintained, the bond must be made such that the one part can expand or contract at a greater rate than the other one without damaging one or both of the parts and without disrupting the thermal or electrical conductivity of the bond during temperature changes that range from room temperature to cryogenic temperatures. The larger the area of the bond the greater the need for compliance in the bond as the induced thermal stress due to expansion mismatch in substrates becomes larger. This is especially needed when the temperature at which the bond was formed is far different than the temperature at which a device that includes the bond is operated; e.g., cryogenic temperatures.
Achieving an accurate bond thickness is essential to obtaining the desired interface stress state and maintaining desired geometrical and functional relationships of the device and its package. During the bonding process this task can be difficult to control due to complexities of the bond wetting, shrinkage of the bonding material, and general applied mass required to maintain device and package intimacy.
Known methods for reducing the induced stress/strain state of joined components include increasing the size of the gap or bond thickness. Depending on the elastic/plastic properties of the bonding material a certain level of success can be achieved using arrayed solder or adhesive bumps or columns, electroformed hinge contacts, or thick bonding layers. When the bonding area gets large, greater than 625 mm2, and the required operational temperature range is greater than 300 K the bond thickness can range from tens to hundreds of microns. Arrayed bonding sites can be applied in large areas which reduces the likelihood of deformation of the device or package but due do the separated nature this approach does not offer the thermal transfer benefits of a continuous bond material.
Use of high strength bonding materials; e.g. AuSn, can reduce the likelihood of fatigue of the joint and offer excellent heat transfer; however high process temperatures for this material makes it unsuitable for joining temperature sensitive devices. Additionally due to the lack of plasticity of this bonding material, especially in large area bonds, the induced stress/strain, caused by the large temperature differential from bonding down to cryogenic and the general large area of the bond, is directed at the joined components fully which then must be designed for added strength or increased compliance. This can be costly and reduce device yields.
Popular bonding materials such as Pb, PbSn, leadfree solders, filled epoxies, and alloys of Bi, Sn, Cd, and Ga have poor cryogenic ductility and become brittle as high aspect ratio features or of large bond thickness. Indium or high indium content alloy solders exhibit exceptional ductility at cryogenic temperatures and large plasticity when subjected to high stress. Indium readily cold welds to itself and attaches to other surfaces if care is taken to address oxide formation; and can be processed at relatively low temperatures within the range typically experienced by sensitive electronic devices during final fabrication or operation. Candidate solders other than those with high percentages of indium formed in gaps greater than 50 microns are susceptible to significant creep and stress induced fracture at cryogenic temperatures.
Known methods for filling a precise gap using a solder preform includes a solder matrix having microparticles such as molybdenum secured within the solder matrix; ref U.S. Pat. No. 7,422,141. The microparticles are of different forms and self arrange during a solder bonding process so as to provide a uniform separation between opposing soldered surfaces.
One major drawback of this technique is that the solder matrix must be prepared in advance and cast as a preform. The ability to produce uniform preforms that are free standing and can maintain extremely uniform thicknesses using high ductility, oxide sensitive, indium solders is difficult and costly. This task is time-consuming and reduces yield. Secondly the temperature of preform and the surfaces to be joined must still be raised above the solder solidus to form a continuous bond which exposes the solder joint and the parts to the same stress/strain effects upon cooling.
Room temperature curing conductive adhesives, using a gap filler medium, expose the surfaces to be joined to significantly smaller temperature differentials reducing the aforementioned stress/strain effects. Unfortunately these adhesives or epoxies typically do not exhibit adequate adhesive strength at cryogenic temperatures when applied in thick layers or large areas without using an elevated temperature curing profile and/or significant mechanical or chemical roughening of the bondable surfaces. Additionally the heat transfer performance of these adhesive matrices are inferior to solder or two-phase alloys.
On the other hand, a known method of making tall accurate structures is referred to in the art as LIGA; ref Becker et al. This method involves lithography, electrodeposition (i.e., galvanoforming), and molding. According to this method, lithography is used to define patterns in polymer resist films. The patterns are then filled with metal by electrodeposition. While this method permits the formation of relatively large structures with high aspect ratios (10 to hundreds of microns tall and only a few microns wide), it does not allow the device complexity obtained by surface micromachining; or include the thermal and electrical conductivity benefits of a continuous adhesive bond.
Alternatively direct patterning and electrodeposition of structures on to semiconductor wafers has been described in detail in U.S. Pat. No. 7,271,022. In this reference lithography is used to produce windows in a resist material; these windows are filled with a metal and either with surface micromachining or using etching methods the height of these structures is accurately obtained. With proper choice of process and materials complex patterns and various densities of structures can be produced on a wide array of materials. While this method is the preferred method for producing accurate height structures on a micro-scale it does not combine the use of a bonding agent or material to facilitate the construction of a highly compliant, high heat transfer, and cryogenic capable adhesive joint.
In view of the foregoing, it would be desirable to provide a method of fabricating an accurate thickness bond between large area temperature sensitive devices and their packages that integrates the benefits of large scale high aspect ratio electrodeposited metal structures and the properties of highly compliant, cryogenic capable, thermally and/or electrically conductive bonding materials such that low stress/strain levels exist at the joined interfaces, high adhesive strength is achieved, a continuous or semi-continuous bond area is achieved, and parts and joint can be bonded at near ambient temperatures.
E. W. Becker, W. Ehrfeld, P. Hagmann, A. Maner and D. Muchmeyer-Fabrication of microstructures with high aspect ratios and great structural heights by synchrotron radiation lithography, gavanoforming, and plastic moulding (LIGA process)—Mar. 3, 1986.
The present invention solves the above-described deficiencies by providing a uniform continuous/semi-continuous large area, thermal and electrical conductive, ambient temperature solder bond for electronic/optical-electronic devices and packaging with integral structural features to accurately control the bond thickness; and capable of accommodating thermal induced stress/strain effects of parts with dissimilar coefficients of thermal expansion over a wide temperature range, >300 K, exhibiting reliable cryogenic performance to 20 K and bonding adhesion.
The foregoing and other features, aspects and advantages of the present invention will become better understood with reference to the accompanying drawings in which:
FIG. 1—Assembled Component Bond Interface with Microstructural Features
FIG. 2—Thermal induced stress is proportional to bond area and expansion coefficient differential
FIGS. 3-9—are schematic views illustrating steps of an embodiment of the process of the invention for making an accurate thickness, highly compliant, continuous bond between two substrates at ambient temperature.
FIG. 10—Solder reflow and deposition
FIG. 11—Solder reflow and substrate joining
At the start of the process the substrates 100, 400 of selected materials are cleaned and prepared for application of the microstructure 300 which will determine part of the required bonding gap of the final assembly. In the trade numerous cleaning processes appropriate for the specific substrate have been developed by many sources and are applied accordingly.
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