Claims
- 1. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) preparing moisture at a first temperature from oxygen and hydrogen by use of a catalyst; (d) transferring the thus-prepared moisture into a wafer heat treatment chamber of a batch processing vertical oxidation furnace to form a wet oxidative atmosphere around a plurality of wafers inside the chamber, while keeping the moisture in a gaseous state; and (c) performing thermal oxidation to a silicon member over a first major surface of each of the wafers in the wet oxidative atmosphere in the wafer heat treatment chamber by heating the wafers up to a second temperature higher than the first temperature.
- 2. A method for fabricating a semiconductor integrated circuit device according to claim 1, wherein said insulating film is a gate insulating film of an insulated gate field effect transistor.
- 3. A method for fabricating a semiconductor integrated circuit device according to claim 2, wherein thickness of the gate insulating film of said insulated gate field effect transistor is not more than 5 nm, and gate length thereof is nor more than 0.25 μm.
- 4. A method for fabricating a semiconductor integrated circuit device according to claim 3, wherein the thickness of the gate insulating film of said insulated gate field effect transistor is not more than 3 nm.
- 5. A method for fabricating a semiconductor integrated circuit device according to claim 1, wherein the first temperature is not more than 500° C., and the second temperature is not less than 800° C.
- 6. A method for fabricating a semiconductor integrated circuit device according to claim 1, wherein the thermal oxidation is performed while providing the heat treatment chamber with said wet oxidative atmosphere.
- 7. A method for fabricating a semiconductor integrated circuit device according to claim 1, further comprising the steps of:
(d) prior to step (b), introducing the wafers into the heat treatment chamber while providing the heat treatment chamber with nitrogen gas; and (e) after step (c), drawing the wafers out of the heat treatment chamber while providing the heat treatment chamber with nitrogen gas.
- 8. A method for fabricating a semiconductor integrated circuit device according to claim 6, further comprising the steps of:
(d) prior to step (b), introducing the wafers into the heat treatment chamber while providing the heat treatment chamber with nitrogen gas; and (e) after step (c), drawing the wafers out of the heat treatment chamber while providing the heat treatment chamber with nitrogen gas.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-50781 |
Mar 1997 |
JP |
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Parent Case Info
[0001] This application is a Continuation application of U.S. application Ser. No. 10/424,105, filed Apr. 28, 2003, which is a Continuation application of U.S. Ser. No. 09/939,600, filed Aug. 28, 2001, now U.S. Pat. No. 6,596,650, issued Jul. 22, 2003, which is a Continuation application of U.S. Ser. No. 09/494,036, filed Jan. 31, 2000, now U.S. Pat. No. 6,518,201, issued Feb. 11, 2003, which is a Continuation application of U.S. Ser. No. 09/380,646, filed Sep. 7, 1999, now U.S. Pat. No. 6,239,041, issued May 29, 2001, which is an application filed under 35 USC 371 of PCT/JP98/00892, filed Mar. 4, 1998. The contents of No. 09/380,646 are incorporated herein by reference in their entirety.
Continuations (4)
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Number |
Date |
Country |
Parent |
10424105 |
Apr 2003 |
US |
Child |
10774588 |
Feb 2004 |
US |
Parent |
09939600 |
Aug 2001 |
US |
Child |
10424105 |
Apr 2003 |
US |
Parent |
09494036 |
Jan 2000 |
US |
Child |
09939600 |
Aug 2001 |
US |
Parent |
09380646 |
Sep 1999 |
US |
Child |
09494036 |
Jan 2000 |
US |