Claims
- 1. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:(a) forming an isolation groove between a plurality of active regions in a first major surface of a wafer; (b) forming an insulating region in the isolation groove by depositing an insulating layer; (c) after step (b), synthesizing water vapor from oxygen and hydrogen gases by use of a catalyst; (d) keeping the thus synthesized water vapor in a gaseous state and feeding it into a processing chamber; and then (e) forming a gate insulating film by thermally oxidizing a silicon surface of the active regions under a wet oxidative atmosphere including oxygen gas in the processing chamber.
- 2. A method for fabricating a semiconductor integrated circuit device according to claim 1, wherein said oxidative atmosphere includes oxygen gas as a principal oxidative gas component.
- 3. A method for fabricating a semiconductor integrated circuit device according to claim 2, wherein said oxidative atmosphere includes oxygen gas as a principal gas component.
- 4. A method for fabricating a semiconductor integrated circuit device according to claim 3, wherein the proportion of the water vapor in said oxidative atmosphere ranges from 0.5% to 40%.
- 5. A method for fabricating a semiconductor integrated circuit device according to claim 4, wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
- 6. A method for fabricating a semiconductor integrated circuit device according to claim 5, wherein a thickness of the insulating film of said insulated gate field effect transistor is not thicker than 5 nm, and a gate length thereof is not longer than 0.25 μm.
- 7. A method for fabricating a semiconductor integrated circuit device according to claim 5, wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (c).
- 8. A method for fabricating a semiconductor integrated circuit device according to claim 6, wherein the planarization is performed by a chemical mechanical method.
- 9. A method for fabricating a semiconductor integrated circuit device according to claim 6, wherein the planarization is performed by chemical mechanical polishing.
- 10. A method for fabricating a semiconductor integrated circuit device according to claim 9, wherein the deposition of the insulating layer is performed by chemical vapor deposition.
- 11. A method for fabricating a semiconductor integrated circuit device according to claim 10, wherein the thickness of the insulating film of said insulated gate field effect transistor is not thicker than 3 nm.
- 12. A method for fabricating a semiconductor integrated circuit device according to claim 11, wherein a temperature of the thermal oxidation is not lower than 800 degrees centigrade.
- 13. A method for fabricating a semiconductor integrated circuit device according to claim 12, wherein the thermal oxidation is performed while feeding said oxidative atmosphere over the first major surface of said wafer.
- 14. A method for fabricating a semiconductor integrated circuit device according to claim 1, wherein a composition of hydrogen and oxygen in a gas provided to synthesize water corresponds to that of stoichiometry for water synthesis, or is oxygen-rich.
- 15. A method for fabricating a semiconductor integrated circuit device according to claim 14, wherein the composition of hydrogen and oxygen in the gas provided to synthesize water is oxygen-rich.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-50781 |
Mar 1997 |
JP |
|
Parent Case Info
This application is a Divisional application of application Ser. No. 09/494,036, filed Jan. 31, 2000, which is a Continuation application of application Ser. No. 09/380,646, filed Sep. 7, 1999, which is an application filed under 35 USC 371 of International (PCT) Patent Application No. PCT/JP98/00892, filed Mar. 4, 1998.
US Referenced Citations (4)
Number |
Name |
Date |
Kind |
5693578 |
Nakanishi et al. |
Dec 1997 |
A |
5786263 |
Perera |
Jul 1998 |
A |
6118167 |
DiSimone et al. |
Sep 2000 |
A |
6362086 |
Weimer et al. |
Mar 2002 |
B2 |
Foreign Referenced Citations (18)
Number |
Date |
Country |
59-132136 |
Jul 1984 |
JP |
60-107840 |
Jun 1985 |
JP |
5-114740 |
May 1993 |
JP |
5-141871 |
Jun 1993 |
JP |
5-144804 |
Jun 1993 |
JP |
5-152282 |
Jun 1993 |
JP |
6-115903 |
Apr 1994 |
JP |
6-120206 |
Apr 1994 |
JP |
6-163517 |
Jun 1994 |
JP |
6-333918 |
Dec 1994 |
JP |
7-10935 |
Feb 1995 |
JP |
7-86264 |
Mar 1995 |
JP |
7-115069 |
May 1995 |
JP |
7-193059 |
Jul 1995 |
JP |
7-321102 |
Dec 1995 |
JP |
8-111449 |
Apr 1996 |
JP |
9-172011 |
Jun 1997 |
JP |
97-28085 |
Jul 1997 |
WO |
Non-Patent Literature Citations (1)
Entry |
Nakamura, et al., “Proceedings of the 45th Symposium on Semiconductors and Integrated Circuits Technology”, Tokyo, Dec. 1-2, 1993, pp. 128-133. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09/380646 |
|
US |
Child |
09/494036 |
|
US |