Patent Grant
8476145
1. Field of the Invention
This invention describes applications of monolithic 3D integration to semiconductor chips performing logic and memory functions.
2. Discussion of Background Art
Over the past 40 years, one has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complimentary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate performance, functionality and power consumption of ICs.
3D stacking of semiconductor chips is one avenue to tackle issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), one can place transistors in ICs closer to each other. This reduces wire lengths and keeps wiring delay low. However, there are many barriers to practical implementation of 3D stacked chips. These include:
It is highly desirable to circumvent these issues and build 3D stacked semiconductor chips with a high-density of connections between layers. To achieve this goal, it is sufficient that one of three requirements must be met: (1) A technology to construct high-performance transistors with processing temperatures below ˜400° C.; (2) A technology where standard transistors are fabricated in a pattern, which allows for high density connectivity despite the misalignment between the two bonded wafers; and (3) A chip architecture where process temperature increase beyond 400° C. for the transistors in the top layer does not degrade the characteristics or reliability of the bottom transistors and wiring appreciably. This patent application describes approaches to address options (1), (2) and (3) in the detailed description section. In the rest of this section, background art that has previously tried to address options (1), (2) and (3) will be described.
U.S. Pat. No. 7,052,941 from Sang-Yun Lee (“S-Y Lee”) describes methods to construct vertical transistors above wiring layers at less than 400° C. In these single crystal Si transistors, current flow in the transistor's channel region is in the vertical direction. Unfortunately, however, almost all semiconductor devices in the market today (logic, DRAM, flash memory) utilize horizontal (or planar) transistors due to their many advantages, and it is difficult to convince the industry to move to vertical transistor technology.
A paper from IBM at the Intl. Electron Devices Meeting in 2005 describes a method to construct transistors for the top stacked layer of a 2 chip 3D stack on a separate wafer. This paper is “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM Tech. Digest, p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L. Shi, et al. (“Topol”). A process flow is utilized to transfer this top transistor layer atop the bottom wiring and transistor layers at temperatures less than 400° C. Unfortunately, since transistors are fully formed prior to bonding, this scheme suffers from misalignment issues. While Topol describes techniques to reduce misalignment errors in the above paper, the techniques of Topol still suffer from misalignment errors that limit contact dimensions between two chips in the stack to >130 nm.
The textbook “Integrated Interconnect Technologies for 3D Nanoelectronic Systems” by Bakir and Meindl (“Bakir”) describes a 3D stacked DRAM concept with horizontal (i.e. planar) transistors. Silicon for stacked transistors is produced using selective epitaxy technology or laser recrystallization. Unfortunately, however, these technologies have higher defect density compared to standard single crystal silicon. This higher defect density degrades transistor performance.
In the NAND flash memory industry, several organizations have attempted to construct 3D stacked memory. These attempts predominantly use transistors constructed with poly-Si or selective epi technology as well as charge-trap concepts. References that describe these attempts to 3D stacked memory include “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”), “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symp. VLSI Technology Tech. Dig. pp. 14-15, 2007 by H. Tanaka, M. Kido, K. Yahashi, et al. (“Tanaka”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by W. Kim, S. Choi, et al. (“W. Kim”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. (“Lue”) and “Sub-50 nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, pp. 2703-2710, November 2009 by A. J. Walker (“Walker”). An architecture and technology that utilizes single crystal Silicon using epi growth is described in “A Stacked SONOS Technology, Up to 4 Levels and 6 nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009 by A. Hubert, et al (“Hubert”). However, the approach described by Hubert has some challenges including use of difficult-to-manufacture nanowire transistors, higher defect densities due to formation of Si and SiGe layers atop each other, high temperature processing for long times, difficult manufacturing, etc.
It is clear based on the background art mentioned above that invention of novel technologies for 3D stacked chips will be useful.
In one aspect, a device with semiconductor memories includes a first layer and a second layer of mono-crystallized silicon, wherein said first layer comprises a first plurality of horizontally-oriented transistors; wherein said second layer comprises a second plurality of horizontally-oriented transistors; wherein said first layer further comprises a first plurality of select lines as memory cell control lines, and wherein said second layer further comprises a second plurality of select lines as memory cell control lines.
In another aspect, a semiconductor device includes a first layer and a second layer of mono-crystallized silicon, wherein said first layer comprises plurality of first transistors; wherein said second layer comprises plurality of second transistors; and wherein said first transistors and said second transistors have at least one feature processed on both following lithography.
In yet another aspect, a semiconductor device includes a first layer and a second layer of layer-transferred silicon, wherein said first layer comprises a first plurality of horizontally-oriented transistors; wherein said second layer comprises a second plurality of horizontally-oriented transistors; and wherein said second plurality of horizontally-oriented transistors overlie said first plurality of horizontally-oriented transistors.
Advantages of the preferred embodiments may include one or more of the following. The system is easy to manufacture. The defect density is low, and the resulting 3D stacked chips offer high density storage capabilities.
Embodiments of the present invention are now described with reference to
Section 1: Construction of 3D Stacked Semiconductor Circuits and Chips with Processing Temperatures Below 400° C.
This section of the document describes a technology to construct single-crystal silicon transistors atop wiring layers with less than 400° C. processing temperatures. This allows construction of 3D stacked semiconductor chips with high density of connections between different layers, because the top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are very thin (preferably less than 200 nm), alignment can be done through these thin silicon and oxide layers to features in the bottom-level.
Step (A): A silicon dioxide layer 0204 is deposited above the generic bottom layer 0202.
Step (B): The top layer of doped or undoped silicon 206 to be transferred atop the bottom layer is processed and an oxide layer 0208 is deposited or grown above it.
Step (C): Hydrogen is implanted into the top layer silicon 0206 with the peak at a certain depth to create the plane 0210. Alternatively, another atomic species such as helium or boron can be implanted or co-implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 0210 using an anneal. Alternatively, a sideways mechanical force may be used. Further details of this cleave process are described in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S. Cristoloveanu (“Celler”) and “Mechanically induced Si layer transfer in hydrogen-implanted Si wafers,” Appl. Phys. Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni, and S. S. Lau (“Hentinnen”). Following this, a Chemical-Mechanical-Polish (CMP) is done.
A possible flow for constructing 3D stacked semiconductor chips with standard transistors is shown in
Step (A): The bottom wafer of the 3D stack is processed with a bottom transistor layer 0306 and a bottom wiring layer 0304. A silicon dioxide layer 0302 is deposited above the bottom transistor layer 0306 and the bottom wiring layer 0304.
Step (B): Using a procedure similar to
Step (C) Isolation regions (between adjacent transistors) on the top wafer are formed using a standard shallow trench isolation (STI) process. After this, a gate dielectric 0318 and a gate electrode 0316 are deposited, patterned and etched.
Step (D): Source 0320 and drain 0322 regions are ion implanted.
Step (E): The top layer of transistors is annealed at high temperatures, typically in between 700° C. and 1200° C. This is done to activate dopants in implanted regions. Following this, contacts are made and further processing occurs.
The challenge with following this flow to construct 3D integrated circuits with aluminum or copper wiring is apparent from
Section 1.1: Junction-Less Transistors as a Building Block for 3D Stacked Chips
One method to solve the issue of high-temperature source-drain junction processing is to make transistors without junctions i.e. Junction-Less Transistors (JLTs). An embodiment of this invention uses JLTs as a building block for 3D stacked semiconductor circuits and chips.
Step (A): The bottom layer of the 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 502. Above this, a silicon dioxide layer 504 is deposited.
Step (B): A layer of n+ Si 506 is transferred atop the structure shown after Step (A). It starts by taking a donor wafer which is already n+ doped and activated. Alternatively, the process can start by implanting a silicon wafer and activating at high temperature forming an n+ activated layer. Then, H+ ions are implanted for ion-cut within the n+ layer. Following this, a layer-transfer is performed. The process as shown in
Step (C): Using lithography (litho) and etch, the n+ Si layer is defined and is present only in regions where transistors are to be constructed. These transistors are aligned to the underlying alignment marks embedded in bottom layer 502.
Step (D): The gate dielectric material 510 and the gate electrode material 508 are deposited, following which a CMP process is utilized for planarization. The gate dielectric material 510 could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.
Step (E): Litho and etch are conducted to leave the gate dielectric material and the gate electrode material only in regions where gates are to be formed.
Step (F): An oxide layer is deposited and polished with CMP. This oxide region serves to isolate adjacent transistors. Following this, rest of the process flow continues, where contact and wiring layers could be formed.
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in
Step (A): The bottom layer of the two chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 702. Above this, a silicon dioxide layer 704 is deposited.
Step (B): A layer of n+ Si 706 is transferred atop the structure shown after Step (A). The process shown in
Step (C): Using lithography (litho) and etch, the n+ Si layer 706 is defined and is present only in regions where transistors are to be constructed. An oxide 705 is deposited (for isolation purposes) with a standard shallow-trench-isolation process. The n+ Si structure remaining after Step (C) is indicated as n+ Si 707.
Step (D): The gate dielectric material 708 and the gate electrode material 710 are deposited. The gate dielectric material 708 could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.
Step (E): Litho and etch are conducted to leave the gate dielectric material 708 and the gate electrode material 710 only in regions where gates are to be formed. It is clear based on the schematic that the gate is present on just one side of the JLT. Structures remaining after Step (E) are gate dielectric 709 and gate electrode 711.
Step (F): An oxide layer 713 is deposited and polished with CMP.
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in
Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 802. Above this, a silicon dioxide layer 804 is deposited.
Step (B): A layer of n+ Si 806 is transferred atop the structure shown after Step (A). The process shown in
Step (C): Using lithography (litho) and etch, the nitride layer 808 and n+ Si layer 806 are defined and are present only in regions where transistors are to be constructed. The nitride and n+ Si structures remaining after Step (C) are indicated as nitride hard mask 809 and n+ Si 807.
Step (D): The gate dielectric material 810 and the gate electrode material 808 are deposited. The gate dielectric material 810 could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.
Step (E): Litho and etch are conducted to leave the gate dielectric material 810 and the gate electrode material 808 only in regions where gates are to be formed. Structures remaining after Step (E) are gate dielectric 811 and gate electrode 809.
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in
Step (A): On a p− Si wafer 902, multiple n+ Si layers 904 and 908 and multiple n+ SiGe layers 906 and 910 are epitaxially grown. The Si and SiGe layers are carefully engineered in terms of thickness and stoichiometry to keep defect density due to lattice mismatch between Si and SiGe low. Some techniques for achieving this include keeping thickness of SiGe layers below the critical thickness for forming defects. A silicon dioxide layer 912 is deposited above the stack.
Step (B): Hydrogen is implanted at a certain depth in the p− wafer, to form a cleave plane 920 after bonding to bottom wafer of the two-chip stack. Alternatively, some other atomic species such as He can be used.
Step (C): The structure after Step (B) is flipped and bonded to another wafer on which bottom layers of transistors and wires 914 are constructed. Bonding occurs with an oxide-to-oxide bonding process.
Step (D): A cleave process occurs at the hydrogen plane using a sideways mechanical force. Alternatively, an anneal could be used for cleaving purposes. A CMP process is conducted till one reaches the n+ Si layer 904.
Step (E): Using litho and etch, Si 918 and SiGe 916 regions are defined to be in locations where transistors are required. Oxide 920 is deposited to form isolation regions and to cover the Si/SiGe regions 916 and 918. A CMP process is conducted.
Step (F): Using litho and etch, Oxide regions 920 are removed in locations where a gate needs to be present. It is clear that Si regions 918 and SiGe regions 916 are exposed in the channel region of the JLT.
Step (G): SiGe regions 916 in channel of the JLT are etched using an etching recipe that does not attack Si regions 918. Such etching recipes are described in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” in Proc. IEDM Tech. Dig., 2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”).
Step (H): This is an optional step where a hydrogen anneal can be utilized to reduce surface roughness of fabricated nanowires. The hydrogen anneal can also reduce thickness of nanowires. Following the hydrogen anneal, another optional step of oxidation (using plasma enhanced thermal oxidation) and etch-back of the produced silicon dioxide can be used. This process thins down the silicon nanowire further.
Step (I): Gate dielectric and gate electrode regions are deposited or grown. Examples of gate dielectrics include hafnium oxide, silicon dioxide, etc. Examples of gate electrodes include polysilicon, TiN, TaN, etc. A CMP is conducted after gate electrode deposition. Following this, rest of the process flow for forming transistors, contacts and wires for the top layer continues.
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are very thin (preferably less than 200 nm), the top transistors can be aligned to features in the bottom-level. While the process flow shown in
Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 950. Above this, a silicon dioxide layer 952 is deposited.
Step (B): A n+ Si wafer 954 that has its dopants activated is now taken. Alternatively, a p− Si wafer that has n+ dopants implanted and activated can be used.
Step (C): Hydrogen ions are implanted into the n+ Si wafer 954 at a certain depth.
Step (D): The wafer after step (C) is bonded to a temporary carrier wafer 960 using a temporary bonding adhesive 958. This temporary carrier wafer 960 could be constructed of glass. Alternatively, it could be constructed of silicon. The temporary bonding adhesive 958 could be a polymer material, such as a polyimide.
Step (E): A anneal or a sideways mechanical force is utilized to cleave the wafer at the hydrogen plane 954. A CMP process is then conducted.
Step (F): Layers of gate dielectric material 966, gate electrode material 968 and silicon oxide 964 are deposited onto the bottom of the wafer shown in Step (E).
Step (G): The wafer is then bonded to the bottom layer of wires and transistors 950 using oxide-to-oxide bonding.
Step (H): The temporary carrier wafer 960 is then removed by shining a laser onto the temporary bonding adhesive 958 through the temporary carrier wafer 960 (which could be constructed of glass). Alternatively, an anneal could be used to remove the temporary bonding adhesive 958.
Step (I): The layer of n+ Si 962 and gate dielectric material 966 are patterned and etched using a lithography and etch step.
Step (J): The oxide layer 974 and gate electrode material 968 are patterned and etched to form a region of silicon dioxide 978 and back gate electrode 976.
Step (K): A silicon dioxide layer is deposited. The surface is then planarized with CMP to form the region of silicon dioxide 982.
Step (L): Trenches are etched in the region of silicon dioxide 982. A thin layer of gate dielectric and a thicker layer of gate electrode are then deposited and planarized. Following this, a lithography and etch step are performed to etch the gate dielectric and gate electrode.
All the types of embodiments of this invention described in Section 1.1 utilize single crystal silicon or monocrystalline silicon transistors. Thicknesses of layer transferred regions of silicon are <2 um, and many times can be <1 um or <0.4 um or even <0.2 um. Interconnect (wiring) layers are preferably constructed substantially of copper or aluminum or some other high conductivity material.
Section 1.2: Recessed Channel Transistors as a Building Block for 3D Stacked Circuits and Chips
Another method to solve the issue of high-temperature source-drain junction processing is an innovative use of recessed channel inversion-mode transistors as a building block for 3D stacked semiconductor circuits and chips. The transistor structures described in this section can be considered horizontally-oriented transistors where current flow occurs between horizontally-oriented source and drain regions. The term planar transistor can also be used for the same in this document. The recessed channel transistors in this section are defined by a process including a step of etch to form the transistor channel. 3D stacked semiconductor circuits and chips using recessed channel transistors preferably have interconnect (wiring) layers including copper or aluminum or a material with higher conductivity.
Step (A): A silicon dioxide layer 1104 is deposited above the generic bottom layer 1102.
Step (B): A wafer of p-Si 1106 is implanted with n+ near its surface to form a layer of n+ Si 1108.
Step (C): A layer of p− Si 1110 is epitaxially grown atop the layer of n+ Si 1108. A layer of silicon dioxide 1112 is deposited atop the layer of p− Si 1110. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants. Note that the terms laser anneal and optical anneal are used interchangeably in this document.
Step (D): Hydrogen H+ is implanted into the n+ Si layer 1108 at a certain depth 1114. Alternatively, another atomic species such as helium can be implanted.
Step (E): The top layer wafer shown after Step (D) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (F): A cleave operation is performed at the hydrogen plane 1114 using an anneal. Alternatively, a sideways mechanical force may be used. Following this, a Chemical-Mechanical-Polish (CMP) is done. It should be noted that the layer-transfer including the bonding and the cleaving could be done without exceeding 400° C. This is the case in various alternatives of this invention.
Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 1202. Above this, a silicon dioxide layer 1204 is deposited.
Step (B): Using the procedure shown in
Step (C): The stack shown after Step (A) is patterned lithographically and etched such that silicon regions are present only in regions where transistors are to be formed. Using a standard shallow trench isolation (STI) process, isolation regions in between transistor regions are formed. These oxide regions are indicated as 1216.
Step (D): Using litho and etch, a recessed channel is formed by etching away the n+ Si region 1209 where gates need to be formed. Little or none of the p− Si region 1206 is removed.
Step (E): The gate dielectric material and the gate electrode material are deposited, following which a CMP process is utilized for planarization. The gate dielectric material could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used. Litho and etch are conducted to leave the gate dielectric material 1210 and the gate electrode material 1212 only in regions where gates are to be formed.
Step (F): An oxide layer 1214 is deposited and polished with CMP. Following this, rest of the process flow continues, with contact and wiring layers being formed.
It is apparent based on the process flow shown in
Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires 1302. Above this, a silicon dioxide layer 1304 is deposited.
Step (B): Using the procedure shown in
Step (C): The stack shown after Step (A) is patterned lithographically and etched such that silicon regions are present only in regions where transistors are to be formed. Using a standard shallow trench isolation (STI) process, isolation regions in between transistor regions are formed.
Step (D): Using litho and etch, a recessed channel is formed by etching away the n+ Si region 1308 and p− Si region 1306 where gates need to be formed. A chemical dry etch process is described in “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond,” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, vol., no., pp. 11-12, 10-12 Jun. 2003 by Kim, J. Y.; Lee, C. S.; Kim, S. E., et al. (“J. Y. Kim”). A variation of this process from J. Y. Kim can be utilized for rounding corners, removing damaged silicon, etc after the etch. Furthermore, Silicon Dioxide can be formed using a plasma-enhanced thermal oxidation process, this oxide can be etched-back as well to reduce damage from etching silicon.
Step (E): The gate dielectric material and the gate electrode material are deposited, following which a CMP process is utilized for planarization. The gate dielectric material could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used. Litho and etch are conducted to leave the gate dielectric material 1310 and the gate electrode material 1312 only in regions where gates are to be formed.
Step (F): An oxide layer 1320 is deposited and polished with CMP. Following this, rest of the process flow continues, with contact and wiring layers being formed.
It is apparent based on the process flow shown in
While
The recessed channel Finfet shown in
Section 1.3: Improvements and Alternatives
Various methods, technologies and procedures to improve devices shown in Section 1.1 and Section 1.2 are given in this section. Single crystal silicon (this term used interchangeably with monocrystalline silicon) is used for constructing transistors in Section 1.3. Thickness of layer transferred silicon is typically <2 um or <1 um or could be even less than 0.2 um, unless stated otherwise. Interconnect (wiring) layers are constructed substantially of copper or aluminum or some other higher conductivity material. The term planar transistor or horizontally oriented transistor could be used to describe any constructed transistor where source and drain regions are in the same horizontal plane and current flows between them.
Section 1.3.1: Construction of CMOS Circuits with Sub-400° C. Processed Transistors
Step (1): A bottom layer of transistors and wires 1414 is first constructed above which a layer of landing pads 1418 is constructed. A layer of silicon dioxide 1416 is then constructed atop the layer of landing pads 1418. Size of the landing pads 1418 is Wx+delta (Wx) in the X direction, where Wx is the distance of one repeat of the repeating pattern in the (to be constructed) top layer. delta(Wx) is an offset added to account for some overlap into the adjacent region of the repeating pattern and some margin for rotational (angular) misalignment within one chip (IC). Size of the landing pads 1418 is F or 2 F plus a margin for rotational misalignment within one chip (IC) or higher in the Y direction, where F is the minimum feature size. Note that the terms landing pad and metal strip are used interchangeably in this document.
Step (2): A top layer having regions of n+ Si 1424 and p+ Si 1422 repeating over-and-over again is constructed atop a p− Si wafer 1420. The pattern repeats in the X direction with a repeat distance denoted by Wx. In the Y direction, there is no pattern at all; the wafer is completely uniform in that direction. This ensures misalignment in the Y direction does not impact device and circuit construction, except for any rotational misalignment causing difference between the left and right side of one IC. A maximum rotational (angular) misalignment of 0.5 um over a 200 mm wafer results in maximum misalignment within one 10 by 10 mm IC of 25 nm in both X and Y direction. Total misalignment in the X direction is much larger, which is addressed in this invention as shown in the following steps.
Step (3): The top layer shown in Step (2) receives an H+ implant to create the cleaving plane in the p− silicon region and is flipped and bonded atop the bottom layer shown in Step (1). A procedure similar to the one shown in
Since the width of the landing pads is slightly wider than the width of the repeating n and p pattern in the X-direction and there's no pattern in the Y direction, the circuitry in the top layer can shifted left or right and up or down until the layer-to-layer contacts within the top circuitry are placed on top of the appropriate landing pad. This is further explained below:
Let us assume that after the bonding process, co-ordinates of alignment mark of the top wafer are (xtop, ytop) while co-ordinates of alignment mark of the bottom wafer are (xbottom, ybottom).
Step (4): A virtual alignment mark is created by the lithography tool. X co-ordinate of this virtual alignment mark is at the location (xtop+(an integer k)*Wx). The integer k is chosen such that modulus or absolute value of (xtop+(integer k)*Wx−xbottom)<=Wx/2. This guarantees that the X co-ordinate of the virtual alignment mark is within a repeat distance (or within the same section of width Wx) of the X alignment mark of the bottom wafer. Y co-ordinate of this virtual alignment mark is ybottom (since silicon thickness of the top layer is thin, the lithography tool can see the alignment mark of the bottom wafer and compute this quantity). Though-silicon connections 1428 are now constructed with alignment mark of this mask aligned to the virtual alignment mark. The terms through via or through silicon vias can be used interchangeably with the term through-silicon connections in this document. Since the X co-ordinate of the virtual alignment mark is within the same ((p+)-oxide-(n+)-oxide) repeating pattern (of length Wx) as the bottom wafer X alignment mark, the through-silicon connection 1428 always falls on the bottom landing pad 1418 (the bottom landing pad length is Wx added to delta (Wx), and this spans the entire length of the repeating pattern in the X direction).
Step (5): n channel and p channel junctionless transistors are constructed aligned to the virtual alignment mark.
From steps (1) to (5), it is clear that 3D stacked semiconductor circuits and chips can be constructed with misalignment tolerance techniques. Essentially, a combination of 3 key ideas—repeating patterns in one direction of length Wx, landing pads of length (Wx+delta (Wx)) and creation of virtual alignment marks—are used such that even if misalignment occurs, through silicon connections fall on their respective landing pads. While the explanation in
Step (A): A bottom wafer 1438 is processed with a bottom transistor layer 1436 and a bottom wiring layer 1434. A layer of silicon oxide 1430 is deposited above it.
Step (B): Using a procedure similar to
Step (C): p-channel junctionless transistors 1450 of the CMOS circuit can be formed on the p+ Si layer 1448 with standard procedures. For n-channel junction-less transistors 1452 of the CMOS circuit, one needs to etch through the p+ layer 1448 to reach the n+ Si layer 1444. Transistors are then constructed on the n+ Si 1444. Due to depth-of-focus issues associated with lithography, one requires separate lithography steps while constructing different parts of re-channel and p-channel transistors.
Section 1.3.2: Accurate Transfer of Thin Layers of Silicon with Ion-Cut
It is often desirable to transfer very thin layers of silicon (<100 nm) atop a bottom layer of transistors and wires using the ion-cut technique. For example, for the process flow in
Step (A): A silicon dioxide layer 1504 is deposited above the generic bottom layer 1502.
Step (B): An SOI wafer 1506 is implanted with n+ near its surface to form a n+ Si layer 1508. The buried oxide (BOX) of the SOI wafer is silicon dioxide 1505.
Step (C): A p− Si layer 1510 is epitaxially grown atop the n+ Si layer 1508. A silicon dioxide layer 1512 is deposited atop the p− Si layer 1510. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.
Alternatively, the n+ Si layer 1508 and p− Si layer 1510 can be formed by a buried layer implant of n+ Si in a p− SOI wafer.
Hydrogen is then implanted into the p− Si layer 1506 at a certain depth 1514. Alternatively, another atomic species such as helium can be implanted or co-implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 1514 using an anneal. Alternatively, a sideways mechanical force may be used. Following this, an etching process that etches Si but does not etch silicon dioxide is utilized to remove the p− Si layer 1506 remaining after cleave. The buried oxide (BOX) 1505 acts as an etch stop.
Step (F): Once the etch stop 1505 is reached, an etch or CMP process is utilized to etch the silicon dioxide layer 1505 till the n+ silicon layer 1508 is reached. The etch process for Step (F) is preferentially chosen so that it etches silicon dioxide but does not attack Silicon.
It is clear from the process shown in
While the process shown in
Step (A): A silicon dioxide layer 1604 is deposited above the generic bottom layer 1602.
Step (B): A n− Si wafer 1606 is implanted with boron doped p+ Si near its surface to form a p+ Si layer 1605. The p+ layer is doped above 1E20/cm3, and preferably above 1E21/cm3. It may be possible to use a p− Si layer instead of the p+ Si layer 1605 as well, and still achieve similar results. A p− Si wafer can be utilized instead of the n− Si wafer 1606 as well.
Step (C): A n+ Si layer 1608 and a p− Si layer 1610 are epitaxially grown atop the p+ Si layer 1605. A silicon dioxide layer 1612 is deposited atop the p− Si layer 1610. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants. Alternatively, the p+ Si layer 1605, the n+ Si layer 1608 and the p− Si layer 1610 can be formed by a series of implants on a n− Si wafer 1606.
Hydrogen is then implanted into the p− Si layer 1606 at a certain depth 1614. Alternatively, another atomic species such as helium can be implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 1614 using an anneal. Alternatively, a sideways mechanical force may be used. Following this, an etching process that etches the n− Si layer 1606 but does not etch the p+ Si etch stop layer 1605 is utilized to etch through the n− Si layer 1606 remaining after cleave. Examples of etching agents that etch n− Si or p− Si but do not attack p+ Si doped above 1E20/cm3 include KOH, EDP (ethylenediamine/pyrocatechol/water) and hydrazine.
Step (F): Once the etch stop 1605 is reached, an etch or CMP process is utilized to etch the p+ Si layer 1605 till the n+ silicon layer 1608 is reached.
It is clear from the process shown in
While silicon dioxide and p+ Si were utilized as etch stop layers in
Section 1.3.3: Alternative Low-Temperature (Sub-300° C.) Ion-Cut Process for Sub-400° C. Processed Transistors
An alternative low-temperature ion-cut process is described in
Step (A): A silicon dioxide layer 1704 is deposited above the generic bottom layer 1702.
Step (B): A p− Si wafer 1706 is implanted with boron doped p+ Si near its surface to form a p+ Si layer 1705. A n− Si wafer can be utilized instead of the p− Si wafer 1606 as well.
Step (C): A n+ Si layer 1708 and a p− Si layer 1710 are epitaxially grown atop the p+ Si layer 1705. A silicon dioxide layer 1712 is grown or deposited atop the p− Si layer 1710. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.
Alternatively, the p+ Si layer 1705, the n+ Si layer 1708 and the p− Si layer 1710 can be formed by a series of implants on a p− Si wafer 1706.
Hydrogen is then implanted into the p− Si layer 1706 at a certain depth 1714. Alternatively, another atomic species such as helium can be (co-)implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 1714 using a sub-300° C. anneal. Alternatively, a sideways mechanical force may be used. An etch or CMP process is utilized to etch the p+ Si layer 1705 till the n+ silicon layer 1708 is reached.
The purpose of hydrogen implantation into the p+ Si region 1705 is because p+ regions heavily doped with boron are known to require lower anneal temperature required for ion-cut. Further details of this technology/process are given in “Cold ion-cutting of hydrogen implanted Si, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms”, Volume 190, Issues 1-4, May 2002, Pages 761-766, ISSN 0168-583X by K. Henttinen, T. Suni, A. Nurmela, et al. (“Hentinnen and Suni”). The contents of these publications are incorporated herein by reference.
Section 1.3.4: Alternative Procedures for Layer Transfer
While ion-cut has been described in previous sections as the method for layer transfer, several other procedures exist that fulfill the same objective. These include:
Lift-off or laser lift-off: Background information for this technology is given in “Epitaxial lift-off and its applications”, 1993 Semicond. Sci. Technol. 8 1124 by P Demeester et al. (“Demeester”).
Porous-Si approaches such as ELTRAN: Background information for this technology is given in “Eltran, Novel SOI Wafer Technology”, JSAP International, Number 4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”) and also in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978, 2003 by G. K. Celler and S. Cristoloveanu (“Celler”).
Time-controlled etch-back to thin an initial substrate, Polishing, Etch-stop layer controlled etch-back to thin an initial substrate: Background information on these technologies is given in Celler and in U.S. Pat. No. 6,806,171.
Rubber-stamp based layer transfer: Background information on this technology is given in “Solar cells sliced and diced”, 19 May 2010, Nature News.
The above publications giving background information on various layer transfer procedures are incorporated herein by reference. It is obvious to one skilled in the art that one can form 3D integrated circuits and chips as described in this document with layer transfer schemes described in these publications.
Step (A): A silicon dioxide layer 1804 is deposited above the generic bottom layer 1802.
Step (B): A SOI wafer 1806 is implanted with n+ near its surface to form a n+ Si layer 1808. The buried oxide (BOX) of the SOI wafer is silicon dioxide 1805.
Step (C): A p− Si layer 1810 is epitaxially grown atop the n+ Si layer 1808. A silicon dioxide layer 1812 is grown/deposited atop the p− Si layer 1810. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.
Alternatively, the n+ Si layer 1808 and p− Si layer 1810 can be formed by a buried layer implant of n+ Si in a p− SOI wafer.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): An etch process that etches Si but does not etch silicon dioxide is utilized to etch through the p− Si layer 1806. The buried oxide (BOX) of silicon dioxide 1805 therefore acts as an etch stop.
Step (F): Once the etch stop 1805 is reached, an etch or CMP process is utilized to etch the silicon dioxide layer 1805 till the n+ silicon layer 1808 is reached. The etch process for Step (F) is preferentially chosen so that it etches silicon dioxide but does not attack Silicon.
At the end of the process shown in
Step (A): A silicon dioxide layer 2004 is deposited above the generic bottom layer 2002.
Step (B): The layer to be transferred atop the bottom layer (top layer of doped germanium or III-V semiconductor 2006) is processed and a compatible oxide layer 2008 is deposited above it.
Step (C): Hydrogen is implanted into the Top layer doped Germanium or III-V semiconductor 2006 at a certain depth 2010. Alternatively, another atomic species such as helium can be (co-) implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 2010 using an anneal or a mechanical force. Following this, a Chemical-Mechanical-Polish (CMP) is done.
Section 1.3.5: Laser Anneal Procedure for 3D Stacked Components and Chips
Step (A): The bottom wafer 2112 is processed with transistor and wiring layers. The top wafer may include a layer of silicon 2110 with an oxide layer above it. The thickness of the silicon layer 2110, t, is typically >50 um.
Step (B): The top wafer 2114 is flipped and bonded to the bottom wafer 2112. It can be readily seen that the thickness of the top layer is >50 um. Due to this high thickness, and due to the fact that the aspect ratio (height to width ratio) of through-silicon connections is limited to <100:1, it can be seen that the minimum width of through-silicon connections possible with this procedure is 50 um/100=500 nm. This is much higher than dimensions of horizontal wiring on a chip.
Step (C): Transistors are then built on the top wafer 2114 and a laser anneal is utilized to activate dopants in the top silicon layer. Due to the characteristics of a laser anneal, the temperature in the top layer 2114 will be much higher than the temperature in the bottom layer 2112.
An alternative procedure described in prior art is the SOI-based layer transfer (shown in
An alternative procedure for laser anneal of layer transferred silicon is shown in
Step (A): A bottom wafer 2212 is processed with transistor, wiring and silicon dioxide layers.
Step (B): A top layer of silicon 2210 is layer transferred atop it using procedures similar to
Step (C): Transistors are formed on the top layer of silicon 2210 and a laser anneal is done to activate dopants in source-drain regions 2216. Fabrication of the rest of the integrated circuit flow including contacts and wiring layers may then proceed.
Most of the figures described thus far in this document assumed the transferred top layer of silicon is very thin (preferably <200 nm). This enables light to penetrate the silicon and allows features on the bottom wafer to be observed. However, that is not always the case.
Step (A): A bottom wafer 2312 is processed to form a bottom transistor layer 2306 and a bottom wiring layer 2304. A layer of silicon oxide 2302 is deposited above it.
Step (B): A wafer of p− Si 2310 has an oxide layer 2306 deposited or grown above it. Using lithography, a window pattern is etched into the p− Si 2310 and is filled with oxide. A step of CMP is done. This window pattern will be used in Step (C) to allow light to penetrate through the top layer of silicon to align to circuits on the bottom wafer 2312. The window size is chosen based on misalignment tolerance of the alignment scheme used while bonding the top wafer to the bottom wafer in Step (C). Furthermore, some alignment marks also exist in the wafer of p− Si 2310.
Step (C): A portion of the p− Si 2310 from Step (B) is transferred atop the bottom wafer 2312 using procedures similar to
Additionally, when circuit cells are built on two or more layers of thin silicon, and enjoy the dense vertical through silicon via interconnections, the metallization layer scheme to take advantage of this dense 3D technology may be improved as follows.
The metallization layer scheme may be improved for 3D circuits as illustrated in
Section 2: Construction of 3D Stacked Semiconductor Circuits and Chips where Replacement Gate High-K/Metal Gate Transistors can be Used. Misalignment-Tolerance Techniques are Utilized to Get High Density of Connections.
Section 1 described the formation of 3D stacked semiconductor circuits and chips with sub-400° C. processing temperatures to build transistors and high density of vertical connections. In this section an alternative method is explained, in which a transistor is built with any replacement gate (or gate-last) scheme that is utilized widely in the industry. This method allows for high temperatures (above 400 C) to build the transistors. This method utilizes a combination of three concepts:
The method mentioned in the previous paragraph is described in
Step (A): After creating isolation regions using a shallow-trench-isolation (STI) process 2504, dummy gates 2502 are constructed with silicon dioxide and poly silicon. The term “dummy gates” is used since these gates will be replaced by high k gate dielectrics and metal gates later in the process flow, according to the standard replacement gate (or gate-last) process. Further details of replacement gate processes are described in “A 45 nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging,” IEDM Tech. Dig., pp. 247-250, 2007 by K. Mistry, et al. and “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization,” IEDM Tech. Dig., pp. 663-666, 2009 by L. Ragnarsson, et al.
Step (B): Rest of the transistor fabrication flow proceeds with formation of source-drain regions 2506, strain enhancement layers to improve mobility, high temperature anneal to activate source-drain regions 2506, formation of inter-layer dielectric (ILD) 2508, etc.
Step (C): Hydrogen is implanted into the wafer at the dotted line regions indicated by 2510.
Step (D): The wafer after step (C) is bonded to a temporary carrier wafer 2512 using a temporary bonding adhesive 2514. This temporary carrier wafer 2512 could be constructed of glass. Alternatively, it could be constructed of silicon. The temporary bonding adhesive 2514 could be a polymer material, such as a polyimide. A anneal or a sideways mechanical force is utilized to cleave the wafer at the hydrogen plane 2510. A CMP process is then conducted.
Step (E): An oxide layer is deposited onto the bottom of the wafer shown in Step (D). The wafer is then bonded to the bottom layer of wires and transistors 2522 using oxide-to-oxide bonding. The bottom layer of wires and transistors 2522 could also be called a base wafer. The temporary carrier wafer 2512 is then removed by shining a laser onto the temporary bonding adhesive 2514 through the temporary carrier wafer 2512 (which could be constructed of glass). Alternatively, an anneal could be used to remove the temporary bonding adhesive 2514. Through-silicon connections 2516 with a non-conducting (e.g. oxide) liner 2515 to the landing pads 2518 in the base wafer could be constructed at a very high density using special alignment methods to be described in
Step (F): Dummy gates 2502 are etched away, followed by the construction of a replacement with high k gate dielectrics 2524 and metal gates 2526. Essentially, partially-formed high performance transistors are layer transferred atop the base wafer (may also be called target wafer) followed by the completion of the transistor processing with a low (sub 400° C.) process.
It will be obvious to someone skilled in the art that alternative versions of this flow are possible with various methods to attach temporary carriers and with various versions of the gate-last process flow.
After bonding the top and bottom wafers atop each other as described in
Next step in the process is described with
After bonding the top and bottom wafers atop each other as described in
The alignment scheme shown in
Step (A): Using procedures similar to
Step (B): Through-silicon connections 4412 are formed well-aligned to the bottom layer of transistors and wires 4402. Alignment schemes to be described in
Step (C): Oxide isolation regions 4414 are formed between adjacent transistors to be defined. These isolation regions are formed by lithography and etch of gate and silicon regions and then fill with oxide.
Step (D): The dummy gates 4408 and 4410 are etched away and replaced with replacement gates 4416 and 4418. These replacement gates are patterned and defined to form gate contacts as well.
After bonding the top and bottom wafers atop each other as described in
An interesting alternative is available when using the carrier wafer flow described in
Another alternative is illustrated in
Using procedures similar to
Section 3: Monolithic 3D DRAM.
While Section 1 and Section 2 describe applications of monolithic 3D integration to logic circuits and chips, this Section describes novel monolithic 3D Dynamic Random Access Memories (DRAMs). Some embodiments of this invention may involve floating body DRAM. Background information on floating body DRAM and its operation is given in “Floating Body RAM Technology and its Scalability to 32 nm Node and Beyond,” Electron Devices Meeting, 2006. IEDM '06. International, vol., no., pp. 1-4, 11-13 Dec. 2006 by T. Shino, N. Kusunoki, T. Higashi, et al., Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond, Solid-State Electronics, Volume 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research Conference—ESSDERC '08, July 2009, Pages 676-683, ISSN 0038-1101, DOI: 10.1016/j.sse.2009.03.010 by Takeshi Hamamoto, Takashi Ohsawa, et al., “New Generation of Z-RAM,” Electron Devices Meeting, 2007. IEDM 2007. IEEE International, vol., no., pp. 925-928, 10-12 Dec. 2007 by Okhonin, S.; Nagoga, M.; Carman, E, et al. The above publications are incorporated herein by reference.
Step (A): A p− Silicon wafer 2901 is taken and an oxide layer 2902 is grown or deposited above it.
Step (B): Hydrogen is implanted into the p− wafer 2901 at a certain depth denoted by 2903.
Step (C): The wafer after Step (B) is flipped and bonded onto a wafer having peripheral circuits 2904 covered with oxide. This bonding process occurs using oxide-to-oxide bonding. The stack is then cleaved at the hydrogen implant plane 2903 using either an anneal or a sideways mechanical force. A chemical mechanical polish (CMP) process is then conducted. Note that peripheral circuits 2904 are such that they can withstand an additional rapid-thermal-anneal (RTA) and still remain operational, and preferably retain good performance. For this purpose, the peripheral circuits 2904 may be such that they have not had their RTA for activating dopants or they have had a weak RTA for activating dopants. Also, peripheral circuits 2904 utilize a refractory metal such as tungsten that can withstand high temperatures greater than 400° C.
Step (D): The transferred layer of p− silicon after Step (C) is then processed to form isolation regions using a STI process. Following, gate regions 2905 are deposited and patterned, following which source-drain regions 2908 are implanted using a self-aligned process. An inter-level dielectric (ILD) constructed of oxide (silicon dioxide) 2906 is then constructed. Note that no RTA is done to activate dopants in this layer of partially-depleted SOI (PD-SOI) transistors. Alternatively, transistors could be of fully-depleted SOI type.
Step (E): Using steps similar to Step (A)-Step (D), another layer of memory 2909 is constructed. After all the desired memory layers are constructed, a RTA is conducted to activate dopants in all layers of memory (and potentially also the periphery).
Step (F): Contact plugs 2910 are made to source and drain regions of different layers of memory. Bit-line (BL) wiring 2911 and Source-line (SL) wiring 2912 are connected to contact plugs 2910. Gate regions 2913 of memory layers are connected together to form word-line (WL) wiring.
Step (A): Peripheral circuits with tungsten wiring 3002 are first constructed and above this a layer of silicon dioxide 3004 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
Step (I):
Step (J):
Step (K):
A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e., current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
Step (A): Peripheral circuits with tungsten wiring 3102 are first constructed and above this a layer of silicon dioxide 3104 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
Step (I):
Step (J):
A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
With the explanations for the formation of monolithic 3D DRAM with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D DRAM array, and this nomenclature can be interchanged. Each gate of the double gate 3D DRAM can be independently controlled for better control of the memory cell. To implement these changes, the process steps in
Section 4: Monolithic 3D Resistance-Based Memory
While many of today's memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in “Overview of candidate device technologies for storage-class memory,” IBM Journal of Research and Development, vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W.; Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.; Shenoy, R. S.
Step (A): Peripheral circuits 3202 are first constructed and above this a layer of silicon dioxide 3204 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
Step (I):
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
Step (A): Peripheral circuits with tungsten wiring 3302 are first constructed and above this a layer of silicon dioxide 3304 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
Step (I):
Step (J):
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
Step (A): Peripheral circuits with tungsten wiring 3402 are first constructed and above this a layer of silicon dioxide 3404 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
Step (I):
Step (J):
Step (K):
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
Step (A): The process flow starts with a p− silicon wafer 3502 with an oxide coating 3504.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in the transistor channels, and (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
While explanations have been given for formation of monolithic 3D resistive memories with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D resistive memory array, and this nomenclature can be interchanged. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown in
Section 5: Monolithic 3D Charge-Trap Memory
While resistive memories described previously form a class of non-volatile memory, others classes of non-volatile memory exist. NAND flash memory forms one of the most common non-volatile memory types. It can be constructed of two main types of devices: floating-gate devices where charge is stored in a floating gate and charge-trap devices where charge is stored in a charge-trap layer such as Silicon Nitride. Background information on charge-trap memory can be found in “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”) and “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. The architectures shown in
Step (A): A p− Silicon wafer 3602 is taken and an oxide layer 3604 is grown or deposited above it.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, and (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of monocrystalline silicon (or single crystal silicon) using ion-cut can be a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work described by Bakir in his textbook used selective epi technology or laser recrystallization or polysilicon.
Step (A): Peripheral circuits 3702 are first constructed and above this a layer of silicon dioxide 3704 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., bit lines BL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of single-crystal silicon obtained with ion-cut is a key differentiator from past work on 3D charge-trap memories such as “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. that used polysilicon.
While
Section 6: Monolithic 3D Floating-Gate Memory
While charge-trap memory forms one type of non-volatile memory, floating-gate memory is another type. Background information on floating-gate flash memory can be found in “Introduction to Flash memory”, Proc. IEEE 91, 489-502 (2003) by R. Bez, et al. There are different types of floating-gate memory based on different materials and device structures. The architectures shown in
Step (A): A p− Silicon wafer 3902 is taken and an oxide layer 3904 is grown or deposited above it.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
A 3D floating-gate memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flow in substantially the horizontal direction in transistor channels, (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of monocrystalline silicon (or single crystal silicon) using ion-cut is a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work used selective epi technology or laser recrystallization or polysilicon.
Step (A): Peripheral circuits 4002 are first constructed and above this a layer of silicon dioxide 4004 is deposited.
Step (B):
Step (C):
Step (D):
Step (E):
Step (F):
Step (G):
Step (H):
While the steps shown in
A 3D floating-gate memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) some of the memory cell control lines are in the same memory layer as the devices. The use of monocrystalline silicon (or single crystal silicon) layer obtained by ion-cut in (2) is a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work used selective epi technology or laser recrystallization or polysilicon.
Section 7: Alternative Implementations of Various Monolithic 3D Memory Concepts
While the 3D DRAM and 3D resistive memory implementations in Section 3 and Section 4 have been described with single crystal silicon constructed with ion-cut technology, other options exist. One could construct them with selective epi technology. Procedures for doing these will be clear to those skilled in the art.
Various layer transfer schemes described in Section 1.3.4 can be utilized for constructing single-crystal silicon layers for memory architectures described in Section 3, Section 4, Section 5 and Section 6.
The double gate devices shown in
One of the concerns with using n+ Silicon as a control line for 3D memory arrays is its high resistance. Using lithography and (single-step of multi-step) ion-implantation, one could dope heavily the n+ silicon control lines while not doping transistor gates, sources and drains in the 3D memory array. This preferential doping may mitigate the concern of high resistance.
In many of the described 3D memory approaches, etching and filling high aspect ratio vias forms a serious limitation. One way to circumvent this obstacle is by etching and filling vias from two sides of a wafer. A procedure for doing this is shown in
Step (A): 3D resistive memories are constructed as shown in
Step (B): Hydrogen is implanted into the wafer 4202 at a certain depth 4242.
Step (C): The wafer with the structure after Step (B) is bonded to a bare silicon wafer 4244. Cleaving is then performed at the hydrogen implant plane 4242. A CMP process is conducted to polish off the silicon wafer.
Step (D): Resistance change memory material and BL contact layers 4241 are constructed for the bottom memory layers. They connect to the partially made top BL contacts 4236 with state-of-the-art alignment.
Step (E): Peripheral transistors 4246 are constructed using procedures shown previously in this document.
The charge-trap and floating-gate architectures shown in FIG. 36A-F-
Section 8: Poly-Silicon-Based Implementation of Various Memory Concepts
The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-silicon-based memory architectures as well. Poly silicon based architectures could potentially be cheaper than single crystal silicon based architectures when a large number of memory layers need to be constructed. While the below concepts are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to NAND flash memory and DRAM architectures described previously in this patent application.
Step (A): As illustrated in
Step (B): As illustrated in
Step (C): As illustrated in
Step (D): As illustrated in
Step (E): As illustrated in
Step (A): As illustrated in
Step (B): As illustrated in
Step (C): As illustrated in
Step (D): This is illustrated in
Step (E): This is illustrated in
Step (F): Using procedures described in Section 1 and Section 2 of this patent application, peripheral circuits 5198 (with transistors and wires) could be formed well aligned to the multiple memory layers shown in Step (E). For the periphery, one could use the process flow shown in Section 2 where replacement gate processing is used, or one could use sub-400° C. processed transistors such as junction-less transistors or recessed channel transistors. Alternatively, one could use laser anneals for peripheral transistors' source-drain processing. Various other procedures described in Section 1 and Section 2 could also be used. Connections can then be formed between the multiple memory layers and peripheral circuits. By proper choice of materials for memory layer transistors and memory layer wires (e.g., by using tungsten and other materials that withstand high temperature processing for wiring), even standard transistors processed at high temperatures (>1000° C.) for the periphery could be used.
Section 9: Monolithic 3D SRAM
The techniques described in this patent application can be used for constructing monolithic 3D SRAMs as well.
It can be seen that the SRAM cell shown in
It is clear to one skilled in the art that other techniques described in this patent application, such as use of junction-less transistors or recessed channel transistors, could be utilized to form the structures shown in
Section 10: NuPackaging Technology
In both the packaging types described in
Step (A) is illustrated in
Step (B) is illustrated in
Step (C) is illustrated using
Step (D) is illustrated using
Step (E) is illustrated using
Step (F) is illustrated using
There are two key conditions while choosing the CTE matched carrier wafer 5414 for this embodiment of the invention. Firstly, the CTE matched carrier wafer 5414 should have a CTE close to that of the organic substrate 5420. Preferably, the CTE of the CTE matched carrier wafer 5414 should be within 10 ppm/K of that of the organic substrate 5420. Secondly, the volume of the CTE matched carrier wafer 5414 should be much higher than the silicon region 5406. Preferably, the volume of the CTE matched carrier wafer 5414 is greater than 5 times the volume of the silicon region 5406. When this happens, the CTE of the combination of the silicon region 5406 and the CTE matched carrier 5414 is close to that of the CTE matched carrier 5414. If these two conditions are met, the issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used.
The organic substrate 5420 typically has a CTE around 17 ppm/K and the printed wiring board 5424 typically is constructed of FR4 which has a CTE around 18 ppm/K. If the CTE matched carrier wafer is constructed of an organic material having a CTE of 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used. If the CTE matched carrier wafer is constructed of a copper alloy having a CTE of around 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used. If the CTE matched carrier wafer is constructed of an aluminum alloy material having a CTE of 24 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used.
Step (A) is illustrated in
Step (B) is illustrated in
Step (C) is illustrated using
Step (D) is illustrated using
Step (E) is illustrated using
Step (F) is illustrated using
There are two key conditions while choosing the CTE matched carrier wafer 5514 for this embodiment of the invention. Firstly, the CTE matched carrier wafer 5514 should have a CTE close to that of the organic substrate 5520. Preferably, the CTE of the CTE matched carrier wafer 5514 should be within 10 ppm/K of that of the organic substrate 5520. Secondly, the volume of the CTE matched carrier wafer 5514 should be much higher than the silicon region 5506. Preferably, the volume of the CTE matched carrier wafer 5514 is greater than 5 times the volume of the silicon region 5506. When this happens, the CTE of the combination of the silicon region 5506 and the CTE matched carrier 5514 is close to that of the CTE matched carrier 5514. If these two conditions are met, the issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used.
The organic substrate 5520 typically has a CTE around 17 ppm/K and the printed wiring board 5524 typically is constructed of FR4 which has a CTE around 18 ppm/K. If the CTE matched carrier wafer is constructed of an organic material having a CTE of 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used. If the CTE matched carrier wafer is constructed of a copper alloy having a CTE of around 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used. If the CTE matched carrier wafer is constructed of an aluminum alloy material having a CTE of 24 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and one can have a reliable packaging process without underfill being used.
While
It will be clear to one skilled in the art that other methods to thin a wafer and attach a CTE matched carrier wafer exist. Other methods to thin a wafer include, not are not limited to, CMP, etch or a combination of these two processes. These processes can be supplemented with various metrology schemes to monitor wafer thickness during thinning Carefully timed thinning processes can also be used.
Section 11: Process Modules for Sub-400° C. Transistors and Contacts
Section 1 discussed various methods to create junctionless transistors and recessed channel transistors with temperatures of less than 400° C.-450° C. after stacking. For these transistor types and other technologies described in this disclosure, process modules such as bonding, cleave, planarization after cleave, isolation, contact formation and strain incorporation would benefit from being conducted at temperatures below 400° C. Techniques to conduct these process modules at less than about 400° C. are described in Section 11.
Section 11.1: Sub-400° C. Bonding Process Module
Bonding of layers for transfer (as shown, for example, in
Section 11.2: Sub-400° C. Cleave Process Module
As described previously in this disclosure, a cleave process can be performed advantageously at less than 400° C. by implantation with hydrogen, helium or a combination of the two species followed by a sideways mechanical force. Alternatively, the cleave process can be performed advantageously at less than 400° C. by implantation with hydrogen, helium or a combination of the two species followed by an anneal. These approaches are described in detail in Section 1 through the description for
The temperature required for hydrogen implantation followed by an anneal-based cleave can be reduced substantially by implanting the hydrogen species in a buried p+ silicon layer where the dopant is boron. This approach has been described previously in this disclosure in Section 1.3.3 through the description of
Section 11.3: Planarization and Surface Smoothening after Cleave at Less than 400° C.
The irregular features 5612 can be removed using a chemical mechanical polish (CMP) that planarizes the surface.
Alternatively, a process shown in
Alternatively, according to an embodiment of this invention, surface non-planarities can be removed or reduced by treating in a hydrogen plasma at less than 400-450° C. Hydrogen anneals at 1100° C. are known to reduce surface roughness in silicon. By having a plasma, the temperature requirement can be reduced to less than 400-450° C.
Alternatively, according to another embodiment of this invention, a thin film (eg. oxide) can be deposited atop the non-planar surface and etched back. The etchant required for this etch-back process is preferably one that has approximately equal etch rates for both silicon and the deposited thin film. This could reduce non-planarities on the wafer surface as well.
Alternatively, Gas Cluster Ion Beam technology can be utilized for smoothing surfaces after cleaving along an implanted plane of hydrogen.
A combination of various techniques described in Section 11.3 can also be used.
Section 11.4: Sub-400° C. Isolation Module
Step (A) is illustrated using
Step (B) is illustrated using
Step (C) is illustrated using
Step (D) is illustrated using
The prior art process described in
Step (A) is illustrated using
Step (B) is illustrated using
Step (C) is illustrated using
Step (D) is illustrated using
It can be observed that the process described using
Section 11.5: Sub-400° C. Silicide Contact Module
To improve the contact resistance of very small scaled contacts, the semiconductor industry employs various metal silicides, such as, for example, cobalt silicide, titanium silicide, tantalum silicide, and nickel silicide. The current advanced CMOS processes, such as, for example, 45 nm, 32 nm, and 22 nm employ nickel silicides to improve deep submicron source and drain contact resistances. Background information on silicides utilized for contact resistance reduction can be found in “NiSi Salicide Technology for Scaled CMOS,” H. Iwai, et. al., Microelectronic Engineering, 60 (2002), pp 157-169; “Nickel vs. Cobalt Silicide integration for sub-50 nm CMOS”, B. Froment, et. al., IMEC ESS Circuits, 2003; and “65 and 45-nm Devices—an Overview”, D. James, Semicon West, July 2008, ctr—024377. To achieve the lowest nickel silicide contact and source/drain resistances, the nickel on silicon could require heating to 450° C.
Thus it may be desirable to enable low resistances for process flows in this document where the post layer transfer temperature exposures must remain under approximately 400° C. due to metallization, such as, for example, copper and aluminum, and low-k dielectrics present. The example process flow forms a Recessed Channel Array Transistor (RCAT), but this or similar flows may be applied to other process flows and devices, such as, for example, S-RCAT, JLT, V-groove, JFET, bipolar, and replacement gate flows.
A planar n-channel Recessed Channel Array Transistor (RCAT) with metal silicide source & drain contacts suitable for a 3D IC may be constructed. As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
Persons of ordinary skill in the art will appreciate that the illustrations in
While the “silicide-before-layer-transfer” process flow described in
One can also create strained silicon regions at less than 400° C. by depositing dielectric strain-inducing layers around recessed channel devices and junctionless transistors in STI regions, in pre-metal dielectric regions, in contact etch stop layers and also in other regions around these transistors.
Section 12: Construction of Sub-400° C. Transistors Using Sub-400° C. Activation Anneals
As described in
Step (A) is illustrated using
Step (B) is illustrated using
Step (C) is illustrated using
Step (D) is illustrated using
Step (E) is illustrated using
(i) A hydrogen plasma treatment can be conducted, following which dopants for source and drain regions 6020 can be implanted. Following the implantation, an activation anneal can be performed using a rapid thermal anneal (RTA). Alternatively, a laser anneal could be used. Alternatively, a spike anneal could be used. Alternatively, a furnace anneal could be used. Hydrogen plasma treatment before source-drain dopant implantation is known to reduce temperatures for source-drain activation to be less than 450° C. or even less that 400° C. Further details of this process for forming and activating source-drain regions are described in “Mechanism of Dopant Activation Enhancement in Shallow Junctions by Hydrogen”, Proceedings of the Materials Research Society, Spring 2005 by A. Vengurlekar, S. Ashok, Christine E. Kalnas, Win Ye. This embodiment of the invention advantageously uses this low-temperature source-drain formation technique and layer transfer techniques and produces 3D integrated circuits and chips.
(ii) Alternatively, another process can be used for forming activated source-drain regions. Dopants for source and drain regions 6020 can be implanted, following which a hydrogen implantation can be conducted. Alternatively, some other atomic species can be used. An activation anneal can then be conducted using a RTA. Alternatively, a furnace anneal or spike anneal or laser anneal can be used. Hydrogen implantation is known to reduce temperatures required for the activation anneal. Further details of this process are described in U.S. Pat. No. 4,522,657. This embodiment of the invention advantageously uses this low-temperature source-drain formation technique and layer transfer techniques and produces 3D integrated circuits and chips.
(iii) Alternatively, another process can be used for forming activated source-drain regions. The wafer could be heated up when implantation for source-drain regions 6020 is carried out. Due to this, the energetic implanted species is subjected to higher temperatures and can be activated at the same time as it is implanted. Further details of this process can be seen in U.S. Pat. No. 6,111,260. This embodiment of the invention advantageously uses this low-temperature source-drain formation technique and layer transfer techniques and produces 3D integrated circuits and chips.
Step (F) is illustrated using
It will also be appreciated by persons of ordinary skill in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3007090 | Rutz | Oct 1961 | A |
| 3819959 | Chang et al. | Jun 1974 | A |
| 4197555 | Uehara et al. | Apr 1980 | A |
| 4400715 | Barbee et al. | Aug 1983 | A |
| 4487635 | Kugimiya et al. | Dec 1984 | A |
| 4522657 | Rohatgi et al. | Jun 1985 | A |
| 4612083 | Yasumoto et al. | Sep 1986 | A |
| 4643950 | Ogura et al. | Feb 1987 | A |
| 4704785 | Curran | Nov 1987 | A |
| 4711858 | Harder et al. | Dec 1987 | A |
| 4721885 | Brodie | Jan 1988 | A |
| 4732312 | Kennedy et al. | Mar 1988 | A |
| 4733288 | Sato | Mar 1988 | A |
| 4829018 | Wahlstrom | May 1989 | A |
| 4854986 | Raby | Aug 1989 | A |
| 4866304 | Yu | Sep 1989 | A |
| 4939568 | Kato et al. | Jul 1990 | A |
| 4956307 | Pollack et al. | Sep 1990 | A |
| 5012153 | Atkinson et al. | Apr 1991 | A |
| 5032007 | Silverstein et al. | Jul 1991 | A |
| 5047979 | Leung | Sep 1991 | A |
| 5087585 | Hayashi | Feb 1992 | A |
| 5093704 | Saito et al. | Mar 1992 | A |
| 5106775 | Kaga et al. | Apr 1992 | A |
| 5152857 | Ito et al. | Oct 1992 | A |
| 5162879 | Gill | Nov 1992 | A |
| 5217916 | Anderson et al. | Jun 1993 | A |
| 5250460 | Yamagata et al. | Oct 1993 | A |
| 5258643 | Cohen | Nov 1993 | A |
| 5265047 | Leung et al. | Nov 1993 | A |
| 5266511 | Takao | Nov 1993 | A |
| 5277748 | Sakaguchi et al. | Jan 1994 | A |
| 5286670 | Kang et al. | Feb 1994 | A |
| 5294556 | Kawamura | Mar 1994 | A |
| 5308782 | Mazure et al. | May 1994 | A |
| 5312771 | Yonehara | May 1994 | A |
| 5317236 | Zavracky et al. | May 1994 | A |
| 5324980 | Kusunoki | Jun 1994 | A |
| 5355022 | Sugahara et al. | Oct 1994 | A |
| 5371037 | Yonehara | Dec 1994 | A |
| 5374564 | Bruel | Dec 1994 | A |
| 5374581 | Ichikawa et al. | Dec 1994 | A |
| 5424560 | Norman et al. | Jun 1995 | A |
| 5475280 | Jones et al. | Dec 1995 | A |
| 5478762 | Chao | Dec 1995 | A |
| 5485031 | Zhang et al. | Jan 1996 | A |
| 5498978 | Takahashi et al. | Mar 1996 | A |
| 5527423 | Neville et al. | Jun 1996 | A |
| 5535342 | Taylor | Jul 1996 | A |
| 5554870 | Fitch et al. | Sep 1996 | A |
| 5563084 | Ramm et al. | Oct 1996 | A |
| 5583349 | Norman et al. | Dec 1996 | A |
| 5583350 | Norman et al. | Dec 1996 | A |
| 5594563 | Larson | Jan 1997 | A |
| 5604137 | Yamazaki et al. | Feb 1997 | A |
| 5617991 | Pramanick et al. | Apr 1997 | A |
| 5627106 | Hsu | May 1997 | A |
| 5656548 | Zavracky et al. | Aug 1997 | A |
| 5670411 | Yonehara | Sep 1997 | A |
| 5681756 | Norman et al. | Oct 1997 | A |
| 5695557 | Yamagata et al. | Dec 1997 | A |
| 5701027 | Gordon et al. | Dec 1997 | A |
| 5707745 | Forrest et al. | Jan 1998 | A |
| 5714395 | Bruel | Feb 1998 | A |
| 5721160 | Forrest et al. | Feb 1998 | A |
| 5737748 | Shigeeda | Apr 1998 | A |
| 5739552 | Kimura et al. | Apr 1998 | A |
| 5744979 | Goetting | Apr 1998 | A |
| 5748161 | Lebby et al. | May 1998 | A |
| 5757026 | Forrest et al. | May 1998 | A |
| 5770881 | Pelella et al. | Jun 1998 | A |
| 5781031 | Bertin et al. | Jul 1998 | A |
| 5829026 | Leung et al. | Oct 1998 | A |
| 5835396 | Zhang | Nov 1998 | A |
| 5854123 | Sato et al. | Dec 1998 | A |
| 5861929 | Spitzer | Jan 1999 | A |
| 5877070 | Goesele et al. | Mar 1999 | A |
| 5882987 | Srikrishnan | Mar 1999 | A |
| 5883525 | Tavana et al. | Mar 1999 | A |
| 5889903 | Rao | Mar 1999 | A |
| 5893721 | Huang et al. | Apr 1999 | A |
| 5915167 | Leedy | Jun 1999 | A |
| 5937312 | Iyer et al. | Aug 1999 | A |
| 5943574 | Tehrani et al. | Aug 1999 | A |
| 5952680 | Strite | Sep 1999 | A |
| 5952681 | Chen | Sep 1999 | A |
| 5965875 | Merrill | Oct 1999 | A |
| 5977579 | Noble | Nov 1999 | A |
| 5977961 | Rindal | Nov 1999 | A |
| 5980633 | Yamagata et al. | Nov 1999 | A |
| 5985742 | Henley et al. | Nov 1999 | A |
| 5998808 | Matsushita | Dec 1999 | A |
| 6001693 | Yeouchung et al. | Dec 1999 | A |
| 6009496 | Tsai | Dec 1999 | A |
| 6020252 | Aspar et al. | Feb 2000 | A |
| 6020263 | Shih et al. | Feb 2000 | A |
| 6027958 | Vu et al. | Feb 2000 | A |
| 6030700 | Forrest et al. | Feb 2000 | A |
| 6052498 | Paniccia | Apr 2000 | A |
| 6057212 | Chan et al. | May 2000 | A |
| 6071795 | Cheung et al. | Jun 2000 | A |
| 6103597 | Aspar et al. | Aug 2000 | A |
| 6111260 | Dawson et al. | Aug 2000 | A |
| 6125217 | Paniccia et al. | Sep 2000 | A |
| 6153495 | Kub et al. | Nov 2000 | A |
| 6191007 | Matsui et al. | Feb 2001 | B1 |
| 6222203 | Ishibashi et al. | Apr 2001 | B1 |
| 6229161 | Nemati et al. | May 2001 | B1 |
| 6242324 | Kub et al. | Jun 2001 | B1 |
| 6259623 | Takahashi | Jul 2001 | B1 |
| 6264805 | Forrest et al. | Jul 2001 | B1 |
| 6281102 | Cao et al. | Aug 2001 | B1 |
| 6294018 | Hamm et al. | Sep 2001 | B1 |
| 6306705 | Parekh et al. | Oct 2001 | B1 |
| 6321134 | Henley et al. | Nov 2001 | B1 |
| 6322903 | Siniaguine et al. | Nov 2001 | B1 |
| 6331468 | Aronowitz et al. | Dec 2001 | B1 |
| 6331790 | Or-Bach et al. | Dec 2001 | B1 |
| 6353492 | McClelland et al. | Mar 2002 | B2 |
| 6355501 | Fung et al. | Mar 2002 | B1 |
| 6358631 | Forrest et al. | Mar 2002 | B1 |
| 6365270 | Forrest et al. | Apr 2002 | B2 |
| 6376337 | Wang et al. | Apr 2002 | B1 |
| 6380046 | Yamazaki | Apr 2002 | B1 |
| 6392253 | Saxena | May 2002 | B1 |
| 6417108 | Akino et al. | Jul 2002 | B1 |
| 6420215 | Knall et al. | Jul 2002 | B1 |
| 6423614 | Doyle | Jul 2002 | B1 |
| 6429481 | Mo et al. | Aug 2002 | B1 |
| 6429484 | Yu | Aug 2002 | B1 |
| 6430734 | Zahar | Aug 2002 | B1 |
| 6475869 | Yu | Nov 2002 | B1 |
| 6476493 | Or-Bach et al. | Nov 2002 | B2 |
| 6479821 | Hawryluk et al. | Nov 2002 | B1 |
| 6515511 | Sugibayashi et al. | Feb 2003 | B2 |
| 6526559 | Schiefele et al. | Feb 2003 | B2 |
| 6528391 | Henley et al. | Mar 2003 | B1 |
| 6534352 | Kim | Mar 2003 | B1 |
| 6534382 | Sakaguchi et al. | Mar 2003 | B1 |
| 6544837 | Divakauni et al. | Apr 2003 | B1 |
| 6545314 | Forbes et al. | Apr 2003 | B2 |
| 6555901 | Yoshihara et al. | Apr 2003 | B1 |
| 6563139 | Hen | May 2003 | B2 |
| 6580289 | Cox | Jun 2003 | B2 |
| 6600173 | Tiwari | Jul 2003 | B2 |
| 6624046 | Zavracky et al. | Sep 2003 | B1 |
| 6627518 | Inoue et al. | Sep 2003 | B1 |
| 6630713 | Geusic | Oct 2003 | B2 |
| 6635552 | Gonzalez | Oct 2003 | B1 |
| 6635588 | Hawryluk et al. | Oct 2003 | B1 |
| 6638834 | Gonzalez | Oct 2003 | B2 |
| 6642744 | Or-Bach et al. | Nov 2003 | B2 |
| 6653209 | Yamagata | Nov 2003 | B1 |
| 6661085 | Kellar et al. | Dec 2003 | B2 |
| 6677204 | Cleeves et al. | Jan 2004 | B2 |
| 6686253 | Or-Bach | Feb 2004 | B2 |
| 6703328 | Tanaka et al. | Mar 2004 | B2 |
| 6756633 | Wang et al. | Jun 2004 | B2 |
| 6756811 | Or-Bach | Jun 2004 | B2 |
| 6759282 | Campbell et al. | Jul 2004 | B2 |
| 6762076 | Kim et al. | Jul 2004 | B2 |
| 6774010 | Chu et al. | Aug 2004 | B2 |
| 6805979 | Ogura et al. | Oct 2004 | B2 |
| 6806171 | Ulyashin et al. | Oct 2004 | B1 |
| 6809009 | Aspar et al. | Oct 2004 | B2 |
| 6815781 | Vyvoda et al. | Nov 2004 | B2 |
| 6819136 | Or-Bach | Nov 2004 | B2 |
| 6821826 | Chan et al. | Nov 2004 | B1 |
| 6841813 | Walker et al. | Jan 2005 | B2 |
| 6844243 | Gonzalez | Jan 2005 | B1 |
| 6864534 | Ipposhi et al. | Mar 2005 | B2 |
| 6875671 | Faris | Apr 2005 | B2 |
| 6882572 | Wang et al. | Apr 2005 | B2 |
| 6888375 | Feng et al. | May 2005 | B2 |
| 6917219 | New | Jul 2005 | B2 |
| 6930511 | Or-Bach | Aug 2005 | B2 |
| 6943067 | Greenlaw | Sep 2005 | B2 |
| 6943407 | Ouyang et al. | Sep 2005 | B2 |
| 6949421 | Padmanabhan et al. | Sep 2005 | B1 |
| 6953956 | Or-Bach et al. | Oct 2005 | B2 |
| 6967149 | Meyer et al. | Nov 2005 | B2 |
| 6985012 | Or-Bach | Jan 2006 | B2 |
| 6989687 | Or-Bach | Jan 2006 | B2 |
| 6995430 | Langdo et al. | Feb 2006 | B2 |
| 6995456 | Nowak | Feb 2006 | B2 |
| 7015719 | Feng et al. | Mar 2006 | B1 |
| 7016569 | Mule et al. | Mar 2006 | B2 |
| 7018875 | Madurawe | Mar 2006 | B2 |
| 7019557 | Madurawe | Mar 2006 | B2 |
| 7043106 | West et al. | May 2006 | B2 |
| 7052941 | Lee | May 2006 | B2 |
| 7064579 | Madurawe | Jun 2006 | B2 |
| 7067396 | Aspar et al. | Jun 2006 | B2 |
| 7068070 | Or-Bach | Jun 2006 | B2 |
| 7068072 | New et al. | Jun 2006 | B2 |
| 7078739 | Nemati et al. | Jul 2006 | B1 |
| 7094667 | Bower | Aug 2006 | B1 |
| 7098691 | Or-Bach et al. | Aug 2006 | B2 |
| 7105390 | Brask et al. | Sep 2006 | B2 |
| 7105871 | Or-Bach et al. | Sep 2006 | B2 |
| 7109092 | Tong | Sep 2006 | B2 |
| 7110629 | Bjorkman et al. | Sep 2006 | B2 |
| 7111149 | Eilert | Sep 2006 | B2 |
| 7115945 | Lee et al. | Oct 2006 | B2 |
| 7115966 | Ido et al. | Oct 2006 | B2 |
| 7141853 | Campbell et al. | Nov 2006 | B2 |
| 7148119 | Sakaguchi et al. | Dec 2006 | B1 |
| 7157787 | Kim et al. | Jan 2007 | B2 |
| 7157937 | Apostol et al. | Jan 2007 | B2 |
| 7166520 | Henley | Jan 2007 | B1 |
| 7170807 | Fazan et al. | Jan 2007 | B2 |
| 7173369 | Forrest et al. | Feb 2007 | B2 |
| 7180091 | Yamazaki et al. | Feb 2007 | B2 |
| 7180379 | Hopper et al. | Feb 2007 | B1 |
| 7189489 | Kunimoto et al. | Mar 2007 | B2 |
| 7205204 | Ogawa et al. | Apr 2007 | B2 |
| 7209384 | Kim | Apr 2007 | B1 |
| 7217636 | Atanackovic | May 2007 | B1 |
| 7223612 | Sarma | May 2007 | B2 |
| 7242012 | Leedy | Jul 2007 | B2 |
| 7245002 | Akino et al. | Jul 2007 | B2 |
| 7256104 | Ito et al. | Aug 2007 | B2 |
| 7259091 | Schuehrer et al. | Aug 2007 | B2 |
| 7265421 | Madurawe | Sep 2007 | B2 |
| 7271420 | Cao | Sep 2007 | B2 |
| 7282951 | Huppenthal et al. | Oct 2007 | B2 |
| 7284226 | Kondapalli | Oct 2007 | B1 |
| 7296201 | Abramovici | Nov 2007 | B2 |
| 7304355 | Zhang | Dec 2007 | B2 |
| 7312109 | Madurawe | Dec 2007 | B2 |
| 7312487 | Alam et al. | Dec 2007 | B2 |
| 7335573 | Takayama et al. | Feb 2008 | B2 |
| 7337425 | Kirk | Feb 2008 | B2 |
| 7338884 | Shimoto et al. | Mar 2008 | B2 |
| 7351644 | Henley | Apr 2008 | B2 |
| 7358601 | Plants et al. | Apr 2008 | B1 |
| 7362133 | Madurawe | Apr 2008 | B2 |
| 7369435 | Forbes | May 2008 | B2 |
| 7371660 | Henley et al. | May 2008 | B2 |
| 7378702 | Lee | May 2008 | B2 |
| 7393722 | Issaq et al. | Jul 2008 | B1 |
| 7419844 | Lee et al. | Sep 2008 | B2 |
| 7436027 | Ogawa et al. | Oct 2008 | B2 |
| 7439773 | Or-Bach et al. | Oct 2008 | B2 |
| 7446563 | Madurawe | Nov 2008 | B2 |
| 7459752 | Doris et al. | Dec 2008 | B2 |
| 7459763 | Issaq et al. | Dec 2008 | B1 |
| 7459772 | Speers | Dec 2008 | B2 |
| 7463062 | Or-Bach et al. | Dec 2008 | B2 |
| 7470142 | Lee | Dec 2008 | B2 |
| 7470598 | Lee | Dec 2008 | B2 |
| 7476939 | Okhonin et al. | Jan 2009 | B2 |
| 7477540 | Okhonin et al. | Jan 2009 | B2 |
| 7485968 | Enquist et al. | Feb 2009 | B2 |
| 7486563 | Waller et al. | Feb 2009 | B2 |
| 7488980 | Takafuji et al. | Feb 2009 | B2 |
| 7492632 | Carman | Feb 2009 | B2 |
| 7495473 | McCollum et al. | Feb 2009 | B2 |
| 7498675 | Farnworth et al. | Mar 2009 | B2 |
| 7499352 | Singh | Mar 2009 | B2 |
| 7499358 | Bauser | Mar 2009 | B2 |
| 7508034 | Takafuji et al. | Mar 2009 | B2 |
| 7514748 | Fazan et al. | Apr 2009 | B2 |
| 7535089 | Fitzgerald | May 2009 | B2 |
| 7541616 | Fazan et al. | Jun 2009 | B2 |
| 7547589 | Iriguchi | Jun 2009 | B2 |
| 7557367 | Rogers et al. | Jul 2009 | B2 |
| 7563659 | Kwon et al. | Jul 2009 | B2 |
| 7566855 | Olsen et al. | Jul 2009 | B2 |
| 7586778 | Ho et al. | Sep 2009 | B2 |
| 7589375 | Jang et al. | Sep 2009 | B2 |
| 7608848 | Ho et al. | Oct 2009 | B2 |
| 7622367 | Nuzzo et al. | Nov 2009 | B1 |
| 7632738 | Lee | Dec 2009 | B2 |
| 7633162 | Lee | Dec 2009 | B2 |
| 7666723 | Frank et al. | Feb 2010 | B2 |
| 7671371 | Lee | Mar 2010 | B2 |
| 7671460 | Lauxtermann et al. | Mar 2010 | B2 |
| 7674687 | Henley | Mar 2010 | B2 |
| 7687372 | Jain | Mar 2010 | B2 |
| 7688619 | Lung et al. | Mar 2010 | B2 |
| 7692202 | Bensch | Apr 2010 | B2 |
| 7692448 | Solomon | Apr 2010 | B2 |
| 7692944 | Bernstein et al. | Apr 2010 | B2 |
| 7697316 | Lai et al. | Apr 2010 | B2 |
| 7709932 | Nemoto et al. | May 2010 | B2 |
| 7718508 | Lee | May 2010 | B2 |
| 7723207 | Alam et al. | May 2010 | B2 |
| 7728326 | Yamazaki et al. | Jun 2010 | B2 |
| 7732301 | Pinnington et al. | Jun 2010 | B1 |
| 7749884 | Mathew et al. | Jul 2010 | B2 |
| 7759043 | Tanabe et al. | Jul 2010 | B2 |
| 7768115 | Lee et al. | Aug 2010 | B2 |
| 7774735 | Sood | Aug 2010 | B1 |
| 7776715 | Wells et al. | Aug 2010 | B2 |
| 7777330 | Pelley et al. | Aug 2010 | B2 |
| 7786460 | Lung et al. | Aug 2010 | B2 |
| 7786535 | Abou-Khalil et al. | Aug 2010 | B2 |
| 7790524 | Abadeer et al. | Sep 2010 | B2 |
| 7795619 | Hara | Sep 2010 | B2 |
| 7799675 | Lee | Sep 2010 | B2 |
| 7800099 | Yamazaki et al. | Sep 2010 | B2 |
| 7800199 | Oh et al. | Sep 2010 | B2 |
| 7843718 | Koh et al. | Nov 2010 | B2 |
| 7846814 | Lee | Dec 2010 | B2 |
| 7867822 | Lee | Jan 2011 | B2 |
| 7888764 | Lee | Feb 2011 | B2 |
| 7915164 | Konevecki et al. | Mar 2011 | B2 |
| 8013399 | Thomas et al. | Sep 2011 | B2 |
| 8014195 | Okhonin et al. | Sep 2011 | B2 |
| 8031544 | Kim et al. | Oct 2011 | B2 |
| 8044464 | Yamazaki et al. | Oct 2011 | B2 |
| 8107276 | Breitwisch et al. | Jan 2012 | B2 |
| 8129256 | Farooq et al. | Mar 2012 | B2 |
| 8136071 | Solomon | Mar 2012 | B2 |
| 8158515 | Farooq et al. | Apr 2012 | B2 |
| 8183630 | Batude et al. | May 2012 | B2 |
| 8184463 | Saen et al. | May 2012 | B2 |
| 8203187 | Lung et al. | Jun 2012 | B2 |
| 8208279 | Lue | Jun 2012 | B2 |
| 20010000005 | Forrest et al. | Mar 2001 | A1 |
| 20010014391 | Forrest et al. | Aug 2001 | A1 |
| 20020024140 | Nakajima et al. | Feb 2002 | A1 |
| 20020025604 | Tiwari | Feb 2002 | A1 |
| 20020081823 | Cheung et al. | Jun 2002 | A1 |
| 20020096681 | Yamazaki et al. | Jul 2002 | A1 |
| 20020141233 | Hosotani et al. | Oct 2002 | A1 |
| 20020153243 | Forrest et al. | Oct 2002 | A1 |
| 20020180069 | Houston | Dec 2002 | A1 |
| 20020190232 | Chason | Dec 2002 | A1 |
| 20020199110 | Kean | Dec 2002 | A1 |
| 20030015713 | Yoo | Jan 2003 | A1 |
| 20030032262 | Dennison et al. | Feb 2003 | A1 |
| 20030059999 | Gonzalez | Mar 2003 | A1 |
| 20030060034 | Beyne et al. | Mar 2003 | A1 |
| 20030067043 | Zhang | Apr 2003 | A1 |
| 20030102079 | Kalvesten et al. | Jun 2003 | A1 |
| 20030107117 | Antonell et al. | Jun 2003 | A1 |
| 20030113963 | Wurzer | Jun 2003 | A1 |
| 20030119279 | Enquist | Jun 2003 | A1 |
| 20030139011 | Cleeves et al. | Jul 2003 | A1 |
| 20030157748 | Kim et al. | Aug 2003 | A1 |
| 20030206036 | Or-Bach | Nov 2003 | A1 |
| 20030213967 | Forrest et al. | Nov 2003 | A1 |
| 20030224582 | Shimoda et al. | Dec 2003 | A1 |
| 20040014299 | Moriceau et al. | Jan 2004 | A1 |
| 20040033676 | Coronel et al. | Feb 2004 | A1 |
| 20040036126 | Chau et al. | Feb 2004 | A1 |
| 20040047539 | Okubora et al. | Mar 2004 | A1 |
| 20040061176 | Takafuji et al. | Apr 2004 | A1 |
| 20040113207 | Hsu et al. | Jun 2004 | A1 |
| 20040150068 | Leedy | Aug 2004 | A1 |
| 20040152272 | Fladre et al. | Aug 2004 | A1 |
| 20040155301 | Zhang | Aug 2004 | A1 |
| 20040156233 | Bhattacharyya | Aug 2004 | A1 |
| 20040166649 | Bressot et al. | Aug 2004 | A1 |
| 20040175902 | Rayssac et al. | Sep 2004 | A1 |
| 20040178819 | New | Sep 2004 | A1 |
| 20040259312 | Schlosser et al. | Dec 2004 | A1 |
| 20040262635 | Lee | Dec 2004 | A1 |
| 20040262772 | Ramanathan et al. | Dec 2004 | A1 |
| 20050003592 | Jones | Jan 2005 | A1 |
| 20050023656 | Leedy | Feb 2005 | A1 |
| 20050067620 | Chan et al. | Mar 2005 | A1 |
| 20050067625 | Hata | Mar 2005 | A1 |
| 20050073060 | Datta et al. | Apr 2005 | A1 |
| 20050098822 | Mathew | May 2005 | A1 |
| 20050110041 | Boutros et al. | May 2005 | A1 |
| 20050121676 | Fried et al. | Jun 2005 | A1 |
| 20050121789 | Madurawe | Jun 2005 | A1 |
| 20050130351 | Leedy | Jun 2005 | A1 |
| 20050130429 | Rayssac et al. | Jun 2005 | A1 |
| 20050148137 | Brask et al. | Jul 2005 | A1 |
| 20050225237 | Winters | Oct 2005 | A1 |
| 20050266659 | Ghyselen et al. | Dec 2005 | A1 |
| 20050273749 | Kirk | Dec 2005 | A1 |
| 20050280061 | Lee | Dec 2005 | A1 |
| 20050280090 | Anderson et al. | Dec 2005 | A1 |
| 20050280154 | Lee | Dec 2005 | A1 |
| 20050280155 | Lee | Dec 2005 | A1 |
| 20050280156 | Lee | Dec 2005 | A1 |
| 20050282019 | Fukushima et al. | Dec 2005 | A1 |
| 20060014331 | Tang et al. | Jan 2006 | A1 |
| 20060024923 | Sarma et al. | Feb 2006 | A1 |
| 20060033110 | Alam et al. | Feb 2006 | A1 |
| 20060033124 | Or-Bach et al. | Feb 2006 | A1 |
| 20060067122 | Verhoeven | Mar 2006 | A1 |
| 20060071322 | Kitamura | Apr 2006 | A1 |
| 20060071332 | Speers | Apr 2006 | A1 |
| 20060083280 | Tauzin et al. | Apr 2006 | A1 |
| 20060113522 | Lee et al. | Jun 2006 | A1 |
| 20060118935 | Kamiyama et al. | Jun 2006 | A1 |
| 20060121690 | Pogge et al. | Jun 2006 | A1 |
| 20060179417 | Madurawe | Aug 2006 | A1 |
| 20060181202 | Liao et al. | Aug 2006 | A1 |
| 20060189095 | Ghyselen et al. | Aug 2006 | A1 |
| 20060194401 | Hu et al. | Aug 2006 | A1 |
| 20060195729 | Huppenthal et al. | Aug 2006 | A1 |
| 20060207087 | Jafri et al. | Sep 2006 | A1 |
| 20060249859 | Eiles et al. | Nov 2006 | A1 |
| 20060275962 | Lee | Dec 2006 | A1 |
| 20070014508 | Chen et al. | Jan 2007 | A1 |
| 20070035329 | Madurawe | Feb 2007 | A1 |
| 20070063259 | Derderian et al. | Mar 2007 | A1 |
| 20070072391 | Pocas et al. | Mar 2007 | A1 |
| 20070076509 | Zhang | Apr 2007 | A1 |
| 20070077694 | Lee | Apr 2007 | A1 |
| 20070077743 | Rao et al. | Apr 2007 | A1 |
| 20070090416 | Doyle et al. | Apr 2007 | A1 |
| 20070102737 | Kashiwabara et al. | May 2007 | A1 |
| 20070108523 | Ogawa et al. | May 2007 | A1 |
| 20070111386 | Kim et al. | May 2007 | A1 |
| 20070111406 | Joshi et al. | May 2007 | A1 |
| 20070132049 | Stipe | Jun 2007 | A1 |
| 20070132369 | Forrest et al. | Jun 2007 | A1 |
| 20070135013 | Faris | Jun 2007 | A1 |
| 20070158659 | Bensce | Jul 2007 | A1 |
| 20070187775 | Okhonin et al. | Aug 2007 | A1 |
| 20070190746 | Ito et al. | Aug 2007 | A1 |
| 20070194453 | Chakraborty et al. | Aug 2007 | A1 |
| 20070210336 | Madurawe | Sep 2007 | A1 |
| 20070215903 | Sakamoto et al. | Sep 2007 | A1 |
| 20070218622 | Lee et al. | Sep 2007 | A1 |
| 20070228383 | Bernstein et al. | Oct 2007 | A1 |
| 20070252203 | Zhu et al. | Nov 2007 | A1 |
| 20070262457 | Lin | Nov 2007 | A1 |
| 20070275520 | Suzuki | Nov 2007 | A1 |
| 20070281439 | Bedell et al. | Dec 2007 | A1 |
| 20070283298 | Bernstein et al. | Dec 2007 | A1 |
| 20070287224 | Alam et al. | Dec 2007 | A1 |
| 20080032463 | Lee | Feb 2008 | A1 |
| 20080038902 | Lee | Feb 2008 | A1 |
| 20080048327 | Lee | Feb 2008 | A1 |
| 20080067573 | Jang et al. | Mar 2008 | A1 |
| 20080099780 | Tran | May 2008 | A1 |
| 20080108171 | Rogers et al. | May 2008 | A1 |
| 20080124845 | Yu et al. | May 2008 | A1 |
| 20080128745 | Mastro et al. | Jun 2008 | A1 |
| 20080136455 | Diamant et al. | Jun 2008 | A1 |
| 20080150579 | Madurawe | Jun 2008 | A1 |
| 20080160431 | Scott et al. | Jul 2008 | A1 |
| 20080160726 | Lim et al. | Jul 2008 | A1 |
| 20080179678 | Dyer et al. | Jul 2008 | A1 |
| 20080191247 | Yin et al. | Aug 2008 | A1 |
| 20080191312 | Oh et al. | Aug 2008 | A1 |
| 20080194068 | Temmler et al. | Aug 2008 | A1 |
| 20080203452 | Moon et al. | Aug 2008 | A1 |
| 20080213982 | Park et al. | Sep 2008 | A1 |
| 20080220558 | Zehavi et al. | Sep 2008 | A1 |
| 20080220565 | Hsu et al. | Sep 2008 | A1 |
| 20080224260 | Schmit et al. | Sep 2008 | A1 |
| 20080237591 | Leedy | Oct 2008 | A1 |
| 20080248618 | Ahn et al. | Oct 2008 | A1 |
| 20080251862 | Fonash et al. | Oct 2008 | A1 |
| 20080254561 | Yoo | Oct 2008 | A2 |
| 20080254572 | Leedy | Oct 2008 | A1 |
| 20080261378 | Yao et al. | Oct 2008 | A1 |
| 20080272492 | Tsang | Nov 2008 | A1 |
| 20080277778 | Furman et al. | Nov 2008 | A1 |
| 20080283875 | Mukasa et al. | Nov 2008 | A1 |
| 20080284611 | Leedy | Nov 2008 | A1 |
| 20080296681 | Georgakos et al. | Dec 2008 | A1 |
| 20080315351 | Kakehata | Dec 2008 | A1 |
| 20090001469 | Yoshida et al. | Jan 2009 | A1 |
| 20090001504 | Takei et al. | Jan 2009 | A1 |
| 20090016716 | Ishida | Jan 2009 | A1 |
| 20090032899 | Irie | Feb 2009 | A1 |
| 20090039918 | Madurawe | Feb 2009 | A1 |
| 20090052827 | Durfee et al. | Feb 2009 | A1 |
| 20090055789 | McIlrath | Feb 2009 | A1 |
| 20090061572 | Hareland et al. | Mar 2009 | A1 |
| 20090064058 | McIlrath | Mar 2009 | A1 |
| 20090066365 | Solomon | Mar 2009 | A1 |
| 20090066366 | Solomon | Mar 2009 | A1 |
| 20090070727 | Solomon | Mar 2009 | A1 |
| 20090079000 | Yamasaki et al. | Mar 2009 | A1 |
| 20090081848 | Erokhin | Mar 2009 | A1 |
| 20090087759 | Matsumoto et al. | Apr 2009 | A1 |
| 20090096009 | Dong et al. | Apr 2009 | A1 |
| 20090096024 | Shingu et al. | Apr 2009 | A1 |
| 20090115042 | Koyanagi | May 2009 | A1 |
| 20090128189 | Madurawe et al. | May 2009 | A1 |
| 20090134397 | Yokoi et al. | May 2009 | A1 |
| 20090144669 | Bose et al. | Jun 2009 | A1 |
| 20090144678 | Bose et al. | Jun 2009 | A1 |
| 20090146172 | Pumyea | Jun 2009 | A1 |
| 20090159870 | Lin et al. | Jun 2009 | A1 |
| 20090160482 | Karp et al. | Jun 2009 | A1 |
| 20090161401 | Bilger et al. | Jun 2009 | A1 |
| 20090179268 | Abou-Khalil et al. | Jul 2009 | A1 |
| 20090194152 | Liu et al. | Aug 2009 | A1 |
| 20090194768 | Leedy | Aug 2009 | A1 |
| 20090204933 | Rezgui | Aug 2009 | A1 |
| 20090212317 | Kolodin et al. | Aug 2009 | A1 |
| 20090218627 | Zhu | Sep 2009 | A1 |
| 20090221110 | Lee et al. | Sep 2009 | A1 |
| 20090224364 | Oh et al. | Sep 2009 | A1 |
| 20090234331 | Langereis et al. | Sep 2009 | A1 |
| 20090236749 | Otremba et al. | Sep 2009 | A1 |
| 20090242893 | Tomiyasu | Oct 2009 | A1 |
| 20090250686 | Sato et al. | Oct 2009 | A1 |
| 20090262583 | Lue | Oct 2009 | A1 |
| 20090263942 | Ohnuma et al. | Oct 2009 | A1 |
| 20090267233 | Lee | Oct 2009 | A1 |
| 20090272989 | Shum et al. | Nov 2009 | A1 |
| 20090290434 | Kurjanowicz | Nov 2009 | A1 |
| 20090302387 | Joshi et al. | Dec 2009 | A1 |
| 20090302394 | Fujita | Dec 2009 | A1 |
| 20090309152 | Knoefler et al. | Dec 2009 | A1 |
| 20090321830 | Maly | Dec 2009 | A1 |
| 20090321853 | Cheng | Dec 2009 | A1 |
| 20090321948 | Wang et al. | Dec 2009 | A1 |
| 20090325343 | Lee | Dec 2009 | A1 |
| 20100001282 | Mieno | Jan 2010 | A1 |
| 20100025766 | Nuttinck et al. | Feb 2010 | A1 |
| 20100031217 | Sinha et al. | Feb 2010 | A1 |
| 20100038743 | Lee | Feb 2010 | A1 |
| 20100052134 | Werner et al. | Mar 2010 | A1 |
| 20100058580 | Yazdani | Mar 2010 | A1 |
| 20100081232 | Furman et al. | Apr 2010 | A1 |
| 20100112753 | Lee | May 2010 | A1 |
| 20100112810 | Lee et al. | May 2010 | A1 |
| 20100123202 | Hofmann | May 2010 | A1 |
| 20100133695 | Lee | Jun 2010 | A1 |
| 20100133704 | Marimuthu et al. | Jun 2010 | A1 |
| 20100137143 | Rothberg et al. | Jun 2010 | A1 |
| 20100190334 | Lee | Jul 2010 | A1 |
| 20100193884 | Park et al. | Aug 2010 | A1 |
| 20100193964 | Farooq et al. | Aug 2010 | A1 |
| 20100224915 | Kawashima et al. | Sep 2010 | A1 |
| 20100276662 | Colinge | Nov 2010 | A1 |
| 20100307572 | Bedell et al. | Dec 2010 | A1 |
| 20100308211 | Cho et al. | Dec 2010 | A1 |
| 20100308863 | Gliese et al. | Dec 2010 | A1 |
| 20110001172 | Lee | Jan 2011 | A1 |
| 20110003438 | Lee | Jan 2011 | A1 |
| 20110024724 | Frolov et al. | Feb 2011 | A1 |
| 20110026263 | Xu | Feb 2011 | A1 |
| 20110037052 | Schmidt et al. | Feb 2011 | A1 |
| 20110042696 | Smith et al. | Feb 2011 | A1 |
| 20110050125 | Medendorp et al. | Mar 2011 | A1 |
| 20110053332 | Lee | Mar 2011 | A1 |
| 20110101537 | Barth et al. | May 2011 | A1 |
| 20110102014 | Madurawe | May 2011 | A1 |
| 20110143506 | Lee | Jun 2011 | A1 |
| 20110147791 | Norman et al. | Jun 2011 | A1 |
| 20110221022 | Toda | Sep 2011 | A1 |
| 20110241082 | Bernstein et al. | Oct 2011 | A1 |
| 20110284992 | Zhu | Nov 2011 | A1 |
| 20110286283 | Lung et al. | Nov 2011 | A1 |
| 20120001184 | Ha et al. | Jan 2012 | A1 |
| 20120003815 | Lee | Jan 2012 | A1 |
| 20120013013 | Sadaka et al. | Jan 2012 | A1 |
| 20120074466 | Setiadi et al. | Mar 2012 | A1 |
| 20120178211 | Hebert | Jul 2012 | A1 |
| 20120181654 | Lue | Jul 2012 | A1 |
| 20120182801 | Lue | Jul 2012 | A1 |
| Number | Date | Country |
|---|---|---|
| 1267594 | Dec 2002 | EP |
| 1909311 | Apr 2008 | EP |
| PCTUS2008063483 | May 2008 | WO |
| Entry |
|---|
| Uchikoga, S., et al., “Low temperature poly-Si TFT-LCD by excimer laser anneal,” Thin Solid Films, vol. 383 (2001), pp. 19-24. |
| He, M., et al., “Large Polycrystalline Silicon Grains Prepared by Excimer Laser Crystallization of Sputtered Amorphous Silicon Film with Process Temperature at 100 C,” Japanese Journal of Applied Physics, vol. 46, No. 3B, 2007, pp. 1245-1249. |
| Kim, S.D., et al., “Advanced source/drain engineering for box-shaped ultra shallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS,” IEEE Trans. Electron Devices, vol. 49, No. 10, pp. 1748-1754, Oct. 2002. |
| Ahn, J., et al., “High-quality MOSFET's with ultrathin LPCVD gate SiO2,” IEEE Electron Device Lett., vol. 13, No. 4, pp. 186-188, Apr. 1992. |
| Agarwal, A., et al., “Efficient production of silicon-on-insulator films by co-implantation of He+ with H+” Applied Physics Letters, vol. 72, No. 9, Mar. 1998, pp. 1086-1088. |
| Cook III, G. O., et al., “Overview of transient liquid phase and partial transient liquid phase bonding,” Journal of Material Science, vol. 46, 2011, pp. 5305-5323. |
| Moustris, G. P., et al., “Evolution of autonomous and semi-autonomous robotic surgical systems: A review of the literature,” International Journal of Medical Robotics and Computer Assisted Surgery, Wiley Online Library, 2011, DOI: 10.10002/rcs.408. |
| Subbarao, M., et al., “Depth from Defocus: A Spatial Domain Approach,” International Journal of Computer Vision, vol. 13, No. 3, pp. 271-294 (1994). |
| Subbarao, M., et al., “Focused Image Recovery from Two Defocused Images Recorded with Different Camera Settings,” IEEE Transactions on Image Processing, vol. 4, No. 12, Dec. 1995, pp. 1613-1628. |
| Guseynov, N. A., et al., “Ultrasonic Treatment Restores the Photoelectric Parameters of Silicon Solar Cells Degraded under the Action of 60Cobalt Gamma Radiation,” Technical Physics Letters, vol. 33, No. 1, pp. 18-21 (2007). |
| Gawlik, G., et al., “GaAs on Si: towards a low-temperature “smart-cut” technology”, Vacuum, vol. 70, pp. 103-107 (2003). |
| Weldon, M. K., et al., “Mechanism of Silicon Exfoliation Induced by Hydrogen/Helium Co-implantation,” Applied Physics Letters, vol. 73, No. 25, pp. 3721-3723 (1998). |
| Batude, P., et al., “Demonstration of low temperature 3D sequential FDSOI integration down to 50nm gate length,” 2011 Syposim on VLSI Technology Digest of Technical Papers, pp. 158-159. |
| Miller, D.A.B., “Optical interconnects to electronic chips,” Applied Optics, vol. 49, No. 25, Sep. 1, 2010, pp. F59-F70. |
| En, W. G., et al., “The Genesis Process”: A New SOI wafer fabrication method, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 163-164. |
| U.S. Appl. No. 12/901,890, filed Oct. 11, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/897,538, filed Oct. 4, 2010, Widjaja, et al. |
| U.S. Appl. No. 12/900,379, filed Apr. 21, 2011, Or-Bach et al. |
| U.S. Appl. No. 12/904,119, filed Oct. 13, 2010, Or-Bach, et al. |
| U.S. Appl. No. 12/577,532, filed Oct. 12, 2009, Or-Bach et al. |
| U.S. Appl. No. 12/423,214, filed Apr. 13, 2009. Or-Bach. |
| U.S. Appl. No. 12/706,520, filed Feb. 16, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/792,673, filed Jun. 2, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/797,493, filed Jun., 9, 2010, Or-Bach. |
| U.S. Appl. No. 12/847,911, filed Jun. 30, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/849,272, filed Aug. 3, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/859,665, filed Aug. 19, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/901,902, filed Oct. 11, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/949,617, filed Nov. 18, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/970,602, filed Dec. 16, 2010, Or-Bach et al. |
| U.S. Appl. No. 13/016,313, filed Jan. 28, 2011, Or-Bach et al. |
| U.S. Appl. No. 13/073,188, filed Mar. 28, 2011, Or-Bach et al. |
| U.S. Appl. No. 13/073,268, filed Mar. 28, 2011, Or-Bach et al. |
| U.S. Appl. No. 13/083,802, filed Apr. 11, 2011, Or-Bach et al. |
| U.S. Appl. No. 12/894,235, filed Sep. 30, 2010, Cronquist et al. |
| U.S. Appl. No. 12/904,114, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/963,659, filed Dec. 9, 2010, Or-Bach et al. |
| U.S. Appl. No. 13/041,404, filed Mar. 6, 2011, Or-Bach et al. |
| U.S. Appl. No. 12/951,913, filed Nov. 22, 2010, Or-Bach et al. |
| U.S. Appl. No. 13/099,010, filed May 2, 2011, Or-Bach et al. |
| U.S. Appl. No. 12/903,862, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/903,847, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/904,103, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/894,252, filed Sep. 30, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/904,108, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/941,073, filed Nov. 7, 2010, Or-Bach. |
| U.S. Appl. No. 12/941,074, filed Nov. 7, 2010, Or-Bach et al. |
| U.S. Appl. No. 12/941,075, filed Nov. 7, 2010, Or-Bach. |
| U.S. Appl. No. 12/951,924, filed Nov. 22, 2010, Or-Bach et al. |
| U.S. Appl. No. 13/041,406, filed Mar. 6, 2011, Or-Bach et al. |
| U.S. Appl. No. 13/098,997, filed May 2, 2011, Or-Bach et al. |
| U.S. Appl. No. 12/904,124, filed Oct. 13, 2010, Or-Bach et al. |
| U.S. Appl. No. 13/041,405, filed Mar. 6, 2011, Or-Bach et al. |
| Colinge, J. P., et al., “Nanowire transistors without Junctions”, Nature Nanotechnology, Feb. 21, 2010, pp. 1-5. |
| Kim, J.Y., et al., “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 11-12, Jun. 10-12, 2003. |
| Kim, J.Y., et al., “The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond,” 2005 IEEE VLSI-TSA International Symposium, pp. 33-34, Apr. 25-27, 2005. |
| Abramovici, Breuer and Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990, pp. 432-447. |
| Topol, A.W., et al., “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM Tech. Digest, Dec. 5, 2005, pp. 363-366. |
| Demeester, P. et al., “Epitaxial lift-off and its applications,” Semicond. Sci. Technol., 1993, pp. 1124-1135, vol. 8. |
| Yoon, J., et al., “GaAs Photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies”, Nature, vol. 465, May 20, 2010, pp. 329-334. |
| Yonehara, T., et al., “ELTRAN: SOI-Epi Wafer by Epitaxial Layer transfer from porous Silicon”, The 198th Electrochemical Society Meeting, abstract No. 438 (2000). |
| Yonehara, T. et al., “Eltran®, Novel SOI Wafer Technology,” JSAP International, Jul. 2001, pp. 10-16, No. 4. |
| Suk, S. D., et al., “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” in Proc. IEDM Tech. Dig., 2005, pp. 717-720. |
| Bangsaruntip, S., et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” Electron Devices Meeting (IEDM), 2009 IEEE International , vol., No., pp. 297-300, Dec. 7-9, 2009. |
| Bakir and Meindl, “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009, Chapter 13, pp. 389-419. |
| Tanaka, H., et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” VLSI Technology, 2007 IEEE Symposium on , vol., No., pp. 14-15, Jun. 12-14, 2007. |
| Burr, G. W., et al., “Overview of candidate device technologies for storage-class memory,” IBM Journal of Research and Development, vol. 52, No. 4.5, pp. 449-464, Jul. 2008. |
| Lue, H.-T., et al., “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010, pp. 131-132. |
| Bez, R., et al., “Introduction to Flash memory,” Proceedings IEEE, 91(4), 489-502 (2003). |
| Kim, W., et al., “Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage”, Symposium on VLSI Technology Digest of Technical Papers, 2009, pp. 188-189. |
| Auth, C., et al., “45nm High-k + Metal Gate Strain-Enhanced Transistors,” Symposium on VLSI Technology Digest of Technical Papers, 2008, pp. 128-129. |
| Jan, C. H., et al., “A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications,” IEEE International Electronic Devices Meeting (IEDM), Dec. 7-9, 2009, pp. 1-4. |
| Mistry, K., “A 45nm Logic Technology With High-K+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-Free Packaging,” Electron Devices Meeting, 2007, IEDM 2007, IEEE International, Dec. 10-12, 2007, p. 247. |
| Ragnarsson, L., et al., “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization,” IEDM Tech. Dig., pp. 663-666, 2009. |
| Sen, P & Kim, C.J., “A Fast Liquid-Metal Droplet Microswitch Using EWOD-Driven Contact-Line Sliding”, Journal of Microelectromechanical Systems, vol. 18, No. 1, Feb. 2009, pp. 174-185. |
| Iwai, H., et al., “NiSi Salicide Technology for Scaled CMOS,” Microelectronic Engineering, 60 (2002), pp. 157-169. |
| Froment, B., et al., “Nickel vs. Cobalt Silicide integration for sub-50nm CMOS”, IMEC ESS Circuits, 2003. pp. 215-219. |
| James, D., “65 and 45-nm Devices—an Overview”, Semicon West, Jul. 2008, ctr—024377. |
| Davis, J.A., et al., “Interconnect Limits on Gigascale Integration(GSI) in the 21st Century”, Proc. IEEE, vol. 89, No. 3, pp. 305-324, Mar. 2001. |
| Dicioccio, L., et al., “Direct bonding for wafer level 3D integration”, ICICDT 2010, pp. 110-113. |
| Shino, T., et al., “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” Electron Devices Meeting, 2006, IEDM '06, International , vol., No., pp. 1-4, Dec. 11-13, 2006. |
| Hamamoto, T., et al., “Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond”, Solid-State Electronics, vol. 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research Conference—ESSDERC'08, Jul. 2009, pp. 676-683. |
| Okhonin, S., et al., “New Generation of Z-RAM”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 925-928, Dec. 10-12, 2007. |
| Kim, W., et al., “Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage,” Symposium on VLSI Technology, 2009, pp. 188-189. |
| Walker, A. J., “Sub-50nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, No. 11, pp. 2703-2710, Nov. 2009. |
| Hubert, A., et al., “A Stacked SONOS Technology, Up to 4 Levels and 6nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009, pp. 637-640. |
| Celler, G.K. et al., “Frontiers of silicon-on-insulator,” J. App. Phys., May 1, 2003, pp. 4955-4978, vol. 93, No. 9. |
| Henttinen, K. et al., “Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers,” Applied Physics Letters, Apr. 24, 2000, p. 2370-2372, vol. 76, No. 17. |
| Lee, C.-W., et al., “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, pp. 053511-1 to 053511-2, 2009. |
| Park, S. G., et al., “Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate,” International Electron Devices Meeting, IEDM 2004, pp. 515-518, Dec. 13-15, 2004. |
| Kim, J.V., et al., “S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005 pp. 34- 35, Jun. 14-16, 2005. |
| Oh, H.J., et al., “High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond,” Solid-State Device Research Conference, ESSDERC 2005. Proceedings of 35th European , pp. 177-180, Sep. 12-16, 2005. |
| Chung, S.-W., et al., “Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology,” 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 32-33. |
| Lee, M. J., et al., “A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor,” IEEE Transactions on Electron Devices, vol. 54, No. 12, pp. 3325-3335, Dec. 2007. |
| Henttinen, K. et al., “Cold ion-cutting of hydrogen implanted Si,” J. Nucl. Instr. and Meth. in Phys. Res. B, 2002, pp. 761-766, vol. 190. |
| Brumfiel, G., “Solar cells sliced and diced”, May 19, 2010, Nature News. |
| Dragoi, et al., “Plasma-activated wafer bonding: the new low-temperature tool for MEMS fabrication”, Proc. SPIE, vol. 6589, 65890T (2007). |
| Rajendran, B., et al., “Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures”, proceedings VMIC 2004. |
| Rajendran, B., “Sequential 3D IC Fabrication: Challenges and Prospects”, Proceedings of VMIC 2006. |
| Jung, S.-M., et al., “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16um2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM,” VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on , vol., No., pp. 228-229, Jun. 15-17, 2004. |
| Vengurlekar, A., et al., “Mechanism of Dopant Activation Enhancement in Shallow Junctions by Hydrogen”, Proceedings of the Materials Research Society, vol. 864, Spring 2005, E9.28.1-6. |
| Hui, K. N., et al., “Design of vertically-stacked polychromatic light-emitting diodes,” Optics Express, Jun. 8, 2009, pp. 9873-9878, vol. 17, No. 12. |
| Yamada, M. et al., “Phosphor Free High-Luminous-Efficiency White Light-Emitting Diodes Composed of InGaN Multi-Quantum Well,” Japanese Journal of Applied Physics, 2002, pp. L246-L248, vol. 41. |
| Guo, X. et al., “Cascade single-chip phosphor-free white light emitting diodes,” Applied Physics Letters, 2008, pp. 013507-1-013507-3, vol. 92. |
| Chuai, D. X., et al., “A Trichromatic Phosphor-Free White Light-Emitting Diode by Using Adhesive Bonding Scheme,” Proc. SPIE, 2009, vol. 7635. |
| Suntharalingam, V. et al., “Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology,” Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, Aug. 29, 2005, pp. 356-357, vol. 1. |
| Coudrain, P. et al., “Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully-Depleted SOI Transistors,” IEDM, 2008, pp. 1-4. |
| Takafuji, Y. et al., “Integration of Single Crystal Si TFTs and Circuits on a Large Glass Substrate,” IEEE International Electron Devices Meeting (IEDM), Dec. 7-9, 2009, pp. 1-4. |
| Flamand, G. et al.; “Towards Highly Efficient 4-Terminal Mechanical Photovoltaic Stacks,” III-Vs Review, Sep.-Oct. 2006, pp. 24-27, vol. 19, Issue 7. |
| Zahler, J.M. et al., “Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells,” Photovoltaic Specialists Conference, Conference Record of the Twenty-Ninth IEEE, May 19-24, 2002, pp. 1039-1042. |
| Wierer, J.J. et al., “High-power AlGaInN flip-chip light-emitting diodes,” Applied Physics Letters, May 28, 2001, pp. 3379-3381, vol. 78, No. 22. |
| El-Gamal, A., “Trends in CMOS Image Sensor Technology and Design,” International Electron Devices Meeting Digest of Technical Papers, Dec. 2002. |
| Ahn, S.W., “Fabrication of a 50 nm half-pitch wire grid polarizer using nanoimprint lithography,” Nanotechnology, 2005, pp. 1874-1877, vol. 16, No. 9. |
| Johnson, R.C., “Switching LEDs on and off to enlighten wireless communications,” EE Times, Jun. 2010, <http://www.embeddedinternetdesign.com/design/225402094>. |
| Ohsawa, et al., “Autonomous Refresh of Floating Body Cell (FBC)”, International Electron Device Meeting, 2008, pp. 801-804. |
| Sekar, D. C., et al, “A 3D-IC Technology with Integrated Microchannel Cooling”, Proc. Intl. Interconnect Technology Conference, 2008, pp. 13-15. |
| Brunschweiler, T., et al., “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008, pp. 1114-1125. |
| Yu, H., et al., “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 14, No. 3, Article 41, May 2009, pp. 41.1-41.31. |
| Chen, P., et al., “Effects of Hydrogen Implantation Damage on the Performance of InP/InGaAs/InP p-i-n Photodiodes, Transferred on Silicon,” Applied Physics Letters, vol. 94, No. 1, Jan. 2009, pp. 012101-1 to 012101-3. |
| Lee, D., et al., “Single-Crystalline Silicon Micromirrors Actuated by Self-Aligned Vertical Electrostatic Combdrives with Piston-Motion and Rotation Capability,” Sensors and Actuators A114, 2004, pp. 423-428. |
| Shi, X., et al., “Characterization of Low-Temperature Processed Single-Crystalline Silicon Thin-Film Transistor on Glass,” IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 574-576. |
| Chen, W., et al., “InP Layer Transfer with Masked Implantation,” Electrochemical and Solid-State Letters, Issue 12, No. 4, Apr. 2009, H149-H150. |
| Motoyoshi, M., “3D-IC Integration,” 3rd Stanford and Tohoku University Joint Open Workshop, Dec. 4, 2009, pp. 1-52. |
| Wong, S., et al., “Monolithic 3D Integrated Circuits,” VLSI Technology, Systems and Applications, 2007, International Symposium on VLSI-TSA 2007, pp. 1-4. |
| Feng, J., et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” IEEE Electron Device Letters, vol. 27, No. 11, Nov. 2006, pp. 911-913. |
| Zhang, S., et al., “Stacked CMOS Technology on SOI Substrate,” IEEE Electron Device Letters, vol. 25, No. 9, Sep. 2004, pp. 661-663. |
| Batude, P., et al., “Advances in 3D CMOS Sequential Integration,” 2009 IEEE International Electron Devices Meeting (Baltimore, Maryland), Dec. 7-9, 2009, pp. 345-348. |
| Tan, C.S., et al., “Wafer Level 3-D ICs Process Technology,” ISBN-10: 0387765328, Springer, 1st Ed., Sep. 19, 2008, pp. v-xii, 34, 58, and 59. |
| Yoon, S.W. et al., “Fabrication and Packaging of Microbump Interconnections for 3D TSV,” IEEE International Conference on 3D System Integration (3DIC), Sep. 28-30, 2009, pp. 1-5. |
| Franzon, P.D. et al., “Design and CAD for 3D Integrated Circuits,” 45th ACM/IEEE Design, Automation Conference (DAC), Jun. 8-13, 2008, pp. 668-673. |
| Brebner, G., “Tooling up for Reconfigurable System Design,” IEE Colloquium on Reconfigurable Systems, 1999, Ref. No. 1999/061, pp. 2/1-2/4. |
| Lajevardi, P., “Design of a 3-Dimension FPGA,” Thesis paper, University of British Columbia, Submitted to Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Jul. 2005, pp. 1-71. |
| Bae, Y.-D., “A Single-Chip Programmable Platform Based on a Multithreaded Processor and Configurable Logic Clusters,” 2002 IEEE International Solid-State Circuits Conference, Feb. 3-7, 2002, Digest of Technical Papers, ISSCC, vol. 1, pp. 336-337. |
| Dong, C. et al., “Reconfigurable Circuit Design with Nanomaterials,” Design, Automation & Test in Europe Conference & Exhibition, Apr. 20-24, 2009, pp. 442-447. |
| Razavi, S.A., et al., “A Tileable Switch Module Architecture for Homogeneous 3D FPGAs,” IEEE International Conference on 3D System Integration (3DIC), Sep. 28-30, 2009, 4 pages. |
| Bakir M., et al., “3D Device-Stacking Technology for Memory,” pp. 407-410, 2009. |
| Lu, N.C.C., et al., “A Buried-Trench DRAM Cell Using a Self-aligned Epitaxy Over Trench Technology,” Electron Devices Meeting, IEDM '88 Technical Digest, International, 1988, pp. 588-591. |
| Valsamakis, E.A., “Generator for a Custom Statistical Bipolar Transistor Model,” IEEE Journal of Solid-State Circuits, Apr. 1985, pp. 586-589, vol. SC-20, No. 2. |
| Srivastava, P. et al., “Silicon Substrate Removal of GaN DHFETs for enhanced (>1100V) Breakdown Voltage,” Aug. 2010, IEEE Electron Device Letters, vol. 31, No. 8, pp. 851-852. |
| Weis, M. et al., “Stacked 3-Dimensional 6T SRAM Cell with Independent Double Gate Transistors,” IC Design and Technology, May 18-20, 2009. |
| Doucette, P., “Integrating Photonics: Hitachi, Oki Put LEDs on Silicon,” Solid State Technology, Jan. 2007, p. 22, vol. 50, No. 1. |
| Gosele, U., et al., “Semiconductor Wafer Bonding,” Annual Review of Materials Science, Aug. 1998, pp. 215-241, vol. 28. |
| Spangler, L.J. et al., “A Technology for High Performance Single-Crystal Silicon-on-Insulator Transistors,” IEEE Electron Device Letters, Apr. 1987, pp. 137-139, vol. 8, No. 4. |
| Luo, Z.S. et al., “Enhancement of (In, Ga)N Light-emitting Diode Performance by Laser Liftoff and Transfer from Sapphire to Silicon,” Photonics Technology Letters, Oct. 2002, pp. 1400-1402, vol. 14, No. 10. |
| Zahler, J.M. et al., “Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells,” NCPV and Solar Program Review Meeting, 2003, pp. 723-726. |
| Larrieu, G., et al., “Low Temperature Implementation of Dopant-Segregated Band-edger Metallic S/D junctions in Thin-Body SOI p-MOSFETs”, Proceedings IEDM, 2007, pp. 147-150. |
| Qui, Z., et al., “A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering”, IEEE Transactions on Electron Devices, vol. 55, No. 1, Jan. 2008, pp. 396-403. |
| Khater, M.H., et al., “High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length”, IEEE Electron Device Letters, vol. 31, No. 4, Apr. 2010, pp. 275-277. |
| Abramovici, M., “In-system silicon validation and debug”, (2008) IEEE Design and Test of Computers, 25 (3), pp. 216-223. |
| Saxena, P., et al., “Repeater Scaling and Its Impact on CAD”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 4, Apr. 2004. |
| Abrmovici, M., et al., A reconfigurable design-for-debug infrastructure for SoCs, (2006) Proceedings—Design Automation Conference, pp. 7-12. |
| Anis, E., et al., “Low cost debug architecture using lossy compression for silicon debug”, (2007) Proceedings of the IEEE/ACM Design, pp. 225-230. |
| Anis, E., et al., “On using lossless compression of debug data in embedded logic analysis”, (2007) Proceedings of the IEEE International Test Conference, paper 18.3, pp. 1-10. |
| Boule, M., et al., “Adding debug enhancements to assertion checkers for hardware emulation and silicon debug”, (2006) Proceedings of the IEEE International Conference on Computer Design, pp. 294-299. |
| Boule, M., et al., “Assertion checkers in verification, silicon debug and in-field diagnosis”, (2007) Proceedings—Eighth International Symposium on Quality Electronic Design, ISQED 2007, pp. 613-618. |
| Burtscher, M., et al., “The VPC trace-compression algorithms”, (2005) IEEE Transactions on Computers, 54 (11), Nov. 2005, pp. 1329-1344. |
| Frieden, B., “Trace port on powerPC 405 cores”, (2007) Electronic Product Design, 28 (6), pp. 12-14. |
| Hopkins, A.B.T., et al., “Debug support for complex systems on-chip: A review”, (2006) IEEE Proceedings: Computers and Digital Techniques, 153 (4), Jul. 2006, pp. 197-207. |
| Hsu, Y.-C., et al., “Visibility enhancement for silicon debug”, (2006) Proceedings—Design Automation Conference, Jul. 24-28, 2006, San Francisco, pp. 13-18. |
| Josephson, D., et al., “The crazy mixed up world of silicon debug”, (2004) Proceedings of the Custom Integrated Circuits Conference, paper 30-1, pp. 665-670. |
| Josephson, D.D., “The manic depression of microprocessor debug”, (2002) IEEE International Test Conference (TC), paper 23.4, pp. 657-663. |
| Ko, H.F., et al., “Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug”, (2009) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28 (2), pp. 285-297. |
| Ko, H.F., et al., “Distributed embedded logic analysis for post-silicon validation of SOCs”, (2008) Proceedings of the IEEE International Test Conference, paper 16.3, pp. 755-763. |
| Ko, H.F., et al., “Functional scan chain design at RTL for skewed-load delay fault testing”, (2004) Proceedings of the Asian Test Symposium, pp. 454-459. |
| Ko, H.F., et al., “Resource-efficient programmable trigger units for post-silicon validation”, (2009) Proceedings of the 14th IEEE European Test Symposium, ETS 2009, pp. 17-22. |
| Liu, X., et al., “On reusing test access mechanisms for debug data transfer in SoC post-silicon validation”, (2008) Proceedings of the Asian Test Symposium, pp. 303-308. |
| Liu, X., et al., “Trace signal selection for visibility enhancement in post-silicon validation”, (2009) Proceedings Date, pp. 1338-1343. |
| Mclaughlin, R., et al., “Automated debug of speed path failures using functional tests”, (2009) Proceedings of the IEEE VLSI Test Symposium, pp. 91-96. |
| Morris, K., “On-Chip Debugging—Built-in Logic Analyzers on your FPGA”, (2004) Journal of FPGA and Structured ASIC, 2 (3). |
| Nicolici, N., et al., “Design-for-debug for post-silicon validation: Can high-level descriptions help?”, (2009) Proceedings—IEEE International High-Level Design Validation and Test Workshop, HLDVT, pp. 172-175. |
| Park, S.-B., et al., “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization”, (2008) Design Automation Conference (DAC08), Jun. 8-13, 2008, Anaheim, CA, USA, pp. 373-378. |
| Park, S.-B., et al., “Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)”, (2009) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28 (10), pp. 1545-1558. |
| Moore, B., et al., “High Throughput Non-contact SiP Testing”, (2007) Proceedings—International Test Conference, paper 12.3. |
| Riley, M.W., et al., “Cell broadband engine debugging for unknown events”, (2007) IEEE Design and Test of Computers, 24 (5), pp. 486-493. |
| Vermeulen, B., “Functional debug techniques for embedded systems”, (2008) IEEE Design and Test of Computers, 25 (3), pp. 208-215. |
| Vermeulen, B., et al., “Automatic Generation of Breakpoint Hardware for Silicon Debug”, Proceeding of the 41st Design Automation Conference, Jun. 7-11, 2004, p. 514-517. |
| Vermeulen, B., et al., “Design for debug: Catching design errors in digital chips”, (2002) IEEE Design and Test of Computers, 19 (3), pp. 37-45. |
| Vermeulen, B., et al., “Core-based scan architecture for silicon debug”, (2002) IEEE International Test Conference (TC), pp. 638-647. |
| Vanrootselaar, G. J., et al., “Silicon debug: scan chains alone are not enough”, (1999) IEEE International Test Conference (TC), pp. 892-902. |
| Kada, M., “Updated results of R&D on functionally innovative 3D-integrated circuit (dream chip) technology in FY2009”, (2010) International Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings. |
| Kada, M., “Development of functionally innovative 3D-integrated circuit (dream chip) technology / high-density 3D-integration technology for multifunctional devices”, (2009) IEEE International Conference on 3D System Integration, 3DIC 2009. |
| Kim, G.-S., et al., “A 25-mV-sensitivity 2-Gb/s optimum-logic-threshold capacitive-coupling receiver for wireless wafer probing systems”, (2009) IEEE Transactions on Circuits and Systems II: Express Briefs, 56 (9), pp. 709-713. |
| Marchal, P., et al., “3-D technology assessment: Path-finding the technology/design sweet-spot”, (2009) Proceedings of the IEEE, 97 (1), pp. 96-107. |
| Xie, Y., et al., “Design space exploration for 3D architectures”, (2006) ACM Journal on Emerging Technologies in Computing Systems, 2 (2), Apr. 2006, pp. 65-103. |
| Sellathamby, C.V., et al., “Non-contact wafer probe using wireless probe cards”, (2005) Proceedings—International Test Conference, 2005, pp. 447-452. |
| Souri, S., et al., “Multiple Si layers ICs: motivation, performance analysis, and design Implications”, (2000) Proceedings—Design Automation Conference, pp. 213-220. |
| Vinet, M., et.al., “3D monolithic integration: Technological challenges and electrical results”, Microelectronic Engineering Apr. 2011 vol. 88, Issue 4, pp. 331-335. |
| Bobba, S. et al., “CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits”, Asia pacific DAC 2011, paper 4A-4. |
| Choudhury, D., “3D Integration Technologies for Emerging Microsystems”, IEEE IMS 2010. |
| Lee, Y.-J., et. al, “3D 65nm CMOS with 320° C. Microwave Dopant Activation”, IEDM 2010. |
| Crnogorac, F., et al., “Semiconductor crystal islands for three-dimensional integration”, J. Vac. Sci. Technol. B 28(6), Nov./Dec. 2010, C6P53-58. |
| Park, J.-H., et al., “N-Channel Germanium MOSFET Fabricated Below 360 ° C. by Cobalt-Induced Dopant Activation for Monolithic Three-Dimensional-ICs”, IEEE Electron Device Letters, vol. 32, No. 3, Mar. 2011, pp. 234-236. |
| Jung, S.-M., et al., “Soft Error Immune 0.46pm2 SRAM Cell with MIM Node Capacitor by 65nm CMOS Technology for Ultra High Speed SRAM”, IEDM 2003, pp. 289-292. |
| Brillouet, M., “Emerging Technologies on Silicon”, IEDM 2004, pp. 17-24. |
| Jung, S.-M., et al., “Highly Area Efficient and Cost Effective Double Stacked S3( Stacked Single-crystal Si) Peripheral CMOS SSTFT and SRAM Cell Technology for 512M bit density SRAM”, IEDM 2003, pp. 265-268. |
| Joyner, J.W., “Opportunities and Limitations of Three-dimensional Integration for Interconnect Design”, PhD Thesis, Georgia Institute of Technology, Jul. 2003. |
| Choi, S.-J., “A Novel TFT with a Laterally Engineered Bandgap for of 3D Logic and Flash Memory”, 2010 Symposium of VLSI Technology Digest, pp. 111-112. |
| Meindl, J. D., “Beyond Moore's Law: The Interconnect ERA”, IEEE Computing in Science & Engineering, Jan./Feb. 2003, pp. 20-24. |
| Radu, I., et al., “Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking”, IEEE 3D Systems Integration Conference (3DIC), Nov. 16-18, 2010. |
| Gaudin, G., et al., “Low temperature direct wafer to wafer bonding for 3D integration”, 3D Systems Integration Conference (3DIC), IEEE, 2010, Munich, Nov. 16-18, 2010, pp. 1-4. |
| Jung, S.-M., et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node”, IEDM 2006, Dec. 11-13, 2006. |
| Souri, S. J., “Interconnect Performance in 3-Dimensional Integrated Circuits”, PhD Thesis, Stanford, Jul. 2003. |
| Uemoto, Y., et al., “A High-Performance Stacked-CMOS SRAM Cell by Solid Phase Growth Technique”, Symposium on VLSI Technology, 2010, pp. 21-22. |
| Jung, S.-M., et al., “Highly Cost Effective and High Performance 65nm S3( Stacked Single-crystal Si ) SRAM Technology with 25F2, 0.16um2 cell and doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications”, 2005 Symposium on VLSI Technology Digest of Technical papers, pp. 220-221 for 512M bit density SRAM, IEDM 2003, pp. 265-268. |
| Steen, S.E., et al., “Overlay as the key to drive wafer scale 3D integration”, Microelectronic Engineering 84 (2007) 1412-1415. |
| Maeda, N., et al., “Development of Sub 10- μm Ultra-Thinning Technology using Device Wafers for 3D Manufacturing of Terabit Memory”, 2010 Symposium on VLSI Technology Digest of Technical Papers, pp. 105-106. |
| Lin, X., et al., “Local Clustering 3-D Stacked CMOS Technology for Interconnect Loading Reduction”, IEEE Transactions on electron Devices, vol. 53, No. 6, Jun. 2006, pp. 1405-1410. |
| Chan, M., et al., “3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies”, IEEE Tencon, Nov. 23, 2006, Hong Kong. |
| Dong, X., et al., “Chapter 10: System-Level 3D IC Cost Analysis and Design Exploration”, in Xie, Y., et al., “Three-Dimensional Integrated Circuit Design”, book in series “Integrated Circuits and Systems” ed. A. Andrakasan, Springer 2010. |
| Naito, T., et al., “World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS”, 2010 Symposium on VLSI Technology Digest of Technical Papers, pp. 219-220. |
| Bernard, E., et al., “Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal / High-K Gate stack”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 16-17. |
| Cong, J., et al., “Quantitative Studies of Impact of 3D IC Design on Repeater Usage”, VMIC 2008. |
| Gutmann, R.J., et al., “Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals”, Journal of Semiconductor Technology and Science, vol. 4, No. 3, Sep. 2004, pp. 196-203. |
| Crnogorac, F., et al., “Nano-graphoepitaxy of semiconductors for 3D integration”, Microelectronic Engineering 84 (2007) 891-894. |
| Koyanagi, M, “Different Approaches to 3D Chips”, 3D IC Review, Stanford University, May 2005. |
| Koyanagi, M, “Three-Dimensional Integration Technology and Integrated Systems”, ASPDAC 2009 presentation. |
| Koyanagi, M., et al., “Three-Dimensional Integration Technology and Integrated Systems”, ASPDAC 2009, paper 4D-1, pp. 409-415. |
| Hayashi, Y., et al., “A New Three Dimensional IC Fabrication Technology Stacking Thin Film Dual-CMOS Layers”, IEDM 1991, paper 25.6.1, pp. 657-660. |
| Clavelier, L., et al., “Engineered Substrates for Future More Moore and More Than Moore Integrated Devices”, IEDM 2010, paper 2.6.1, pp. 42-45. |
| Kim, K., “From The Future Si Technology Perspective: Challenges and Opportunities”, IEDM 2010, pp. 1.1.1-1.1.9. |
| Ababei, C., et al., “Exploring Potential Benefits of 3D FPGA Integration”, in book by Becker, J.et al. Eds., “Field Programmable Logic 2004”, LNCS 3203, pp. 874-880, 2004, Springer-Verlag Berlin Heidelberg. |
| Ramaswami, S., “3D TSV IC Processing”, 3DIC Technology Forum Semicon Taiwan 2010, Sep. 9, 2010. |
| Davis, W.R., et al., “Demystifying 3D Ics: Pros and Cons of Going Vertical”, IEEE Design and Test of Computers, Nov.-Dec. 2005, pp. 498-510. |
| Lin, M., et al., “Performance Benefits of Monolithically Stacked 3DFPGA”, FPGA06, Feb. 22-24, 2006, Monterey, California, pp. 113-122. |
| Dong, C., et al., “Performance and Power Evaluation of a 3D CMOS/Nanomaterial Reconfigurable Architecture”, ICCAD 2007, pp. 758-764. |
| Gojman, B., et al., “3D Nanowire-Based Programmable Logic”, International Conference on Nano-Networks (Nanonets 2006), Sep. 14-16, 2006. |
| He, T., et al., “Controllable Molecular Modulation of Conductivity in Silicon-Based Devices”, J. Am. Chem. Soc. 2009, 131, 10023-10030. |
| Henley, F., “Engineered Substrates Using the Nanocleave Process”, SemiconWest, Jul. 19, 2006, San Francisco. |
| Dong, C., et al., “3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits”, IEEE Transactions on Circuits and Systems, vol. 54, No. 11, Nov. 2007, pp. 2489-2501. |
| Diamant, G., et al., “Integrated Circuits based on Nanoscale Vacuum Phototubes”, Applied Physics Letters 92, 262903-1 to 262903-3 (2008). |
| Landesberger, C., et al., “Carrier techniques for thin wafer processing”, CS MANTECH Conference, May 14-17, 2007 Austin, Texas, pp. 33-36. |
| Golshani, N., et al., “Monolithic 3D Integration of SRAM and Image Sensor Using Two Layers of Single Grain Silicon”, 2010 IEEE International 3D Systems Integration Conference (3DIC), Nov. 16-18, 2010, pp. 1-4. |
| Shen, W., et al., “Mercury Droplet Micro switch for Re-configurable Circuit Interconnect”, The 12th International Conference on Solid State Sensors, Actuators and Microsystems. Boston, Jun. 8-12, 2003, pp. 464-467. |
| Rajendran, B., et al., “Thermal Simulation of laser Annealing for 3D Integration”, Proceedings VMIC 2003. |
| Bangsaruntip, S., et al., “Gate-all-around Silicon Nanowire 25-Stage CMOS Ring Oscillators with Diameter Down to 3 nm”, 2010 Symposium on VLSI Technology Digest of papers, pp. 21-22. |
| Borland, J.O., “Low Temperature Activation of Ion Implanted Dopants: A Review”, International Workshop on Junction technology 2002, S7-3, Japan Society of Applied Physics, pp. 85-88. |
| Vengurlekar, A., et al., “Hydrogen Plasma Enhancement of Boron Activation in Shallow Junctions”, Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4052-4054. |
| El-Maleh, A. H., et al., “Transistor-Level Defect Tolerant Digital System Design at the Nanoscale”, Research Proposal Submitted to Internal Track Research Grant Programs, 2007. Internal Track Research Grant Programs. |
| Austin, T., et al., “Reliable Systems on Unreliable Fabrics”, IEEE Design & Test of Computers, Jul./Aug. 2008, dtco-25-04-aust.3d. |
| Borkar, S., “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation”, IEEE Micro, IEEE Computer Society, Nov.-Dec. 2005, pp. 10-16. |
| Zhu, S., et al., “N-Type Schottky Barrier Source/Drain MOSFET Using Ytterbium Silicide”, IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, pp. 565-567. |
| Zhang, Z., et al., “Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources,” IEEE Electron Device Letters, vol. 31, No. 7, Jul. 2010, pp. 731-733. |
| Lee, R. T.P., et al., “Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs”, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 108-109. |
| Awano, M., et al., “Advanced DSS MOSFET Technology for Ultrahigh Performance Applications”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 24-25. |
| Choi, S.-J., et al., “Performance Breakthrough in NOR Flash Memory with Dopant-Segregated Schottky-Barrier (DSSB) SONOS Devices”, 2009 Symposium of VLSI Technology Digest, pp. 222-223. |
| Zhang, M., et al., “Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs”, Proceeding of ESSDERC, Grenoble, France, 2005, pp. 457-460. |
| Larrieu, G., et al., “Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI”, IEEE Electron Device vol. 30, No. 12, Dec. 2009, 1266-1268. |
| Ko, C.H., et al., “NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications”, 2006 Symposium on VLSI Technology Digest of Technical Papers. |
| Kinoshita, A., et al., “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 168-169. |
| Kinoshita, A., et al., “High-performance 50-nm-Gate-Length Schottky-Source/Drain MOSFETs with Dopant-Segregation Junctions”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159. |
| Kaneko, A., et al., “High-Performance FinFET with Dopant-Segregated Schottky Source/Drain”, IEDM 2006. |
| Kinoshita, A., et al., “Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors”, IEDM 2006. |
| Kinoshita, A., et al., “Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs”, IEDM 2006. |
| Choi, S.-J., et al., “High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications”, 2008 IEDM, pp. 223-226. |
| Chin, Y.K., et al., “Excimer Laser-Annealed Dopant Segregated Schottky (ELA-DSS) Si Nanowire Gate-All-Around (GAA) pFET with Near Zero Effective Schottky Barrier Height (SBH)”, IEDM 2009, pp. 935-938. |
| Agoura Technologies white paper, “Wire Grid Polarizers: A New High Contrast Polarizer Technology for Liquid Crystal Displays”, 2008, pp. 1-12. |
| Unipixel Displays, Inc. white paper, “Time Multi-plexed Optical Shutter (TMOS) Displays”, Jun. 2007, pp. 1-49. |
| Woo, H.-J., et al., “Hydrogen Ion Implantation Mechanism in GaAs-on-insulator Wafer Formation by Ion-cut Process”, Journal of Semiconductor Technology and Science, vol. 6, No. 2, Jun. 2006, pp. 95-100. |
| Azevedo, I. L., et al., “The Transition to Solid-State Lighting”, Proc. IEEE, vol. 97, No. 3, Mar. 2009, pp. 481-510. |
| Crawford, M.H., “LEDs for Solid-State Lighting: Performance Challenges and Recent Advances”, IEEE Journal of Selected Topics in Quantum Electronics, vol. 15, No. 4, Jul./Aug. 2009, pp. 1028-1040. |
| Tong, Q.-Y., et al., “A “smarter-cut” approach to low temperature silicon layer transfer”, Applied Physics Letters, vol. 72, No. 1, Jan. 5, 1998, pp. 49-51. |
| Sadaka, M., et al., “Building Blocks for wafer level 3D integration”, electroiq Aug. 18, 2010. |
| Tong, Q.-Y., et al., “Low Temperature Si Layer Splitting”, Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 126-127. |
| Nguyen, P., et al., “Systematic study of the splitting kinetic of H/He co-implanted substrate”, SOI Conference, 2003, pp. 132-134. |
| Ma, X., et al., “A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding”, Semiconductor Science and Technology, vol. 21, 2006, pp. 959-963. |
| Yu, C.Y., et al., “Low-temperature fabrication and characterization of Ge-on-insulator structures”, Applied Physics Letters, vol. 89, 101913-1 to 101913-2 (2006). |
| Li, Y. A., et al., “Surface Roughness of Hydrogen Ion Cut Low Temperature Bonded Thin Film Layers”, Japan Journal of Applied Physics, vol. 39 (2000), Part 1, No. 1, pp. 275-276. |
| Hoechbauer, T., et al., “Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers”, Nuclear Instruments and Methods in Physics Research B, vol. 216 (2004), pp. 257-263. |
| Aspar, B., et al., “Transfer of structured and patterned thin silicon films using the Smart-Cut process”, Electronics Letters, Oct. 10, 1996, vol. 32, No. 21, pp. 1985-1986. |
| Demeester, P., et al., “Epitaxial lift-off and its applications,” Semicond. Sci. Technol., 1993, pp. 1124-1135, vol. 8. |
| Dicioccio, L., et. al., “Direct bonding for wafer level 3D integration”, ICICDT 2010, pp. 110-113. |
| Celler, G.K., et al., “Frontiers of silicon-on-insulator,” J. App. Phys., May 1, 2003, pp. 4955-4978, vol. 93, No. 9. |
| Rajendran, B., et al., “Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures”, proceedings VLSI Multi Level Interconnect Conference 2004, pp. 73-74. |
| Rajendran, B., “Sequential 3D IC Fabrication: Challenges and Prospects”, Proceedings of VLSI Multi Level Interconnect Conference 2006, pp. 57-64. |
| Jung, S.-M., et al., “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16um2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM,” VLSI Technology, 2004. Digest of Technical Papers, pp. 228- 229, Jun. 15-17, 2004. |
| Suntharalingam, V., et al., “Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology,” Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, Aug. 29, 2005, pp. 356-357, vol. 1. |
| Coudrain, P., et al., “Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully-Depleted SOI Transistors,” IEDM, 2008, pp. 1-4. |
| Flamand, G., et al., “Towards Highly Efficient 4-Terminal Mechanical Photovoltaic Stacks,” III-Vs Review, Sep.-Oct. 2006, pp. 24-27, vol. 19, Issue 7. |
| Zahler, J.M., et al., “Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells,” Photovoltaic Specialists Conference, Conference Record of the Twenty-Ninth IEEE, May 19-24, 2002, pp. 1039-1042. |
| Sekar, D. C., et al., “A 3D-IC Technology with Integrated Microchannel Cooling”, Proc. Intl. Interconnect Technology Conference, 2008, pp. 13-15. |
| Franzon, P.D., et al., “Design and CAD for 3D Integrated Circuits,” 45th ACM/IEEE Design, Automation Conference (DAC), Jun. 8-13, 2008, pp. 668-673. |
| Dong, C., et al., “Reconfigurable Circuit Design with Nanomaterials,” Design, Automation & Test in Europe Conference & Exhibition, Apr. 20-24, 2009, pp. 442-447. |
| Weis, M., et al., “Stacked 3-Dimensional 6T SRAM Cell with Independent Double Gate Transistors,” IC Design and Technology, May 18-20, 2009. |
| Luo, Z.S., et al., “Enhancement of (In, Ga)N Light-emitting Diode Performance by Laser Liftoff and Transfer from Sapphire to Silicon,” Photonics Technology Letters, Oct. 2002, pp. 1400-1402, vol. 14, No. 10. |
| Bobba, S., et al., “CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits”, Asia pacific DAC 2011, paper 4A-4. |
| Choudhury, D., “3D Integration Technologies for Emerging Microsystems”, IEEE Proceedings of the IMS 2010, pp. 1-4. |
| Lee, Y.-J., et. al, “3D 65nm CMOS with 320° C. Microwave Dopant Activation”, IEDM 2010, pp. 1-4. |
| Crnogorac, F., et al., “Semiconductor crystal islands for three-dimensional integration”, J. Vac. Sci. Technol. B 28(6), Nov./Dec. 2010, pp. C6P53-58. |
| Park, J.-H., et al., “N-Channel Germanium MOSFET Fabricated Below 360° C. by Cobalt-Induced Dopant Activation for Monolithic Three-Dimensional-ICs”, IEEE Electron Device Letters, vol. 32, No. 3, Mar. 2011, pp. 234-236. |
| Jung, S.-M., et al., “Highly Area Efficient and Cost Effective Double Stacked S3( Stacked Single-crystal Si) Peripheral CMOS SSTFT and SRM Cell Technology for 512M bit density SRAM”, IEDM 2003, pp. 265-268. |
| Jung, S.-M., et al., “Highly Cost Effective and High Performance 65nm S3( Stacked Single-crystal Si ) SRAM Technology with 25F2, 0.16um2 cell and doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications”, 2005 Symposium on VLSI Technology Digest of Technical papers, pp. 220-221. |
| Cong, J., et al., “Quantitative Studies of Impact of 3D IC Design on Repeater Usage”, Proceedings of International VLSI/ULSI Multilevel Interconnection Conference, pp. 344-348, 2008. |
| Sadaka, M., et al., “Building Blocks for wafer level 3D integration”, www.electroiq.com , Aug. 18, 2010, last accessed Aug. 18, 2010. |
| Madan, N., et al., “Leveraging 3D Technology for Improved Reliability,” Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), IEEE Computer Society. |
| Hayashi, Y., et al., “Fabrication of Three Dimensional IC Using “Cumulatively Bonded IC” (CUBIC) Technology”, 1990 Symposium on VLSI Technology, pp. 95-96. |
| Akasaka, Y., “Three Dimensional IC Trends,” Proceedings of the IEEE, vol. 24, No. 12, Dec. 1986. |
| Guarini, K. W., et al., “Electrical Integrity of State-of-the-Art 0.13um SOI Device and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEDM 2002, paper 16.6, pp. 943-945. |
| Kunio, T., et al., “Three Dimensional ICs, Having Four Stacked Active Device Layers,” IEDM 1989, paper 34.6, pp. 837-840. |
| Gaillardon, P-E., et al., “Can We Go Towards True 3-D Architectures?,” DAC 2011, paper 58, pp. 282-283. |
| Yun, J-G., et al., “Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory,” IEEE Transactions on Electron Devices, vol. 58, No. 4, Apr. 2011, pp. 1006-1014. |
| Kim, Y., et al., “Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline Stacked Array,” IEEE Transactions on Electron Devices, vol. 59, No. 1, Jan. 2012, pp. 35-45. |
| Goplen, B., et al., “Thermal Via Placement in 3DICs,” Proceedings of the International Symposium on Physical Design, Apr. 3-6, 2005, San Francisco. |
| Bobba, S., et al., “Performance Analysis of 3-D Monolithic Integrated Circuits,” 2010 IEEE International 3D Systems Integration Conference (3DIC), Nov. 2010, Munich, pp. 1-4. |
| Batude, P., et al., “Demonstration of low temperature 3D sequential FDSOI integration down to 50nm gate length,” 2011 Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159. |
| Batude, P., et al., “Advances, Challenges and Opportunities in 3D CMOS Sequential Integration,” 2011 IEEE International Electron Devices Meeting, paper 7.3, Dec. 2011, pp. 151-154. |
| Yun, C. H., et al., “Transfer of patterned ion-cut silicon layers”, Applied Physics Letters, vol. 73, No. 19, Nov. 1998, pp. 2772-2774. |
| Ishihara, R., et al., “Monolithic 3D-ICs with single grain Si thin film transistors,” Solid-State Electronics 71 (2012) pp. 80-87. |
| Lee, S. Y., et al., “Architecture of 3D Memory Cell Array on 3D IC,” IEEE International Memory Workshop, May 20, 2012, Monterey, CA. |
| Lee, S. Y., et al., “3D IC Architecture for High Density Memories,” IEEE International Memory Workshop, p. 1-6, May 2010. |
| Rajendran, B., et al., “CMOS transistor processing compatible with monolithic 3-D Integration,” Proceedings VMIC 2005. |
| Huet, K., “Ultra Low Thermal Budget Laser Thermal Annealing for 3D Semiconductor and Photovoltaic Applications,” NCCAVS 2012 Junction Technology Group, Semicon West, San Francisco, Jul. 12, 2012. |
| Derakhshandeh, J., et al., “A Study of the CMP Effect on the Quality of Thin Silicon Films Crystallized by Using the u-Czochralski Process,” Journal of the Korean Physical Society, vol. 54, No. 1, 2009, pp. 432-436. |
| Kim, J., et al., “A Stacked Memory Device on Logic 3D Technology for Ultra-high-density Data Storage,” Nanotechnology, vol. 22, 254006 (2011). |
| Lee, K. W., et al., “Three-dimensional shared memory fabricated using wafer stacking technology,” IEDM Tech. Dig., 2000, pp. 165-168. |
| Chen, H. Y., et al., “HfOx Based Vertical Resistive Random Access Memory for Cost Effective 3D Cross-Point Architecture without Cell Selector,” Proceedings IEDM 2012, pp. 497-499. |
| Huet, K., et al., “Ultra Low Thermal Budget Anneals for 3D Memories: Access Device Formation,” Ion Implantation Technology 2012, AIP Conf Proceedings 1496, 135-138 (2012). |
| Batude, P., et al., “3D Monolithic Integration,” ISCAS 2011 pp. 2233-2236. |
| Batude P., et al., “3D Sequential Integration: A Key Enabling Technology for Heterogeneous C-Integration of New Function With CMOS,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 2, No. 4, Dec. 2012, pp. 714-722. |
| Vinet, M., et.al., “Germanium on Insulator and new 3D architectures opportunities for integration”, International Journal of Nanotechnology, vol. 7, No. 4, pp. 304-319, Aug. 2010. |
| Kawaguchi, N., et al., “Pulsed Gren-Laser Annealing for Single-Crystalline Silicon Film Transferred onto Silicon wafer and Non-alkaline Glass by Hydrogen-Induced Exfoliation,” Japanese Journal of Appl,ied Physics, vol. 46, No. 1, 2007, pp. 21-23. |
| Yang, M., et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientation,” Proceedings IEDM 2003. |
| Yin, H., et al., “Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application,” IEEE Trans. Electron Devices, vol. 55, No. 2, pp. 578-584, Feb. 2008. |
| Number | Date | Country | |
|---|---|---|---|
| 20120193719 A1 | Aug 2012 | US |
