Patent Grant
8513061
This application claims priority to and the benefit of Korean Patent Application No. 10-2010-0131906, filed in the Korean Intellectual Property Office on Dec. 21, 2010, the entire content of which is incorporated herein by reference.
(a) Field of the Invention
The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electrical conductivity, and minimizing electrical signal delay without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.
(b) Description of the Related Art
Electronic package technology is very broad, and includes various system manufacturing technologies including all the processes from a semiconductor device to a final product. In particular, with the rapid development of electronic products, electronic package technology is a very important for achieving compactness, lightness, and high performance of devices.
Electronic package technology is also a very important technology for determining performance, size, price, reliability, etc., of final electronic products. In particular, in recent electronic products pursuing high electrical performance, subminiature/high density, low power, multi-function, ultrahigh speed signal processing, and permanent reliability, the subminiature package parts are needed as essential parts for computers, information communication devices, mobile communication devices, premium home appliances, etc.
An example of a representative technology of three-dimensionally stacking semiconductor devices including chips to connect the semiconductor devices or mount the semiconductor devices on a substrate may include wire bonding technology, flip chip technology, and through silicon via (TSV) technology.
Wire bonding technology, which is a technology of attaching and connecting a wire to a metal pad of a connection part using an ultrasonic tool, is inexpensive in view of manufacturing costs but has a limitation in connecting fine pitches and high-density electrodes due to the bonding between the wire and the metal pad, and cannot be used for parts requiring ultrahigh speed signal processing due to an increase in parasitic inductance according to an increase in the length of the signal line for electrically connecting between the connection parts.
The flip chip technology is largely divided into two, i.e., a solder flip chip using solder and a non-solder flip chip not using solder. The solder flip chip has problems in that production cost is increased due to a very complicated connection process such as solder flux application, chip/substrate alignment, solder bump reflow, flux removal, underfill filling, curing, etc. Therefore, recently, the non-solder flip chip technology has gained a large amount of interest in order to reduce the number of complicated processes.
A representative technology of the non-solder flip chip is a flip chip technology using an anisotropic conductive film (ACA). The flip chip technology using the existing ACA includes a process in which an ACA material is applied or temporarily bonded to substrates and the chips and the substrates are aligned, and heat and pressure are finally applied thereto to complete the flip chip package. However, the process has a long process time in forming a film or applying or temporarily bonding the ACA material to each substrate.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
The present invention has been made in an effort to provide a through silicon via (TSV) for 3D packaging of a semiconductor device and a method for manufacturing the same having advantages of easily aligning chips with high precision of submicrons or less as compared with the related art when self-aligning the substrates, bonding the semiconductor dies (or semiconductor chips) at a low temperature by using plasma, improving production process efficiency, having very high electrical conductivity, and minimizing electrical signal delay.
Further, the present invention has been made in an effort to provide a through silicon via (TSV) for 3D packaging of a semiconductor device and a method for manufacturing the same that are capable of simplifying production processes, improving productivity, and having uniform quality by sequentially bonding a plurality of semiconductor dies (semiconductor chips).
An exemplary embodiment of the present invention provides a method for manufacturing a through silicon via (TSV) including: preparing a substrate having a metal thin film formed in a predetermined region of the substrate; preparing a semiconductor die (or semiconductor chip) having an insulation layer formed on a side of the semiconductor die (or semiconductor chip) formed with a via hole and formed with a through via hole by back grinding the other side of the semiconductor die (or semiconductor chip); aligning the substrate formed with the metal thin film and the semiconductor die (or semiconductor chip) formed with the insulation layer; forming a seed layer on one side including the via hole of the aligned semiconductor die (or semiconductor chip); and forming an electroplating layer on a top portion of the seed layer by using electroplating, including the inside of the via hole.
During the preparation of the substrate, an oxide bonding layer having the metal thin film provided therein may be further formed, and removing a predetermined region of the oxide bonding layer on the top portion of the metal thin film may be performed.
In addition, the oxide bonding layer may be formed using a chemical vapor deposition tetraethylortho silicate (CVD TEOS) process or a spin on glass (SOG) process.
The removing of the oxide bonding layer may be performed by etching or chemical-mechanical polishing (CMP).
The aligning may include spraying moisture or appling water drop to a bonding surface between the semiconductor die (or semiconductor chip) and the substrate to form a wetting layer, and then contacting the semiconductor die (or semiconductor chip) to the substrate to be self-aligned.
The preparing of the semiconductor die (or semiconductor chip) may include first surface treatment of the bonding surface of the semiconductor die (or semiconductor chip) so that the bonding surface has a hydrophilic surface, and the preparing of the substrate may include second surface treatment of the bonding surface of the substrate so that the bonding surface has a hydrophilic surface, prior to forming the metal thin film.
Further, the first surface treatment and the second surface treatment may be plasma treatments.
After the electroplating, a plurality of semiconductor dies (or semiconductor chips) may be stacked by repeatedly performing the removing of the electroplating layer other than at a predetermined area communicating with the via hole and the preparing of the semiconductor dies (or semiconductor chip) for the electroplating.
In this case, the metal thin film may be any one selected from Cu, Ag, Au, Pt, and Al, the seed layer may be Cu, and the electroplating layer may be any one selected from Cu, W, and Al.
The through silicon via (TSV) according to the exemplary embodiment of the present invention is manufactured according to the above-mentioned manufacturing method.
According to the exemplary embodiments of the present invention, the through silicon via (TSV) for 3D packaging of a semiconductor device and the method for manufacturing the same can easily align the chips with high precision of submicrons or less as compared with the related art when self-aligning the substrates, bond the substrates at a low temperature by using plasma, improve the production process efficiency, form very high electrical conductivity, and minimize electrical signal delay.
Further, according to the exemplary embodiments of the present invention, the through silicon via (TSV) for 3D packaging of a semiconductor device and the method for manufacturing the same can simplify the production processes, improve the productivity, and have uniform quality by sequentially bonding the plurality of semiconductor dies (or semiconductor chips).
In general, the through silicon via (TSV), which is a package scheme of forming an electrode by punching a silicon wafer, has been in the limelight as a 3D packaging technology that can remarkably reduce power consumption while preventing high-frequency signal loss and seldom causes a signal delay in order to meet compactness, high speed, and low power performance objectives.
The through silicon via (TSV) is manufactured by a technology of filling via holes formed on separate silicon wafers (or chips) and then stacking the plurality of wafers (or chips) with the via holes filled.
Since the wafers with the filled via holes should be provided with bump layers for electrically connecting the wafers with each other, the manufacturing process is difficult and therefore the productivity is degraded.
Generally, when a via hole is filled by Cu electroplating, the bump layer includes a first bump layer using Cu on the top portion of the Cu layer, and a second bump layer using Sn formed on the top portion of the first bump layer.
In more detail, the method for manufacturing the through silicon via according to a conventional methode individually fills the via holes in each wafer and then stacks the wafers so that the portions where the via holes are formed correspond to each other. In this case, separate bump layers that are mechanically and electrically bonded are formed, such that the process is difficult and expensive.
Further, there is a problem in that when the plurality of wafers are stacked and bonded, each wafer essentially requires a carrier wafer, and after the bonding, a process of removing the carrier wafer is needed.
Before detailed content for implementing the present invention is described, a configuration that does not directly relate to the technical gist of the present invention is omitted in the range that deranges the technical gist of the present invention.
In addition, terms or words that are used in the present specification and claims should be understood as meanings and concepts that correspond to the technical spirit of the present invention in consideration of the principle that the concept of the term can be appropriately defined in order to describe the invention by using the best method by the inventor.
A through silicon via (TSV) 1000 for 3D packaging of a semiconductor device according to exemplary embodiments of the present invention having the above-mentioned characteristics and a method for manufacturing the same will now be described with reference to the accompanying drawings.
The method for manufacturing a through silicon via (TSV) 1000 for 3D packaging of a semiconductor device according to the exemplary embodiments of the present invention includes preparing a substrate 100 (S10), preparing a semiconductor die (or semiconductor chip) 200 (S20), aligning (S30), forming a seed layer 310 (S40), and electroplating (S50). (See
First, the preparing of the substrate 100 (S10) is a step of forming a metal thin film 110 in a predetermined region of the substrate 100 having a plate shape and that is bonded to the semiconductor die (or semiconductor chip) 200.
Thereafter, when the electroplating (S50) is completed, the metal thin film 110 has a structure that conducts the substrate 100 to the semiconductor die (or semiconductor chip) 200 and mechanically couples them.
Referring to
The oxide bonding layer 120 has a structure that may increase adhesion between the substrate 100 and the semiconductor die (or semiconductor chip) 200 while preventing insulation and metal materials from being diffused, and may be formed by using a chemical vapor deposition tetraethylorthosilicate (CVD TEOS) process or a spin on glass (SOG) method.
In more detail, as the CVD TEOS process, plasma enhanced CVD (PECVD), high density plasma CVD (HDP CVD), or sub-atmospheric CVD (SACVD) may be performed.
Thereafter, in order to contact a seed layer 310 to the metal thin film 100, the forming of the seed layer 310 (S40) and the removing of the oxide bonding layer 120 (S60) in the region in which the metal thin film 110 is formed are performed prior to the electroplating (for example, between the aligning (S30) and the forming of the seed layer 310 (S40)).
The removing of the oxide bonding layer 120 (S60) may be performed by etching or chemical-mechanical polishing.
In
The method for manufacturing a through silicon via (TSV) 1000 according to the exemplary embodiment of the present invention includes each step described above, but is not limited to the order shown in the drawings. Therefore, when the removing (S60) of the oxide bonding layer 120 is performed by the chemical-mechanical polishing, it is first performed prior to the aligning (S30), and then the aligning (S30), the forming of the seed layer 130 (S40), and the electroplating (S50) may be performed.
Referring to
The aligning (S30), which is a step of aligning the substrate 100 and the semiconductor die (or semiconductor chip) 200 prepared through the preparing of the substrate 100 (S10) and the preparing of the semiconductor die (or semiconductor chip) 200 (S20), aligns the substrate 100 formed with the metal thin film 110 and the other side of the semiconductor die (or semiconductor chip) 200 formed with the insulation layer 210 to contact each other.
In this case, the aligning (S30) may be self-alignment.
The self-alignment step includes spraying moisture or applying water drop 410 to one side of surfaces contacting each other to form a wetting layer 420 and then contacts them. In this case, the contact surface of the semiconductor die (or semiconductor chip) 200 and the substrate 100 may be subjected to the surface treatment to have a hydrophilic surface during the preparing (S20) of the semiconductor die (or semiconductor chip) 200 or the preparing (S10) of the substrate 100.
First, (a) of
The second surface treatment (S11) may be preformed by plasma-treating one side of the substrate 100, and may lower the bonding temperature between the substrate 100 and the semiconductor die (or semiconductor chip) 200 due to the oxide bonding layer 120.
That is, the atmosphere and vacuum plasma treatment may increase the hydrophilicity and may improve the adhesion by lowering the bonding temperature.
In
By performing the surface treatment as shown in
Through this, the method for manufacturing a through silicon via (TSV) 1000 according to the exemplary embodiment of the present invention self-aligns the semiconductor die (or semiconductor chip) by moving the semiconductor die (or semiconductor chip) 200 in a direction for reducing surface energy, having the wetting layer 420 between the semiconductor die (or semiconductor chip) 200 and the substrate 100, thereby making it possible to achieve the alignment at a higher speed as compared to the case of using a separate alignment device.
The forming of the seed layer 310 (S40) is a step of forming the metal thin film 110 of the substrate 100 and the seed layer 310 on the top portion of the semiconductor die (or semiconductor chip) 200 and in the region where the via hole 201 is formed, as shown in
The forming of the seed layer 310 (S40) may be performed by using deposition, and may be performed by, for example, sputtering.
The electroplating (S50) is a step of forming an electroplating layer 300 on the top portion of the seed layer 310, including the inside of the via hole 201, by using the electroplating, which is shown in
The through silicon via (TSV) 1000 for 3D packaging of a semiconductor device according to the exemplary embodiment of the present invention may be connected to a plurality of semiconductor dies (or semiconductor chips) 200 as well as having a shape shown in
Referring to
In addition, after the removing of the electroplating layer 300 (S70), the contacting of the semiconductor die (or semiconductor chip) 200 (S20) to the electroplating (S50) are performed, such that the one-layer semiconductor die (or semiconductor chip) 200 may be coupled to be stacked.
That is, the substrate 100, which is a component required for supporting the first semiconductor die (or semiconductor chip) 200, contacts the semiconductor die (or semiconductor chip) 200 to the top portion of the semiconductor die (or semiconductor chip) 200 from the stacking of the next semiconductor die (or semiconductor chip) 200.
Through this, the method for manufacturing a through silicon via (TSV) 1000 according to the exemplary embodiment of the present invention may form the through silicon via (TSV) 1000 having the multi-layer semiconductor die (or semiconductor chip) 200 in a build-up scheme of connecting the semiconductor die (or semiconductor chip) 200 through the electroplating after aligning the semiconductor die (or semiconductor chip) 200 in a multi-stage scheme.
As described above, even though the method for manufacturing a through silicon via (TSV) 1000 according to the exemplary embodiment of the present invention aligns the multi-layer semiconductor die (or semiconductor chip) 200, the semiconductor die (or semiconductor chip) 200 is separately connected by the build-up scheme, thereby making it possible to prevent the electrical connection and the mechanical adhesion from being degraded.
In addition, the method for manufacturing a through hole 1000 according to the exemplary embodiment of the present invention does not require the carrier wafer that should be provided for each semiconductor die (or semiconductor chip) 200 as compared with the method of aligning the semiconductor die (or semiconductor chip) 200 filled with the via hole 201 according to the conventional method, thereby making it possible to simplify the production processes, perform the alignment at a higher speed by using the self-alignment to increase the productivity, and produce the through silicon via (TSV) 1000 at a low cost in a short time.
While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2010-0131906 | Dec 2010 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7973411 | Borthakur | Jul 2011 | B2 |
| 20070108489 | Nagai | May 2007 | A1 |
| 20070284729 | Kwon et al. | Dec 2007 | A1 |
| 20080230912 | Lee et al. | Sep 2008 | A1 |
| 20090023243 | Koyanagi | Jan 2009 | A1 |
| 20100224977 | Kim | Sep 2010 | A1 |
| 20110133333 | Kwon et al. | Jun 2011 | A1 |
| 20110147946 | Lee et al. | Jun 2011 | A1 |
| 20120028412 | Jeong et al. | Feb 2012 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20120153496 A1 | Jun 2012 | US |
