Patent Application
20060134836
The present invention relates in general to semiconductor devices and, more particularly, to semiconductor dice housed in low profile packages.
There is a continuing demand for electronic systems with a higher functionality and smaller physical size. For example, successive generations of personal computers are specified to utilize motherboards of a decreasing while incorporating more features and operating at lower voltages but a higher power consumption. The power requirements often are met by using multiple local voltage regulators located at several locations on each motherboard.
The multiple voltage regulators typically are implemented as switching regulators that include an integrated control circuit and, to accommodate the high current levels, multiple parallel-connected discrete power switching transistors. A problem with this arrangement is that with each generation the multiple power switching transistors occupy larger portions of smaller motherboards, which reduces the area available for implementing other functions.
Some previous power transistors connect their semiconductor dice to package leads using wirebonds, but do not mount the dice on die attach flags. These devices have poor yields, and a resulting high cost, because the die is not adequately secured in position during the wirebond process. If a die moves while a wirebond is being attached, the die could
Hence, there is a need for a packaged semiconductor device that has a small physical size and high efficiency to alleviate the above mentioned problems.
In the figures, elements having the same reference number have a similar structure and functionality. Similar elements associated with a particular reference number may be described in either the plural or general sense or in the singular or specific sense, depending on the context.
Mounting tape 12 comprises a standard semiconductor package assembly tape having an adhesive surface 11 for holding mounted components in position during the assembly process. An array of holes 18 are punched or otherwise formed in tape 12 at predefined locations determined by the package size and other factors. Holes 18 may be formed in situ with a computer-controlled hole punch apparatus just prior to mounting package components, or may be purchased commercially in a pre-punched form from a tape manufacturer or vendor. Tape 12 preferably is formed with materials that can withstand the temperatures needed to complete the package assembly. For example, in one embodiment, the highest temperature occurs during the encapsulation process during which an epoxy-based or plastic mold compound is dispensed and cured at a temperature of about one hundred eighty degrees Celsius. In one embodiment, tape 12 is made of a polyester-backed acrylic adhesive and formed with holes 18 of a diameter of about one thousand five hundred micrometers. Alternatively, tape 12 may comprise silicone and/or acrylic adhesive with a polyester, polyimide or polytetrafluoroethylene (PTFE) backing. Tape 12 may also be formed with an adhesive material applied to a metal foil such as an aluminum foil.
Leadframe matrix 16 has an X-Y array of regions that define individual leadframes, including a leadframe 20 defined by singulation along cut lines 21-24 and severed after assembly to form a plurality of packaged integrated circuits or transistors. In the embodiment of
Openings 19 have a larger area than the area of semiconductor dice 14 to allow a standard pick-and-place apparatus (not shown) to mount semiconductor dice 14 directly on adhesive surface 11 within openings 19 and over holes 18. The size of openings 19 is selected taking into account the die size, the requirements of the pick-and-place apparatus and any alignment tolerance necessary for a saw or other singulation tool to avoid damaging dice 14 during the subsequent singulation process.
A vacuum pump (not shown) pulls a vacuum in a direction indicated by arrows 40 through ducts of vacuum system 42 to produce a low pressure at holes 18 for securing the positions of semiconductor dice 14 and compensating for any elasticity or movement of tape 12 during subsequent wirebonding. Once the vacuum is drawn, a wirebonding machine attaches bonding wires 35 from a top surface 43 of lead 17 to a top surface 32 of semiconductor die 14. Similar wire bonds are attached from lead 15 to top surface 32 as shown and described below.
After wirebonding, semiconductor device 10, with tape 12 attached, is placed on the floor of a molding chamber (not shown) into which is introduced a molding material 49 such as a plastic material or thermoset epoxy. Molding material 49 is formed as a continuous body that encapsulates top surfaces 32 of semiconductor dice 14, top surfaces 43 of leads 17 and the top surfaces of leads 15 (not shown in
Bottom surface 31 of semiconductor die 14 is formed during wafer processing with a solderable layer 72 for mechanically and electrically attaching to an external surface. Bottom surfaces 31, bottom surfaces 44 of leads 17 and bottom surfaces 54 of leads 15 (shown in
Note that leadframe matrix 16 is subjected to a half-etch or similar process to form mold locks 71 that prevent molding material 49 from separating from leads 15 and 17 during subsequent processing or while semiconductor device 10 is being used or operated. In one embodiment, mold locks 71 have a generally rectangular reentrant shape as shown.
Leads 15 and 17, and in fact leadframe matrix 16, are made to a thickness less than the thickness of semiconductor dice 14. For example, in one embodiment, semiconductor dice 14 have a thickness of about two hundred micrometers, while leads 15 and 17 have a thickness of about one hundred twenty-five micrometers. This thickness difference allows bonding wires 35 to be formed with a small loop height to reduce the overall thickness or height of semiconductor device 10. In an embodiment in which semiconductor dice 14 have a thickness of two hundred micrometers, the loop height is about four hundred eighty micrometers from the peak of bonding wires 35-36 to top surface 32 of semiconductor die 14, and the overall height of semiconductor device 10 is about eight hundred micrometers.
Semiconductor die 14 has a gate electrode coupled to a gate bonding pad 51 and a source electrode coupled to a source bonding pad 52, both formed on top surface 32 of semiconductor die 14. Solderable layer 72 is formed on bottom surface 31 during wafer processing to function as a drain terminal. In one embodiment, solderable layer 72 is formed with a titanium-nickel-silver alloy. Bottom surface 31 is exposed, i.e., not encapsulated by molding material 49, so solderable layer 72 allows bottom surface 31 to function as a package lead that can be attached by a solder reflow or other process for making external connections.
Where semiconductor device 10 comprises a vertical power transistor, multiple bonding wires 35 are attached in parallel between source bonding pad 52 and top surface 43 of lead 17 to reduce the on-resistance. The gate current is transient in nature and generally of a lower amplitude, so a single bonding wire 36 attached between gate bonding pad 51 and lead 15 is generally adequate to ensure a high performance.
Note that bottom surface 31 of semiconductor die 14, bottom surface 44 of lead 17 and a bottom surface 54 of lead 15 are all coplanar and exposed from molding material 49 to facilitate external connectivity.
Tabs 55-56 project from leads 15 and 17, respectively, and are remnants of the tie bar of region 29, remaining on leads 15 and 17 as artifacts of the sawing or singulation process.
The exposure of bottom surface 31 of semiconductor die 14 and the reduced loop height of bonding wires 35-36 provide package 70 of semiconductor device 10 with a low profile. In one embodiment, semiconductor device 10 has an overall height of about eight hundred micrometers.
Motherboard 60 is formed with a trace 61 to which is attached lead 17 and a trace 62 for attaching to bottom surface 31 of semiconductor die 14. In one embodiment, lead 17 and bottom surface 31 are attached to traces 61-62 by reflow soldering.
The exposure of bottom surface 31 of semiconductor die 14 results in a low thermal resistance since heat does not flow through a die attach pad and its associated metallurgical junctions as in other packaged devices. This benefit is particularly apparent in an embodiment in which a large portion of the power is generated throughout the bulk of semiconductor die 14, rather than at top surface 32.
Thermal resistance is further reduced by the low package profile of semiconductor device 10 because of the short distance from semiconductor die 14 to a top surface 65 of molding material 49. In some applications, it is advantageous to mount an external heat sink (not shown) to top surface 65 to further aid in dissipating power. Note also that trace 62 is formed to extend outwardly from semiconductor device 10. This arrangement exposes a portion of trace 62 to ambient air currents to further facilitate the removal of power PD dissipated by semiconductor device 10.
Moreover, by mounting bottom surface 31 of semiconductor die 14 directly to trace 62, the electrical resistance is reduced since the distance from trace 62 to bottom surface 31 is virtually zero. Indeed, current flows from the bulk substrate of semiconductor die 14 through solderable layer 72 directly to trace 62. Hence, current flowing through semiconductor device 10 encounters no die attach flag and flows through fewer metallurgical junctions, which results in a lower on-resistance than is the case with other devices. The lower on-resistance provides a high performance and efficiency by further reducing the dissipated power PD.
By now it can be seen that the present invention provides a packaged semiconductor device with a low profile and a low electrical and thermal resistance. A lead has a first surface for wirebonding to a first surface of a semiconductor die and a second surface substantially coplanar with a second surface of the semiconductor die. A molding material encapsulates the first surface of the semiconductor die and exposes the second surface of the semiconductor die. The semiconductor die and lead are disposed on a mounting tape to maintain their position during the packaging assembly process. The semiconductor die is secured during package assembly by positioning over a hole in the mounting tape and applying a vacuum through the hole to obviate any movement or elasticity in the mounting tape while pressure is applied to the die by the wirebonding tool during the wirebonding process.
The present invention provides a packaged semiconductor device with a high reliability and low cost. Because the semiconductor die is exposed to function as a lead, there is no die attach pad and therefore no solder reflow die attach process is needed. Hence, the semiconductor device can be assembled in a wider variety of manufacturing locations and at a lower cost. Moreover, fewer dissimilar component materials and therefore fewer dissimilar temperature coefficients of expansion within the semiconductor device. Consequently, internal stresses are reduced and reliability enhanced. Finally, the semiconductor device can be formed with a smaller footprint because there is no need to align and mount the semiconductor die on a die attach pad that is made larger to avoid die overhang.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US03/13027 | 4/29/2003 | WO | 9/9/2005 |
