Patent Application
20240071891
The present disclosure generally relates to semiconductor device assemblies, and more particularly relates to semiconductor device assemblies having face-to-face subassemblies, and methods for making the same.
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry with a high density of very small components. Typically, dies include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dies are formed, they are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
The electronics industry relies upon continuous innovation in the field of semiconductor packaging to meet the global need for higher-functioning technology. This demand calls for increasingly complicated assemblies of semiconductor devices, which may diverge in terms of plan area, thickness, connection methodology, etc. One approach to accommodate the packaging of such varied devices into a single assembly is to layer semiconductor devices into a stack. Stacks, however, have many disadvantages.
One disadvantage is the need to keep the stack thermally and mechanically stable on the substrate. At the same time, the resulting package must be as thin as possible, with die interconnections that are electrically good and reliable. Another disadvantage in die stacking is the difficulty in picking known good die (KGD) from a wafer. Including a single defective die can ‘kill’ the entire stack and result in yield losses and higher costs. Die stacking, therefore, becomes less attractive as the number of die in the stack increases and as the die involved become more expensive or complex.
To address these drawbacks and others, various embodiments of the present disclosure provide semiconductor device assemblies having face-to-face sub-assemblies.
Arranging the total number of dies provided into two separate stacks reduces the impact of including a single bad die in one of the stacks (i.e., reducing the number of wasted “good” dies), and still maintains almost an equivalent footprint as die grouped in the single stack. This modularization is achieved through the use of interconnect structures 105 and 106, which can be connected to their substrates 103 and 104, respectively. In this regard, the interconnect structures 105 and 106 may be soldered to pads located on an inside surface of their substrates 103 and 104, respectively. In addition to providing the assembly 100 with conductive paths between the subassemblies 101 and 102, the interconnect structures 105 and 106 can also provide the assembly 100 with its structural stability.
While these subassemblies 101 and 102 appear similar, in some embodiments there can exist several differences between them. Some such differences are highlighted in
Each of the subassemblies can be formed separately, encapsulated separately, and then joined together via the interconnect structures and adhesive to form a semiconductor device assembly having face-to-face sub-assemblies.
The manner in which these interconnect structures 205 and 306 are coupled is illustrated in greater detail in
Viewed from an oblique angle,
In contrast,
In other embodiments assemblies can have interconnect structures that comprise a mix of groupings. This mix can include a semiconductor device assembly that has both conductive pillars sharing a region of dielectric material along with conductive pillars possessing their own discrete regions of dielectric material, varying according to number and relative position. Additionally, although only illustrated for the first semiconductor subassembly, these same embodiments can be applied to the second semiconductor subassembly, allowing for both subassemblies to be coupled according to the embodiments of their respective interconnect structures.
Although in the foregoing example embodiment semiconductor device assemblies have been illustrated and described as including a specific number of semiconductor devices, in other embodiments assemblies can be provided with more or fewer semiconductor devices. For example, the stack of semiconductor devices illustrated in
In accordance with one aspect of the present disclosure, the semiconductor devices illustrated in the assemblies of
Any one of the semiconductor device subassemblies and semiconductor device assemblies described above with reference to
Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described above. A person skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
The devices discussed herein, including a memory device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”
As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.
It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
