Patent Grant
12170282
The present disclosure relates to a semiconductor device and a manufacturing method of the semiconductor device using a metal gate electrode.
In the related art, the integration degree of a semiconductor device has doubled every eighteen to twenty-four months according to Moore's law. However, a gate tunnel leakage current around the 90 nm node may not be disregarded, and thus a gate oxide film of MOSFET has almost completely stopped being thinned. In addition, since it is difficult to control the short channel effect, a reduction in the gate length has slowly progressed.
As a result, it is difficult to improve the performance of the MOSFET itself, engineering for mobility improvement has been performed using a mechanical stress such as DSL (Dual Stress Liner) or embedded SiGe on or beyond the 90 nm node. A mechanical stress technique considered in terms of manufacturing is substantially employed up to the 45 nm node. Beyond the 45 nm node, scaling of a gate oxide film has started to progress by heightening the dielectric constant of the gate oxide film with an HKMG structure using a high dielectric constant (HK: high-k) and metal gate (MG) electrode.
The HKMG structure is manufactured mainly using two kinds of methods such as gate-first and gate-last methods.
In the gate-first method, a poly-Si gate structure or an SiON gate insulating film structure in the related art is only replaced with the HKMG structure, and thus the structure is relatively simple.
On the other hand, in the gate-last method, a poly-Si dummy gate electrode structure which is initially formed is replaced with the HKMG structure after an interlayer insulating layer is removed (for example, refer to JP-A-2007-134432). For this reason, the manufacturing method thereof is greatly different from that of a semiconductor device in the related art. There are many cases where, in the gate-last structure, metals having different work functions are employed in the NMOS and PMOS using the same high-k (HK) insulation layer. In addition, since very fine patterns are processed, the gate length which is patterned is desired to be arranged with regularity so as to be constant for ease of manufacturing.
Here,
The semiconductor device 60 shown in
Next, a manufacturing method of the semiconductor device 60 shown in
First, as shown in
In addition, a Si3N4 layer or the like is formed using a plasma CVD method and then is etched back, thereby forming the side wall spacers 69 at the side walls of the dummy gate electrodes 71. Further, the interlayer insulating layer 64 is formed on the semiconductor base 61 so as to cover the dummy gate electrodes 71 and the side wall spacers 69, and is planarized using a CMP method.
Thereafter, as shown in
Further, as shown in
Through the above-described process, it is possible to manufacture the semiconductor device having the HKMG structure in the related art shown in
However, there are cases where the gate length is optimized with the NMOS and the PMOS in order to reduce gate capacitance in an advanced CMOS. The gate length is optimized so as to have as a small value as possible in a range allowed by the short channel effect. However, in a case of forming a very fine pattern using lithography, if the gate length of the dummy gates is different in the NMOS and the PMOS, a burden is greatly increased in the lithography process, and thus manufacturing costs are increased. In other words, it is difficult to manufacture the optimized gate length such that the patterned gate length is arranged with regularity so as to be constant.
In addition, in a planar type structure in the related art, the gate length is defined at the bottom of the gate electrode. However, in a fin structure which may be employed beyond a 22 nm generation, the shape of the gate side wall also influences the gate length. In other words, a difference occurs in the gate length in a case where the side wall of the gate electrode is tapered or in a case where roughness is present in the side wall. Particularly, the difference in the gate length is greatly problematic in the processes when an effective gate width is increased by heightening the fin.
Thus, it is desirable to provide a semiconductor device capable of optimizing the gate length in the semiconductor device having a fine structure.
An embodiment of the present disclosure is directed to a semiconductor device including gate insulating films made of a high dielectric constant material and formed on a base, metal gate electrodes formed on the gate insulating films, side wall spacers formed at side walls of the metal gate electrodes, and offset spacers formed between the side walls of the metal gate electrodes and inner walls of the side wall spacers.
Here, the offset spacers are formed in any one of a first conductivity type transistor and a second conductivity type transistor. Alternatively, the offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
Another embodiment of the present disclosure is directed to a semiconductor device including gate insulating films made of a high dielectric constant material and formed on a base, metal gate electrodes formed on the gate insulating films, and offset spacers formed at side walls of the metal gate electrodes. In addition, each of the gate insulating films is continuously formed from a bottom of the metal gate electrode to the inner walls of the side wall spacers, which is formed at side walls of the metal gate electrodes via the offset spacers, and the gate insulating film is interposed between the offset spacers and the side wall spacers.
Still another embodiment of the present disclosure is directed to a semiconductor device including gate insulating films made of a high dielectric constant material and formed on a base, WF metal layers formed on the gate insulating films, and buried metal layers formed on the WF metal layers, offset spacers formed at side walls of the buried metal layers on the WF metal layers, and side wall spacers formed at side walls of the buried metal layers via the offset spacers.
Yet another embodiment of the present disclosure is directed to a manufacturing method of a semiconductor device including forming a first conductivity type semiconductor region and a second conductivity type semiconductor region on a base. In addition, the manufacturing method of the semiconductor device further includes forming dummy gate electrodes on the base, and forming side wall spacers at side walls of the dummy gate electrodes, and further forming an interlayer insulating layer which buries the side wall spacers therein and exposes upper surfaces of the dummy gate electrodes, and removing the dummy gate electrodes, in the first conductivity type semiconductor region and the second conductivity type semiconductor region.
In addition, the manufacturing method includes forming offset spacers at the inner walls of the side wall spacers in any one of the first conductivity type semiconductor region and the second conductivity type semiconductor region, or forming offset spacers having different thicknesses at the inner walls of the side wall spacers in the first conductivity type semiconductor region and the second conductivity type semiconductor region.
Further, the manufacturing method includes forming gate insulating films made of a high dielectric constant material on the exposed base inside the side wall spacers, and forming metal gate electrodes on the gate insulating films.
Still yet another embodiment of the present disclosure is directed to a manufacturing method of a semiconductor device including forming dummy gate electrodes on the base, forming side wall spacers and an interlayer insulating layer, removing the dummy gate electrodes, forming gate insulating films made of a high dielectric constant material on the exposed base inside the side wall spacers and at the inner walls of the side wall spacers, forming offset spacers at side walls of the gate insulating film, and forming metal gate electrodes on the gate insulating films and at the inner walls of the offset spacers.
Further another embodiment of the present disclosure is directed to a manufacturing method of a semiconductor device including forming gate insulating films made of a high dielectric constant material on a base, forming WF metal layers on the gate insulating films, forming dummy gate electrodes on the WF metal layers, forming side wall spacers at side walls of the dummy gate electrodes, forming an interlayer insulating layer which buries the side wall spacers therein and exposes upper surfaces of the dummy gate electrodes, removing the dummy gate electrodes, forming offset spacers on the exposed WF metal layers inside the side wall spacers and at the inner walls of the side wall spacers, and forming buried metal layers on the gate insulating layers and at the inner wall sides of the offset spacers.
In the semiconductor device according to the embodiments of the present disclosure, and the semiconductor device manufactured according to the embodiments of the present disclosure, the gate length of a transistor is limited by offset spacers formed between metal gate electrodes and side wall spacers. Therefore, a formation region of the metal gate electrodes can be controlled at an arbitrary size by the offset spacers regardless of the size of the region of the inner wall sides of the side wall spacers. For this reason, it is possible to optimize of the gate length of a semiconductor device where a fine pattern is formed.
According to the embodiments of the present disclosure, it is possible to provide a semiconductor device having a fine structure and capable of optimizing the gate length.
Hereinafter, preferred embodiments for implementing the present disclosure will be described; however, the present disclosure is not limited to the following examples.
In addition, the description will be made in the following order.
The semiconductor device 10 shown in
In the Nfet region, a buried metal layer 18 is formed via an HK insulating layer 15 and an Nfet WF (Work Function) metal layer 17 on the semiconductor base 11. In addition, in the Pfet region, a buried metal layer 18 is formed via an HK insulating layer 15, a Pfet WF metal layer 16, and an Nfet WF metal layer 17 on the semiconductor base 11.
The semiconductor device 10 has a metal gate electrode formed of the Pfet WF metal layer 16 or the Nfet WF metal layer 17 and the buried metal layer 18.
The HK insulating layer 15 is a high-k insulating layer having the dielectric constant higher than silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like may be used. In addition, the HK insulating layer 15 and the silicon oxide film may form the gate insulating film together.
The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and, for example, is made of Ti, Al, Cu, and W, or alloys including the metals.
In the Nfet region and the Pfet region, side wall spacers 21 are formed at the side walls of the buried metal layers 18. In addition, in the Pfet region, offset spacers 19 are formed at the inner walls of the side wall spacers 21 of the metal gate electrode. For this reason, the Pfet region has a multi-layer body formed of the offset spacers 19, the HK insulating layer 15, the Pfet WF metal layer 16, and the Nfet WF metal layer 17 from the inner walls of the side wall spacers 21. Further, the buried metal layer 18 is formed at the inside surrounded by the multi-layer body.
The side wall spacers 21 are made of SiN, SiO2, or the like, and are formed of a single layer or a plurality of layers. In addition, SiN, SiO2, or the like is used for the offset spacers 19.
The offset spacers 19 are formed in order to adjust the gate length of each of the Nfet region and the Pfet region.
In the Nfet region and the Pfet region, opening portions of the side wall spacers 21 are preferably formed with the same size. This is because patterning is desired to be designed with regularity so as to be constant for ease of manufacturing in a case of processing a fine pattern. The sizes of the opening portions of the side wall spacers 21 are determined by patterning the gate electrodes in the lithography process, and thus the same pattern is preferable. Particularly, in a case of forming the gate electrodes, the length in the gate longitudinal direction becomes fine. For this reason, the lengths of the gate electrodes in the gate longitudinal direction are formed so as to be the same as each other in the Nfet region and the Pfet region, and thereby a burden in the lithography process can be reduced.
However, if the lithography process is performed with the same pattern in the Nfet region and the Pfet region, the gate length may not be optimized so as to match each diffusion layer profile. Therefore, the sizes of the opening portions are adjusted by forming the offset spacers 19 inside the opening portions of the side wall spacers 21. The offset spacers 19 are formed on the inner walls of the side wall spacers 21, and thereby it is possible to adjust ranges which the WF metal layers 16 are formed inside the opening portions. For this reason, the gate lengths can be optimized at arbitrary lengths.
In the semiconductor device 10 shown in
Source/drain 23 which is a P type impurity diffusion region, or source/drain 24 which is an N type impurity diffusion region is formed in the semiconductor base 11 which is located at both sides of the buried metal layer 18 and directly under the side wall spacers 21. The sources/drains 23 and 24 have LDDs (Lightly Doped Drains) and halo (not shown) formed therein. In addition, the surface layers of the sources/drains 23 and 24 exposed from the side wall spacers 21 become silicide. The silicide of the sources/drains 23 and 24 is formed from, for example, a cobalt silicide, a nickel silicide, a platinum silicide, or the like.
In the semiconductor device according to the first embodiment, the offset spacers are formed on the lateral surfaces of the metal gate electrodes and the WF metal layers. For this reason, the gate length can be arbitrarily set by changing the thicknesses of the offset spacers. Therefore, even if the dummy gate electrodes and the side wall spacers are formed with the same pattern in the lithography process, it is possible to configure the semiconductor device having the optimized gate length in each region.
Next, a manufacturing method of the semiconductor device according to the first embodiment will be described.
First, SiO2 and Si3N4 are sequentially formed on the semiconductor base 11 formed from a silicon substrate. In addition, a resist is patterned at parts where active regions are formed. The Si3N4, the SiO2, and the semiconductor base 11 are sequentially etched using the formed resist pattern as a mask, thereby forming a trench (a trench region). At this time, the etching is performed until the depth of the trench of the semiconductor base 11 becomes 350 to 400 nm. The region where the Si3N4 is patterned becomes an active region, and the trench region becomes a field oxide film.
Thereafter, the trench region is buried in the SiO2. For example, it is possible to form a film which has a good step coating property and is precise, by the use of a high density plasma CVD method or the like. The surface is planarized through CMP (Chemical Mechanical Polish). Polishing is performed through the CMP until the SiO2 film on the Si3N4 is removed in the Si3N4 region.
Next, the Si3N4 is removed using, for example, hot phosphoric acid, thereby forming the active region.
On the surface of the part where the active region is formed, SiO2 (sacrificial oxide film) of 10 nm is formed. Ion implantation for forming the P well region or forming a buried layer for suppressing punch-through, and ion implantation for adjusting a threshold value voltage (Vth) are performed in the Nfet forming region, thereby forming an Nfet channel region. Further, ion implantation for forming the N well region or forming a buried layer for suppressing punch-through, and ion implantation for adjusting a threshold value voltage (Vth) are performed in the Pfet forming region, thereby forming a Pfet channel region.
Through the above-described process, as shown in
Next, as shown in
First, the sacrificial oxide film which is provided on the semiconductor base 11 when the active region is formed is separated therefrom with a hydrogen fluoride (HF). After the separation, a gate insulating film 26 is formed with the thickness of about 1 to 3 nm through dry oxidation (O2, 700° C.). As the oxidation gas, for example, a mixed gas of H2/O2, N2O, and NO may be used in addition to the dry O2. In addition, a furnace annealing treatment or a rapid thermal annealing (RTA) treatment may be used.
Next, a dummy gate electrode material layer is formed using a CVD method. The dummy gate electrode material layer is formed on the gate insulation film 26 by, for example, depositing poly-silicon or amorphous silicon with the thickness of 50 to 100 nm. Next, Si3N4 is deposited as a hard mask with the thickness of, for example, 50 to 100 nm, using an LP-CVD (Low Pressure-Chemical Vapor Deposition). After the deposition, an electrode pattern is formed on the Si3N4 hard mask using the lithography process, and then anisotropic etching is performed for the gate insulating film 26 and the dummy gate electrode material layer using the hard mask pattern. The dummy gate electrode material layer is patterned, and thereby the gate insulating films 26 and the dummy gate electrodes 25 are formed on the semiconductor base 11 as shown in
The patterns of the dummy gate electrodes are formed as the same shape in the Nfet region and the Pfet region. In a case of processing a fine pattern, patterning is desired to be designed with regularity so as to be constant for manufacturing easiness in the lithography process. For this reason, the dummy gate electrodes are formed as the same pattern in the Nfet region and the Pfet region, thereby reducing a burden in the lithography process. Particularly, in a case of forming the gate electrode, the length in the gate longitudinal direction becomes fine, and thus the lengths of the dummy gate electrodes in the gate longitudinal direction are preferably formed as the same pattern.
Next, as shown in
First, the ion of BF2+ is implanted into the Pfet region at 3 to 5 keV and 5 to 20×1014/cm2, thereby forming a PLDD region. In addition, the ion of As+ is implanted into the Nfet region at 5 to 10 keV and 5 to 20×1014/cm2, thereby forming an NLDD region.
In addition, in order to suppress the short channel effect, so-called halo having impurity concentration higher than the wells is implanted into the sources/drains along with the formation of the LDD. For example, the Nfet region is divided into four regions and undergoes tilt ion implantation using B at 12 keV, 3×1013/cm2, and 45°. In addition, the Pfet region is divided into four regions and undergoes tilt ion implantation using As at 70 keV, 2×1013/cm2, and 45°.
Next, the side wall spacers 21 are formed at the side walls of the dummy gate electrodes 25.
Si3N4 is deposited with the thickness of 50 to 150 nm on the semiconductor base 11 so as to cover the dummy gate electrodes 25 using a plasma CVD method. Thereafter, anisotropic etching is performed so as to etch back the Si3N4 layer, thereby forming the side wall spacers 21 at the side walls of the dummy gate electrodes 25. At this time, the Si3N4 which is a hard mask of the dummy gate electrodes 25 is made to remain.
Next, the ion of BF2+ is implanted into the N well region 13 at 5 to 10 keV and 1 to 2×1015/cm2, thereby forming the P type source/drain 23. In addition, the ion of As+ is implanted into the P well region 14 at 40 to 50 keV and 1 to 2×1015/cm2, thereby forming the N type source/drain 24. After the ion implantation, the impurities are activated under the condition of 1000° C. and five seconds using the RTA (Rapid Thermal Annealing), thereby forming a MOSFET shown in
After the MOSFET is formed, resistance of the sources/drains 23 and 24 is reduced using a so-called SALICIDE (Self-Aligned siLICIDE) technique. For example, Ni is deposited with the thickness of 6 to 8 nm on the semiconductor base 11 through sputtering. The RTA is performed under the conditions of 300 to 500° C. and ten seconds, and thereby silicide (NiSi) is formed only on Si of the sources/drains 23 and 24. After the silicide is formed, unreacted Ni is removed by a chemical solution such as H2SO4/H2O2.
Next, SiN is formed with the thickness of 10 to 100 nm as a contact etching stopper (not shown). Two kinds of SiN may be formed separately so as to apply different mechanical stresses to the NMOS and the PMOS in the transistor.
In addition, SiO2 is deposited with the thickness of 100 to 1000 nm as the interlayer insulating layer 22 on the semiconductor base 11 so as to cover the dummy gate electrodes 25 and the side wall spacers 21. Further, as shown in
Next, as shown in
Next, as shown in
First, an offset spacer material is formed in a range of 1 to 20 nm on the entire surface of the semiconductor base 11. In addition, the offset spacer material layer is etched back through anisotropic etching so as to form the offset spacers 19 at the inner walls of the grooves from which the dummy gate electrodes are removed. The offset spacer material uses SiN, SiO2, or the like.
After the offset spacers 19 are formed, a resist layer is formed over the entire surface of the semiconductor base 11, and a resist pattern for opening the grooves from where the dummy gate electrodes are removed in the Nfet region is formed. The offset spacers formed at the inner walls of the side wall spacers 21 in the Nfet region are removed through the wet etching method using an HF solution or the like. For example, in a case where the offset spacers 19 are made of SiO2, the upper part of the interlayer insulating layer 22 is also etched with the thickness of about 10 nm together with the offset spacer material layer through etch-back; however, the etched amount of this degree does not cause a particular problem in a configuration of the semiconductor device.
In addition, for example, in the above-described dummy gate removal process, the gate insulating films 26 are made to remain by removing only the dummy gate electrodes 25. In the offset spacer formation process, an offset spacer material layer is formed on the entire surface of the semiconductor base 11 including the dummy gate electrodes 25 using SiN. In addition, the offset spacer material layer is etched back through anisotropic etching, thereby etching the offset spacers in the Nfet region. The gate insulating films 26 are removed after the offset spacers 19 are formed in the Pfet region.
In the above-described method, the side wall spacers are made of SiN, thereby preventing the upper part of the interlayer insulating layer 22 from being etched when the offset spacer material layer is etched.
In addition, since the surface of the semiconductor base 11 is not exposed inside the grooves from which the dummy gate electrodes are removed when the offset spacer material layer is etched, it is possible to suppress the semiconductor base 11 from being damaged due to the etching.
Next, as shown in
The HK insulating layer 15 is formed over the entire surface of the semiconductor base 11 using an ALD (Atomic Layer Deposition) method or the like. The HK insulating layer 15 is formed using, for example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like. In addition, there are cases where a ground of the HK insulating layer 15 mainly includes SiO2. In this case, the SiO2 is removed through plasma oxidation.
After the HK insulating layer 15 is formed, WF (Work Function) metal layers are formed. A single metal electrode or separate metal electrodes are formed in the Nfet region and the Pfet region using the WF metal layers. Here, a case where different WF metal layers are formed in the Nfet region and the Pfet region will be described below.
First, the Pfet WF metal layer 16 is formed.
As shown in
Next, the Pfet WF metal layer 16 is removed from the Nfet region by the dry etching method or the wet etching method. At this time, the HK insulating layer 15 in the Nfet region is not removed but is left. For example, a resist pattern or the like is formed on the part where the Pfet WF metal layer 16 is left in the Pfet region, and the Pfet WF metal layer 16 in the Nfet region is etched using the resist pattern as a mask. In a case where TiN is formed as the Pfet WF metal layer 16, the Pfet WF metal layer 16 is removed from the Nfet region using, for example, ammonia hydrogen peroxide.
Next, as shown in
After the Pfet WF metal layer 16 and the Nfet WF metal layer 17 are formed, as shown in
As described above, after the offset spacers 19 or the HK insulating layer 15 are formed in the grooves from which the dummy gate electrodes are removed, the low resistance gate material is buried therein so as to form the low resistance gate material layer, thereby obtaining the buried metal layer 18. In addition, planarization is performed by removing the low resistance gate layer, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 on the interlayer insulating layer 22 using a CMP method. That is to say, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 which are continuously formed on the interlayer insulating layer 22 are removed so as to be left only in the grooves when the buried metal layer 18 is formed.
The low resistance gate material is left only in the grooves from which the dummy gate electrodes are removed through this process, thereby forming the buried metal layers 18. In addition, in this process, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the buried metal layer 18 form a metal gate electrode.
Through the above-described processes, the semiconductor device 10 shown in
The semiconductor device 20 shown in
In the Nfet region, a buried metal layer 18 is formed via an HK insulating layer 15 and an Nfet WF (Work Function) metal layer 17 on the semiconductor base 11. In addition, in the Pfet region, a buried metal layer 18 is formed via an HK insulating layer 15, a Pfet WF metal layer 16, and an Nfet WF metal layer 17 on the semiconductor base 11.
The semiconductor device 20 has a metal gate electrode formed of the Pfet WF metal layer 16 or the Nfet WF metal layer 17 and the buried metal layer 18.
The HK insulating layer 15 is a high-k insulating layer having the dielectric constant higher than silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like may be used. In addition, the HK insulating layer 15 and the silicon oxide film may form the gate insulating film together.
The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and, for example, is made of Ti, Al, Cu, and W, or alloys including the metals.
In the Nfet region and the Pfet region, side wall spacers 21 are formed at the side walls of the buried metal layers 18. In addition, in the Pfet region, offset spacers 19 are formed between the HK insulating layer 15 and the Pfet WF metal layer 16 at the side walls of the buried metal layers 18. For this reason, the Pfet region has a multi-layer body formed of the HK insulating layer 15, the offset spacers 19, the Pfet WF metal layer 16, and the Nfet WF metal layer 17 from the inner walls of the side wall spacers 21. Further, the buried metal layer 18 is formed at the inside surrounded by the multi-layer body.
The side wall spacers 21 are made of SiN, SiO2, or the like, and are formed of a single layer or a plurality of layers. In addition, SiN, SiO2, or the like is used for the offset spacers 19.
In the Pfet region, the gate length is determined depending on a range where the Pfet WF metal layer 16 is formed. For this reason, a formation range of the Pfet WF metal layer 16 can be controlled by forming the Pfet WF metal layer 16 at the inner walls of the HK insulating layer 15 via the offset spacers 19. The Pfet WF metal layer 16 can be formed with an arbitrary size inside the opening portion of the side wall spacer 21 by setting the offset spacers 19 to an arbitrary thickness. For this reason, an arbitrary gate length can be set without depending on the size of the opening portion of the side wall spacer 21.
In addition, the offset spacers may be formed in both of the Pfet region and the Nfet region as well as being formed only in the Pfet region as shown in
Source/drain 23 which is a P type impurity diffusion region, or source/drain 24 which is an N type impurity diffusion region is formed in the semiconductor base 11 which is located at both sides of the buried metal layer 18 and directly under the side wall spacers 21. The sources/drains 23 and 24 have LDDs (Lightly Doped Drains) and halo (not shown) formed therein. In addition, the surface layers of the sources/drains 23 and 24 exposed from the side wall spacers 21 become silicide. The silicide of the sources/drains 23 and 24 is formed from, for example, a cobalt silicide, a nickel silicide, a platinum silicide, or the like.
In the semiconductor device according to the second embodiment, the offset spacers are formed between the lateral surfaces of the buried metal layer and the WF metal layers, and the lateral surfaces of the HK insulating layer. For this reason, a formation range of the WF metal layer can be arbitrarily set by changing the thicknesses of the offset spacers. Thereby, the gate length can be arbitrarily set using the offset spacers. Therefore, even if the dummy gate electrodes are formed with the same pattern in the lithography process, it is possible to configure the semiconductor device having the optimized gate length in each region.
Next, a manufacturing method of the semiconductor device according to the second embodiment will be described.
A manufacturing method of the semiconductor device according to the second embodiment can be performed similarly up to the removal process of the dummy gate electrodes shown in
As shown in
Next, as shown in
The HK insulating layer 15 is formed using an ALD (Atomic Layer Deposition) method or the like. The HK insulating layer 15 is formed using, for example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like. In addition, there are cases where SiO2 is formed for a ground of the HK insulating layer 15 as the gate insulating film. In this case, the SiO2 is removed through plasma oxidation.
First, an offset spacer material is formed in a range of 1 to 20 nm on the entire surface of the HK insulating layer 15. In addition, as shown in
After the offset spacers 19 are formed in both the regions of the Nfet region and the Pfet region or in one region, the Pfet WF (Work Function) metal layer 16 is formed.
As shown in
Next, the Pfet WF metal layer 16 is removed from the Nfet region by the dry etching method or the wet etching method. At this time, the HK insulating layer 15 in the Nfet region is not removed but is left. For example, a resist pattern or the like is formed on the part where the Pfet WF metal layer 16 is left in the Pfet region, and the Pfet WF metal layer 16 in the Nfet region is etched using the resist pattern as a mask. In a case where TiN is formed as the Pfet WF metal layer 16, the Pfet WF metal layer 16 is removed from the Nfet region using, for example, ammonia hydrogen peroxide.
After the Pfet WF metal layer 16 is removed from the Nfet region, the offset spacers 19 formed at the inner walls of the grooves from which the dummy gate electrodes are removed are removed from the Nfet region. For example, the offset spacers 19 formed in the Nfet region are removed using the Pfet WF metal layer 16 as a mask by a wet etching method using an HF solution. Thereby, the offset spacers 19 are removed from the Nfet region without addition of a process such as lithography where a pattern mask is formed, and thus the offset spacers 19 can be left only in the Pfet region.
Next, as shown in
The Nfet WF metal layer 17 has 4.0 eV as the optimal work function, and a material close to this value is used. For example, alloys including Hf, Zr, Ti, Ta, and Al, or a carbide, HfSi, and the like are used.
After the Pfet WF metal layer 16 and the Nfet WF metal layer 17 are formed, as shown in
As described above, after the dummy gate electrodes are removed, the HK insulating layer 15, the offset spacers 19, the Pfet WF metal layer 16, the Nfet WF metal layer 17, and the low resistance gate material buried in the grooves are formed, thereby obtaining the buried metal layer 18. In addition, planarization is performed by removing the low resistance gate layer, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 on the interlayer insulating layer 22 using a CMP method.
The low resistance gate material is left only in the grooves from which the dummy gate electrodes are removed through this process, thereby forming the buried metal layers 18. In addition, in this process, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the buried metal layer 18 form a metal gate electrode.
Through the above-described processes, the semiconductor device 20 shown in
The semiconductor device 30 shown in
In the Nfet region, a buried metal layer 18 is formed via an HK insulating layer 15 and an Nfet WF (Work Function) metal layer 17 on the semiconductor base 11. In addition, in the Pfet region, a buried metal layer 18 is formed via an HK insulating layer 15 and a Pfet WF metal layer 16 on the semiconductor base 11.
The semiconductor device 30 has a metal gate electrode formed of the Pfet WF metal layer 16 or the Nfet WF metal layer 17 and the buried metal layer 18.
The HK insulating layer 15 is a high-k insulating layer having the dielectric constant higher than silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like may be used. In addition, the HK insulating layer 15 and the silicon oxide film may form the gate insulating film together.
The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and, for example, is made of Ti, Al, Cu, and W, or alloys including the metals.
In the Nfet region and the Pfet region, side wall spacers 21 are formed at the side walls of the buried metal layers 18. In addition, in the Pfet region, offset spacers 19 are formed between the HK insulating layer 15 and the Pfet WF metal layer 16 at the side walls of the buried metal layers 18. The side wall spacers 21 are made of SiN, SiO2, or the like, and are formed of a single layer or a plurality of layers. In addition, SiN, SiO2, or the like is used for the offset spacers 19.
In the Nfet region, source/drain 24 which is an n type impurity diffusion region is formed in the semiconductor base 11 which is located directly under the side wall spacers 21 at both sides of the buried metal layer 18. In addition, in the Pfet region, a raised source/drain portion 27 which is formed of epitaxial layers and source/drain 23 which is a P type impurity diffusion region are formed directly under the side wall spacers 21 at both sides of the buried metal layer 18. The sources/drains 23 and 24 have LDDs and halo (not shown) formed therein.
In addition, the surface layers of the sources/drains 23 and 24 and the raised source/drain portion 27 exposed from the side wall spacers 21 become silicide. The silicide is formed from, for example, a cobalt silicide, a nickel silicide, a platinum silicide, or the like.
In the Nfet region of the semiconductor device 30 according to the third embodiment, the HK insulating layer 15 and the Nfet WF metal layer 17 are formed only on the bottom of the buried metal layer 18. In addition, in the Pfet region, the HK insulating layer 15 and the Pfet WF metal layer 16 are formed only on the bottom of the buried metal layer 18. Further, the offset spacers 19 are formed between the metal gate electrodes and the side wall spacers 21 on the HK insulating layer 15 and the Pfet WF metal layer 16.
Since the offset spacers 19 are formed on the Pfet WF metal layer 16 in the Pfet region of the semiconductor device 30 according to the third embodiment, it has no influence on a formation range of the Pfet WF metal layer 16. For this reason, it is difficult to adjust the gate length through the formation of the offset spacers 19. However, it is possible to reduce gate side wall fringing capacitance by forming a reverse T-shaped gate formed of the Pfet WF metal layer 16 and the metal gate electrode. This can improve an increase in capacitance between the gate diffusion layers, particularly, in a recent stress technique, for example, in a case of applying embedded SiGe to a PMOS and of applying embedded SiC to an NMOS.
Next, a manufacturing method of the semiconductor device according to the third embodiment will be described.
First, as shown in
First, the sacrificial oxide film which is provided on the semiconductor base 11 when the active region is formed is separated therefrom with a hydrogen fluoride (HF) solution. After the separation, the HK insulating layer is formed using an ALD (Atomic Layer Deposition) method or like. The HK insulating layer 15 is formed using HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like. In addition, there are cases where a ground of the HK insulating layer 15 mainly includes SiO2. In this case, the SiO2 is formed through plasma oxidation.
Next, WF (Work Function) metal layers are formed on the HK insulating layer 15. A single metal electrode or separate metal electrodes are formed in the NMOS and the PMOS using the WF metal layers. Here, a case where different types of WF metal layers are formed in the NMOS and the PMOS will be described below.
In the Nfet region, the Nfet WF metal layer 17 is formed on the HK insulating layer 15. In addition, in the Pfet region, the Pfet WF metal layer 16 is formed on the HK insulating layer 15.
The Pfet WF metal layer 16 and the Nfet WF metal layer 17 are formed in a range of 1 to 20 nm using TiN, by a CVD method, a PVD method, or an ALD method. The Pfet WF metal layer 16 has 5.2 eV as the optimal work function, and a material close to this value is used. For example, alloys including Ru, Pd, Pt, Co, Ni, and Mo, or an oxide, TiN and the like are used. The Nfet WF metal layer 17 has 4.0 eV as the optimal work function, and a material close to this value is used. For example, alloys including Hf, Zr, Ti, Ta, and Al, or a carbide, HfSi, and the like are used.
After the Pfet WF metal layer 16 and the Nfet WF metal layer 17 are formed, a dummy gate electrode material layer is formed. The dummy gate electrode material layer is formed on the Pfet WF metal layer 16 and the Nfet WF metal layer 17 by, for example, depositing poly-silicon or amorphous silicon with the thickness of 50 to 100 nm using a CVD method or the like. Next, Si3N4 is deposited as a hard mask with the thickness of, for example, 50 to 100 nm, using an LP-CVD (Low Pressure-Chemical Vapor Deposition). After the deposition, an electrode pattern is formed on the Si3N4 hard mask using the lithography process, and then anisotropic etching is performed for the HK insulating layer 15, the Pfet WF metal layer 16, and the Nfet WF metal layer 17, and the dummy gate electrode material layer using the hard mask pattern. The dummy gate electrode material layer is patterned, and thereby the HK insulating layer 15, the Nfet WF metal layer 17, and the dummy gate electrode 25 are formed in the Nfet region of the semiconductor base 11 as shown in
Next, as shown in
First, the raised source/drain portion 27 is formed in the Pfet region.
In other words, a SiN layer is formed so as to cover the dummy gate electrodes 25 on the semiconductor base 11. Next, a resist pattern which opens the Pfet region is formed. The SiN layer is etched back from the resist opening portion through anisotropic etching, thereby forming dummy side wall spacers at the side walls of the dummy gate electrodes 25.
After the dummy side wall spacers are formed and the semiconductor base 11 of the resist opening portion is etched, SiGe is selectively grown, and thereby an epitaxial growth layer (epi layer) is formed.
After the epi layer made of SiGe is formed, the dummy side wall spacers and the SiN layer remaining at other than the Pfet region are removed so as to form the raised source/drain portion 27.
The ion of BF2+ is implanted into the PMOS region at 3 to 5 keV and 5 to 20×1014/cm2, thereby forming a PLDD region. In addition, the ion of As+ is implanted into the NMOS region at 5 to 10 keV and 5 to 20×1014/cm2, thereby forming an NLDD region.
In addition, in order to suppress the short channel effect, so-called halo having impurity concentration higher than the wells is implanted into the sources/drains along with the formation of the LDD. For example, the Nfet region is divided into four regions and undergoes tilt ion implantation using B at 12 keV, 3×1013/cm2, and 45°. In addition, the Pfet region is divided into four regions and undergoes tilt ion implantation using As at 70 keV, 2×1013/cm2, and 45°.
Next, the side wall spacers 21 are formed at the side walls of the dummy gate electrodes 25.
Si3N4 is deposited with the thickness of 50 to 150 nm on the semiconductor base 11 so as to cover the dummy gate electrodes 25 using the plasma CVD method. Thereafter, anisotropic etching is performed so as to etch back the Si3N4 layer, thereby forming the side wall spacers 21 at the side walls of the dummy gate electrodes 25. At this time, the Si3N4 which is a hard mask of the dummy gate electrodes 25 is made to remain.
Next, the ion of BF2+ is implanted into the N well region 13 at 5 to 10 keV and 1 to 2×1015/cm2, thereby forming the P type source/drain 23. The ion implantation of BF2+ is performed such that a P type region by B is formed in the entire region of the raised source/drain portion 27. In addition, the ion of As+ is implanted into the P well region 14 at 40 to 50 keV and 1 to 2×1015/cm2, thereby forming the N type source/drain 24. After the ion implantation, the impurities are activated under the condition of 1000° C. and five seconds using the RTA (Rapid Thermal Annealing), thereby forming a MOSFET shown in
After the MOSFET is formed, resistance of the sources/drains 23 and 24 is reduced using a so-called SALICIDE (Self-Aligned siLICIDE) technique. For example, Ni is deposited with the thickness of 6 to 8 nm on the semiconductor base 11 through sputtering. The RTA is performed under the condition of 300 to 500° C. and ten seconds, and thereby silicide (NiSi) is formed only on Si of the sources/drains 23 and 24. After the silicide is formed, unreacted Ni is removed by a chemical solution such as H2SO4/H2O2.
Next, SiN is formed with the thickness of 10 to 100 nm as a contact etching stopper (not shown). Two kinds of SiN may be formed separately so as to apply different mechanical stresses to the NMOS and the PMOS in the transistor.
In addition, SiO2 is deposited with the thickness of 100 to 1000 nm as the interlayer insulating layer 22 on the semiconductor base 11 so as to cover the dummy gate electrodes 25, the side wall spacers 21, and the raised source/drain portions 27. Further, the upper parts of the dummy gate electrodes 25 are exposed through planarization using the CMP method.
Next, as shown in
Next, as shown in
The Pfet WF metal layer 16 or the Nfet WF metal layer 17 is present on the bottom of the grooves from which the dummy gate electrodes are removed. An offset spacer material is formed in a range of 1 to 20 nm so as to cover the grooves from which the dummy gate electrodes are removed. In addition, etch-back is performed through anisotropic etching, thereby forming the offset spacers at the inner walls of the grooves from which the dummy gate electrodes are removed. As a material of the offset spacers, SiN, SiO2, or the like is used.
Thereafter, the offset spacers are removed from the Nfet region by a wet etching method using an HF solution.
After the offset spacers 19 are formed, as shown in
After the offset spacers 19 are formed in the grooves from which the dummy gate electrodes are removed, the low resistance gate material is buried therein so as to form the low resistance gate material layer on the Pfet WF metal layer 16 or the Nfet WF metal layer 17, thereby obtaining the buried metal layer 18. In addition, planarization is performed by removing the low resistance gate layer on the interlayer insulating layer 22 using the CMP method. Through this process, the low resistance gate material is left only in the grooves from which the dummy gate electrodes are removed, thereby forming the buried metal layer 18.
Through the above-described processes, the semiconductor device 30 shown in
In the semiconductor device 40 shown in
Next, a structure of the gate electrodes 44 of the semiconductor device 40 shown in
The gate electrodes 44 are formed in the U shape so as to cover the channel regions of the above-described fins 42 and 43 from one side to the other side. The configurations of the gate electrodes of the semiconductor device 40 are different in the Pfet region and the Nfet region.
In the Pfet region, a buried metal layer 48 is formed via an HK insulating layer 45, a Pfet WF metal layer 46, and an Nfet WF metal layer 47 on the oxide insulating layer 41. In addition, in the Nfet region, a buried metal layer 48 is formed via an HK insulating layer 45 and an Nfet WF (Work Function) metal layer 47 on the oxide insulating layer 41.
The semiconductor device 40 has a metal gate electrode 44 formed of the Pfet WF metal layer 46 or the Nfet WF metal layer 47 and the buried metal layer 48.
The HK insulating layer 45 is a high-k insulating layer having the dielectric constant higher than silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like may be used. In addition, the HK insulating layer 45 and the silicon oxide film may form the gate insulating film together.
The buried metal layer 48 is made of a pure metal material, an alloy or a metal compound, and, for example, is made of Ti, Al, Cu, and W, or alloys including the metals.
In the Nfet region and the Pfet region, side wall spacers 51 are formed at the side walls of the buried metal layers 48. In addition, in the Pfet region, offset spacers 49 are formed at the lower parts of the inner walls of the HK insulating layer 45 and the side wall spacers 51. For this reason, the Pfet region has a multi-layer body formed of the offset spacers 49, the HK insulating layer 45, the Pfet WF metal layer 46, and the Nfet WF metal layer 47 from the inner walls of the side wall spacers 51. Further, the buried metal layer 48 is formed at the inside surrounded by the multi-layer body.
The side wall spacers 51 are made of SiN, SiO2, or the like, and are formed of a single layer or a plurality of layers. In addition, SiN, SiO2, or the like is used for the offset spacers 49.
The offset spacers 49 are formed only at the lower parts of the inner walls of the side wall spacers 51. In addition, the offset spacers 49 are formed up to positions higher than the upper part of the fin 42. Therefore, in the part where the fin 42 is formed, the HK insulating layer 45, the Pfet WF metal layer 46, and the side wall spacers 51 are connected to the fin 42 only via the offset spacers 49.
The sizes of the opening portions of the side wall spacers are determined by patterning the gate electrodes in the lithography process, and thus the same pattern is preferable.
This is because patterning is desired to be designed with regularity so as to be constant for ease of manufacturing in a case of processing a fine pattern. In the Nfet region and the Pfet region, opening portions of the side wall spacers are preferably formed with the same size. However, if the opening portions of the side wall spacers are the same as each other in the Nfet region and the Pfet region, the gate length may not be optimized so as to match each diffusion layer profile.
Therefore, the sizes of the opening portions are adjusted by forming the offset spacers 49 inside the opening portions of the side wall spacers. The gate length of the Pfet region can be adjusted by forming the offset spacers 49 between the WF metal layer 46 and the side wall spacers 51. In addition, a range where the Pfet WF metal layer 46 is formed is adjusted using the offset spacers 49 in the opening portion, and thus the gate length can be optimized at an arbitrary length.
In addition, in a case of the fin type semiconductor device, the gate electrode bottom and the gate side wall shape influence the gate length. For this reason, a difference occurs in the gate length in a case where the inner walls of the side wall spacers where the gate electrode is formed are tapered or in a case where roughness is present in the side walls, and thereby optimization is difficult.
On the other hand, in the semiconductor device according to the fourth embodiment, the offset spacers 49 are formed at the inner wall sides of the side wall spacers 51, particularly, between the side wall spacers 51 and the HK insulating layer 45, or between the HK insulating layer 45 and the WF metal layer 46. With this structure, for example, in a case where the roughness is present in the inner walls of the side wall spacers 51, the inner walls of the side wall spacers 51 where the fin 42 is formed can be planarized by the offset spacers 49. In addition, for example, even if the inner walls of the side wall spacers 51 are tapered, the inner walls of the parts where the fin 42 is formed are made to be vertical by forming the offset spacers 49, and thereby the gate length can be adjusted.
In addition, the offset spacers may be formed in both of the Pfet region and the Nfet region as well as being formed only in the Pfet region as shown in
As shown in the semiconductor device according to the above-described fourth embodiment, the gate electrode structure of the semiconductor device having the planar type structure as in the first embodiment or the second embodiment described above is applicable to the semiconductor device having the fin type structure. In addition, the gate length can be optimized by changing the thicknesses of the offset spacers. Therefore, even if the dummy gate electrodes and the side wall spacers are formed with the same pattern in the lithography process, it is possible to configure the semiconductor device having the optimized gate length in each region.
Next, a manufacturing method of the semiconductor device according to the fourth embodiment will be described. A manufacturing method of the semiconductor device according to the fourth embodiment can be performed by the same processes except that the above-described manufacturing method of the semiconductor device according to the first embodiment is applied to the fin type semiconductor device. Detailed description of the same processes as in the manufacturing method of the semiconductor device according to the first embodiment will be omitted in the following.
First, as shown in
The fin 42 is formed in the Pfet region by the well-known method. In addition, the fin 43 is formed in the Nfet region. For example, a semiconductor layer such as silicon is deposited, the ion of a P type impurity or an N type impurity is implanted thereinto so as to form a source/drain, and etching is performed so as to have a predetermined fin shape.
Next, a gate insulating film and a dummy gate electrode are formed in the Nfet region and the Pfet region of the oxide insulating layer 41.
First, a gate insulating film is formed with the thickness of 1 to 3 nm through dry oxidation (O2, 700° C.) on the surfaces of the fins 42 and 43. Next, a dummy gate electrode material layer is formed using the CVD method. The dummy gate electrode material layer is formed on the oxide insulating layer 41 by, for example, depositing poly-silicon or amorphous silicon with the thickness of 50 to 100 nm. After the deposition, a resist pattern is formed using the lithography process, and then anisotropic etching is performed for the dummy gate electrode material layer using the hard mask pattern. The dummy gate electrode material layer is patterned, and thereby the dummy gate electrodes 53 are formed on the oxide insulating layer 41 as shown in
Next, the side wall spacers 51 are formed at the side walls of the dummy gate electrodes 53.
Si3N4 is deposited with the thickness of 50 to 150 nm on the oxide insulating layer 41 so as to cover the dummy gate electrodes 53 using a plasma CVD method. Thereafter, anisotropic etching is performed so as to etch back the Si3N4 layer, thereby forming the side wall spacers 51 at the side walls of the dummy gate electrodes 53.
In addition, SiO2 is deposited with the thickness of 100 to 1000 nm as the interlayer insulating layer 52 on the oxide insulating layer 41 so as to cover the dummy gate electrodes 53 and the side wall spacers 51. Further, as shown in
Next, as shown in
Next, as shown in
First, an offset spacer material is formed in a range of 1 to 20 nm over the entire surface of the oxide insulating layer 41, inside the opening portions of the inner walls of the side wall spacers 51, and on the exposed fins 42 and 43. The offset spacer material uses SiN, SiO2, or the like. Further, the offset spacer material layer is etched back through anisotropic etching.
In the etch-back of the offset spacer material layer, over-etching is performed until the offset spacer material layer formed at the side walls of the fins 42 and 43 exposed from the opening portions of the side wall spacers 51 is removed. Through the etching, the offset spacers 49 can be formed only at the inner wall sides of the side wall spacers 51 without remaining at the side walls of the fins 42 and 43.
At this time, it is necessary to form the above-described dummy gate electrodes 53 and side wall spacers 51 so as to be double or more the height of the fins. With being double or more the height of the fins, the offset spacers 49 remain so as to be more than the height at which the fins 42 and 43 are formed in the side wall spacers 51 when the over-etching is performed until the offset spacer material layer formed at the side walls of the fins 42 and 43 are removed.
In addition, in the same manner as the manufacturing method of the semiconductor device according to the first embodiment, the gate insulating layer may be removed after the offset spacers 49 are formed, without removing the gate insulating film in the dummy gate removal process.
After the offset spacers 49 are formed, a resist layer is formed over the entire surface of the oxide insulating layer 41, and a resist pattern for opening the groove from which the dummy gate electrodes are removed in the Nfet region is formed. The offset spacers formed at the inner walls of the side wall spacers 51 in the Nfet region are removed through the wet etching method using an HF solution.
Next, as shown in
The HK insulating layer 45 is formed over the entire surface of the interlayer insulating layer 52 so as to cover the opening portions of the side wall spacers 51 using an ALD (Atomic Layer Deposition) method or the like. The HK insulating layer 45 is formed using, for example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, and the like.
After the HK insulating layer 45 is formed, WF (Work Function) metal layers are formed. A single metal electrode or separate metal electrodes are formed in the NMOS and the PMOS using the WF metal layers. Here, a case where different WF metal layers are formed in the NMOS and the PMOS will be described below.
First, the Pfet WF metal layer 46 is formed.
As shown in
Next, the Pfet WF metal layer 46 is removed from the Nfet region by the dry etching method or the wet etching method. At this time, the HK insulating layer 45 in the Nfet region is not removed but is left. For example, a resist pattern is formed on the part where the Pfet WF metal layer 46 is left in the Pfet region, and the Pfet WF metal layer 46 in the Nfet region is etched using the resist pattern as a mask. In a case where TiN is formed as the Pfet WF metal layer 46, the Pfet WF metal layer 46 is removed from the Nfet region using, for example, ammonia hydrogen peroxide.
Next, the Nfet WF metal layer 47 is formed in a range of 1 to 20 nm on the Pfet WF metal layer 46 and the HK insulating layer 45, using a CVD method, a PVD method, or an ALD method. The Nfet WF metal layer 47 has 4.0 eV as the optimal work function, and a material close to this value is used. For example, alloys including Hf, Zr, Ti, Ta, and Al, or a carbide, HfSi, and the like are used.
After the Pfet WF metal layer 46 and the Nfet WF metal layer 47 are formed, as shown in
As described above, after the offset spacers 49, the HK insulating layer 45, the Pfet WF metal layer 46, and the Nfet WF metal layer 47 are formed in the grooves from which the dummy gate electrodes are removed, the low resistance gate material is buried therein so as to form the low resistance gate material layer, thereby obtaining the buried metal layer 48. In addition, planarization is performed by removing the low resistance gate layer, the Nfet WF metal layer 47, the Pfet WF metal layer 46, and the HK insulating layer 45 on the interlayer insulating layer 52 using a CMP method.
The low resistance gate material is left only in the grooves from which the dummy gate electrodes are removed through this process, thereby forming the buried metal layers 48. In addition, in this process, the Nfet WF metal layer 47, the Pfet WF metal layer 46, and the HK insulating layer 45 which are continuously formed on the interlayer insulating layer 52 are removed so as to be left only in the grooves when the buried metal layer 48 is formed.
Through the above-described processes, the semiconductor device 40 shown in
Although, in the semiconductor device according to the fourth embodiment, the offset spacers are formed between the inner walls of the side wall spacers and the HK insulating layer in the same manner as the first embodiment, the formation position of the offset spacers is not particularly limited as long as it is located between the inner walls of the side wall spacers and the WF metal layer. For example, the offset spacers may be formed between the HK insulating layer and the WF metal layer in the inner walls of the side wall spacers in the same manner as the semiconductor device according to the second embodiment.
In this case, as described with reference to
The present disclosure is not limited to the configurations described in the above-described embodiments, and may have various modifications and alterations in the scope not departing from the configurations of the present disclosure.
The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-243251 filed in the Japan Patent Office on Oct. 29, 2010, the entire content of which is hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-243251 | Oct 2010 | JP | national |
This application is as continuation of U.S. Ser. No. 17/399,222 filed Aug. 11, 2021, which is a continuation of U.S. patent application Ser. No. 17/023,611 filed Sep. 17, 2020, now U.S. Pat. No. 11,121,133 issued Sep. 14, 2021, which is a continuation of U.S. patent application Ser. No. 16/443,319 filed Jun. 17, 2019, now U.S. Pat. No. 10,811,416 issued Oct. 20, 2020, which is a division of U.S. patent application Ser. No. 15/588,072 filed May 5, 2017, now U.S. Pat. No. 10,373,955 issued Aug. 6, 2019, which is a continuation of U.S. patent application Ser. No. 15/080,657 filed Mar. 25, 2016, now U.S. Pat. No. 9,741,814 issued Aug. 22, 2017, which is a continuation of U.S. patent application Ser. No. 14/709,047 filed May 11, 2015, now U.S. Pat. No. 9,331,077 issued May 3, 2016, which is a continuation of U.S. patent application Ser. No. 13/278,809 filed Oct. 21, 2011, now U.S. Pat. No. 9,059,312 issued Jun. 16, 2015, the entireties of which are incorporated herein by reference to the extent permitted by law. The present application contains subject matter related to and claims the benefit of priority to Japanese Patent Application No. JP 2010-243251 filed on Oct. 29, 2010 in the Japan Patent Office, the entirety of which is incorporated by reference herein to the extent permitted by law.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5827761 | Fulford et al. | Oct 1998 | A |
| 6333540 | Shiozawa et al. | Dec 2001 | B1 |
| 6908801 | Saito | Jun 2005 | B2 |
| 7622340 | Akaska et al. | Nov 2009 | B2 |
| 7952142 | Wu | May 2011 | B2 |
| 8247281 | Hempel et al. | Aug 2012 | B2 |
| 8273632 | Lin et al. | Sep 2012 | B2 |
| 8580625 | Lu et al. | Nov 2013 | B2 |
| 11824057 | Matsumoto | Nov 2023 | B2 |
| 20040061185 | Doyle et al. | Apr 2004 | A1 |
| 20050019993 | Lee et al. | Jan 2005 | A1 |
| 20050158935 | Shin | Jul 2005 | A1 |
| 20050233527 | Brask | Oct 2005 | A1 |
| 20060071275 | Brask et al. | Apr 2006 | A1 |
| 20060091432 | Guha et al. | May 2006 | A1 |
| 20060157797 | Tateshita | Jul 2006 | A1 |
| 20060189043 | Schultz | Aug 2006 | A1 |
| 20070178634 | Jung et al. | Aug 2007 | A1 |
| 20070284671 | Tsutsumi | Dec 2007 | A1 |
| 20080001224 | Kinoshita | Jan 2008 | A1 |
| 20080135972 | Ikuta | Jun 2008 | A1 |
| 20080149984 | Chang et al. | Jun 2008 | A1 |
| 20090011610 | Bojarczuk et al. | Jan 2009 | A1 |
| 20090039445 | Wu | Feb 2009 | A1 |
| 20090170339 | Trentzsch et al. | Jul 2009 | A1 |
| 20090189201 | Chang et al. | Jul 2009 | A1 |
| 20090212332 | Wang et al. | Aug 2009 | A1 |
| 20100065925 | Hung et al. | Mar 2010 | A1 |
| 20100065926 | Yeh et al. | Mar 2010 | A1 |
| 20100065928 | Yasutake | Mar 2010 | A1 |
| 20100210079 | Masuoka | Aug 2010 | A1 |
| 20110186915 | Schelper et al. | Aug 2011 | A1 |
| 20110278676 | Cheng et al. | Nov 2011 | A1 |
| 20120025323 | Teo | Feb 2012 | A1 |
| 20130020657 | Lu et al. | Jan 2013 | A1 |
| 20130334690 | Tsaid et al. | Dec 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 1731588 | Feb 2006 | CN |
| 101013700 | Aug 2007 | CN |
| 101174587 | May 2008 | CN |
| 11-241350 | Sep 1999 | JP |
| 2001-015749 | Jan 2001 | JP |
| 2001-308318 | Nov 2001 | JP |
| 2002093927 | Mar 2002 | JP |
| 2002-110815 | Apr 2002 | JP |
| 2002-164535 | Jun 2002 | JP |
| 2002-289851 | Oct 2002 | JP |
| 2005-259945 | Sep 2005 | JP |
| 2008-244331 | Mar 2007 | JP |
| 2007-134432 | May 2007 | JP |
| 2008-193060 | Aug 2008 | JP |
| 2009182317 | Aug 2009 | JP |
| 2009-224386 | Oct 2009 | JP |
| 2009-278042 | Nov 2009 | JP |
| 2010-171137 | Aug 2010 | JP |
| 2010-212507 | Sep 2010 | JP |
| 2011-108825 | Jun 2011 | JP |
| 2011-165973 | Aug 2011 | JP |
| 2001-284466 | Oct 2011 | JP |
| 200731401 | Aug 2007 | TW |
| 200731410 | Aug 2007 | TW |
| Entry |
|---|
| Japanese Office Action issued in connection with related Japanese patent application No. 2010-243251 dated Jul. 1, 2014. |
| Chinese Patent Office Action issued in corresponding to Chinese Patent Application No. 201510969631.9 dated Dec. 7, 2017 with English translation. |
| Chinese Patent Office Action issued in corresponding Chinese Patent Application No. 201810372155.6 dated Apr. 3, 2019 with English translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20240047461 A1 | Feb 2024 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15588072 | May 2017 | US |
| Child | 16443319 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17399222 | Aug 2021 | US |
| Child | 18485440 | US | |
| Parent | 17023611 | Sep 2020 | US |
| Child | 17399222 | US | |
| Parent | 16443319 | Jun 2019 | US |
| Child | 17023611 | US | |
| Parent | 15080657 | Mar 2016 | US |
| Child | 15588072 | US | |
| Parent | 14709047 | May 2015 | US |
| Child | 15080657 | US | |
| Parent | 13278809 | Oct 2011 | US |
| Child | 14709047 | US |
