1) Technical field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to so-called a direct-lead-bonding type semiconductor device having a lead plate for directly connecting a surface electrode of the semiconductor chip with a terminal.
2) Description of Related Arts
The recent power semiconductor device such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) utilizes a direct lead plate, instead of a bonding wire, for connecting an emitter electrode with a lead terminal.
As shown in
Moreover, the semiconductor chip 1 includes a collector electrode 7 on the bottom surface. The semiconductor chip 1 is bonded via a solder layer 8 on the substrate 9 having a patterned wiring (not shown) on the top thereof.
In more particular, formed on the semiconductor substrate 1 is a polycrystalline silicon wiring 21 via an underlaid oxide layer 20, on which the gate wiring 4 is formed, as illustrated in
In the manufacturing process of the semiconductor device 800, the metal layer 6 may sometimes be formed offset relative to the emitter electrode 2.
In the semiconductor device 810 shown in
The present invention is made for addressing the problem and is to provide the direct-lead-bonding type semiconductor device, preventing the gate wiring from being damaged, even where the metal layer is formed offset and over the gate wiring.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.
According to one of the aspects of the present invention, a semiconductor device, which includes a semiconductor substrate, a surface electrode on the semiconductor substrate, and a gate wiring on the semiconductor substrate, the gate wiring being spaced from the surface electrode. It also includes a metal layer on the surface electrode, a lead terminal plate connected onto the metal layer, and a polyimide layer covering the gate wiring.
The present invention will more fully be understood from the detailed description given hereinafter and accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention.
The semiconductor device 100 includes a semiconductor chip 1 such as an IGBT. The semiconductor chip 1 has an emitter electrode (surface electrode) 2 and a gate electrode 3 formed on the top surface thereof. Those electrodes are made of metal such as aluminum. Connected with the gate electrode 3 is a gate wiring 4 of metal such as aluminum. Also, bonded on the gate electrode 3 is a bonding wire 12 of metal such as aluminum.
An overcoat layer 5 of material such as silicon dioxide and silicon nitride is formed on the emitter electrode 2 and the peripheral region of the gate electrode 3, covering the top surface of the semiconductor chip 1.
Further formed on the emitter electrode 2 is a metal layer 6 having a multilayer structure such as a Ti/Ni/Au-layer structure. A metal deposition process may be used to selectively form the metal layer 6 on the emitter electrode 2, by covering a metal mask on the top surface of the wafer (semiconductor chip 1) and depositing the respective metal on the emitter electrode. In the multilayer structure of the metal layer 6, the Ti-, Ni- and Au-layers perform functions serving as an agent for improving the ohmic contact with the emitter electrode 2, an adhesive agent with the solder layer 11, and an antioxidant agent of the Ni-layer, respectively. Besides of the Ti/Ni/Au-layer structure, the metal layer 6 may have another multilayer structure such as Al/Mo/Ni/Au-layer structure and Al/Ti/Ni/Au-layer structure. Also, the metal layer 6 may be formed by a sputtering process as well. Further, although not specifically indicated in the following embodiments, the sputtering process may also be used for forming the metal layer 6.
The direct-lead-bonding type semiconductor device 100 includes a lead terminal plate 10 bonded on the metal layer 6 via the solder layer 11 of metal such as Ag—Sn alloy. The lead terminal plate 10 may be formed of metal such as copper, for connecting with an external device (not shown).
Moreover, the semiconductor chip 1 includes a collector electrode (reverse electrode) 7 on the bottom surface, which has a multilayer structure such as an Al/Mo/Ni/Au-layer structure. Also, the semiconductor chip 1 is bonded through a solder layer 8 on the substrate 9 having a patterned wire (not shown) on the top thereof. The substrate 9 is made of insulating material such as alumina.
In more particular, formed on the semiconductor chip 1 is a polycrystalline silicon wiring 21 via an underlaid oxide layer 20, on which the gate wiring 4 is formed, as illustrated in
In the semiconductor device 100, an overcoat layer 5 is used to cover the gate wiring 4, on which the polyimide layer 13 is formed. The polyimide layer 13 preferably has thickness in the range between about 10 μm and about 50 μm, for instance.
While
In the manufacturing process of the semiconductor device 110, after depositing the gate wiring 4 and the emitter electrode 2, the overcoat layer 5 is formed and then the polyimide layer 13 is formed. The overcoat layer 5 and the polyimide layer 13 are formed by means of typical photolithography and etching.
In general, after forming the polyimide layer 13, the metal layer 6 is deposited with use of a metal mask. In the semiconductor device 110, the metal mask is arranged offset to the left towards the gate electrode 4 so that the metal layer 6 is formed over and extends beyond the polyimide layer 13. Therefore, the semiconductor device has the metal layer 6, the solder layer 11, and the lead terminal plate 10 laminating on the polyimide layer 13.
Thus, the semiconductor device 110 of the first embodiment of the present invention includes the polyimide layer 13 formed over and adjacent the gate wiring 4, so as to eliminate a stepped portion which is otherwise formed close to the gate wiring of the conventional semiconductor device as indicated by a mark “A” in
In the above description with reference to
The semiconductor device 200 according to the second embodiment of the present invention is has a structure similar to that of the semiconductor device 100 of the first embodiment except that the overcoat layer 5 is eliminated.
Another function of the polyimide layer 13 serving as a protection layer may eliminate the overcoat layer 5. This skips the production step of the overcoat layer 5, and simplifies the manufacturing process, thereby reducing the production cost.
While the semiconductor device 100 includes a bonding wire 12 for connection with the gate electrode 3, the semiconductor device 300 includes a metal layer 6 deposited on the gate electrode 3, and a lead terminal plate 10 bonded on the gate electrode 3 via the solder layer 11.
The metal layer 6 on the gate electrode 3 may be deposited during the same production step as one on the emitter electrode 2, for example, by means of the deposition technique with the metal mask. The solder layer 11 for connection of the lead terminal onto the metal layer 6 over the gate electrode 3 may be made of Ag—Sn solder similar to one for connection of the lead terminal onto the metal layer 6 over the emitter electrode 2, and also the lead terminal over the gate electrode 3 may be made of copper similar to one over the emitter electrode 2.
As above, the direct-lead-bonding technique can be used for connection of the gate electrode 3 so that the resistance of the wiring to the gate electrode 3 can be reduced.
Also, it should be noted that the gate wiring based upon the direct-lead-bonding technique can be used in the semiconductor devices 100, 200 as well.
According to the fourth embodiment, the polyimide layer 13 is adapted to cover optional elements (functional elements) rather than the gate wiring of the semiconductor device. The semiconductor device 400 includes a temperature sensing element 150 as the optional or functional element in addition to the gate wiring (not shown).
As illustrated in
The cathode electrode 42 and the anode electrode 43 are connected via the wirings 151 with the terminals 152. To this result, the resistance of the diode 41 varying in accordance with the temperature is measured with reading across the terminals 152 to detect the temperature of the semiconductor chip.
According to the semiconductor device 400 of the fourth embodiment of
Therefore, even if the metal layer 6 is formed offset towards the temperature sensing element 150 from the emitter electrode 2, since the polyimide layer 13 performs a function serving as a buffer layer for reducing mechanical stress while bonding the lead terminal plate 10 via the solder layer 11 onto the metal layer 6, the temperature sensing element 150 can be prevented from being damaged.
The optional (functional) element may include a current-sensing element rather than the temperature sensing element 150.
According to the semiconductor device 500 shown in
As above, plating on the exposed region of the emitter electrode 2 that are not covered by the polyimide layer 13 causes the selective formation of the metal layer 17. This eliminates the necessity of precise alignment of the metal mask relative to the wafer when forming the metal layer 17, and avoids misalignment of the mask. Also, this allows the metal layer to be formed simultaneously both on the emitter electrode 2 and the gate electrode 3.
Further, according to the semiconductor device 500 of the present embodiment shown in
As described above for the first through fifth embodiments, while the IGBT is used as the semiconductor chip, the present invention can be adapted to any other power MOSFETs. When a lateral power MOSFET is used, the electrodes on both sides of the gate wiring are the source/drain electrodes.
Furthermore, the present invention can be adapted to any other diodes and CSTBT (Carrier Stored Trench Gate Bipolar Transistor) commercially available from Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan. Moreover, it can also be adapted to the device rather than the power semiconductor devices, such as the HVIC (High Voltage IC) and LSI.
Number | Date | Country | Kind |
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2005-333656 | Nov 2005 | JP | national |