Patent Application
20060091524
The present application claims the right of priority of Japanese Patent Application No.2004-318891 (filed Nov. 2, 2004, the title of the invention: “SEMICONDUCTOR MODULE, PROCESS FOR PRODUCING THE SAME, AND FILM INTERPOSER”), the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor module, and a process for producing the same. In particular, the present invention relates to the semiconductor module wherein a semiconductor element is superposed on a film member. Furthermore, the present invention relates to a film interposer.
In recent years, not only is an electronics device becoming smaller, but also such device is increasingly becoming sophisticated. This results in a high pin-count of a semiconductor composing the electronics device as well as a miniaturization of various components. Not only the number of wirings used for a printed board having the semiconductor element mounted thereon, but also a density of the printed board increases dramatically. Above all, the number of lead wires or leads extended from the semiconductor element (e.g. semiconductor chip) as well as the terminal number is increasing markedly. Therefore, a fine-pitch connection technique has become much more important in these days of an ongoing miniaturization of the printed board (i.e. wiring board).
At present, there are three main types of the fine-pitch connection technique: (i) wire bonding technique (WB); (ii) flip chip bonding technique (FC); and (iii) tape automated bonding technique (TAB). Each of them will be concisely described in the following paragraphs.
To begin with, the wire bonding technique will be described. Japanese Patent Kokai Publication No.4-286134, for example, discloses the wire bonding technique. In this technique, a gold wire (20 to 25 μm in diameter) is used to connect between an electrode of a semiconductor chip and an electrode of a lead frame. A connection between each electrode and the gold wire is achieved due to a so-called solid phase diffusion caused by a heat treatment or an ultrasonic wave treatment.
With reference to FIGS. 19(a) and (b), the wire bonding technique disclosed in Japanese Patent Kokai Publication No.4-286134 will be hereinafter described.
In a process of this technique, first, a die bonding of a semiconductor chip 501 and a part of a lead frame 504 (i.e. die pad) is carried out, followed by carrying out a wire bonding between wire bonding pads 502 of the semiconductor 501 and external terminals 505 of the lead frame 504 (i.e. inner lead parts) by means of boding wires 503. Subsequently, the area including the semiconductor chip 501 and inner leads of the external terminals 505 is sealed within a sealing resin 506. As a result, a resin sealing body (i.e. semiconductor module) 500 as shown in
There are, however, a few problems associated with the wire bonding technique. One of them is the fact that a packaging or mounting area of the semiconductor element (i.e. the module 500 including the semiconductor chip 501 as shown in
Another problem is related to a troublesome connection operation. In this technique, the wire bonding pads 502 of the semiconductor chip 501 are connected to the external terminals 505 by means of the bonding wire one by one. Thus, the more the terminals are provided, the more troublesome the connection operation becomes. Further another problem is related to the fact that, as shown in
In the second place, the flip chip bonding technique will be hereinafter described. Japanese Patent Kokai Publication No.2000-36504, for example, discloses (i.e. projecting electrode) is formed on the semiconductor chip, followed by connecting the bump to an electrode of a wiring board. The technique is characterized in that an electrode-forming surface of the semiconductor chip and an electrode-forming surface of the wiring board are facing each other.
With reference to
In a process of this technique, each of electrodes 604 of the semiconductor chip 605 is electrically connected to each of wiring patterns 602 of the board 601 via a bump 603. In other words, through the intervention of bumps 603, electrodes 604 of the semiconductor chip 605 having a sensitive area provided with a transistor are connected to predetermined wiring patterns 602 formed on the board 601. As a result, a clearance gap between the board 601 and the semiconductor 605 is formed. Subsequently, a resin material is poured into the clearance gap to form the sealing resin body 607. This causes the wiring pattern 602, the bump 603 and the electrode 604 to be embedded in the resin material. As a result, the semiconductor device 600 having a configuration as shown in
There are, however, a few problems associated with the flip chip bonding technique. One of them is the fact that an alignment of the semiconductor chip 605 with respect to the board 601 is hard to perform. The reason for this is that the bump 603 cannot be seen directly from the outside since the semiconductor chip 605 is superposed on the substrate 601 in such a manner that the electrode-forming surface of the semiconductor chip 605 faces downward. Another reason for the difficult alignment is that a pitch of the electrodes 604 of the semiconductor chip 605 for the case of the flip chip bonding technique is finer than the pitch of the external terminals for the case of the wire bonding technique.
Another problem is the fact the board 601 is liable to be expensive in the case of flip chip bonding technique. The reason for this is that the board 601 requires a fine wiring patterns 602 corresponding to the pitch of the electrodes 604 of the semiconductor chip 605. Another reason is that some boards 601 need to be stacked on each other to form a multilayer board in the case where a lot of input-output terminals are provided. Further another problem associated with the flip chip bonding technique is the fact that a coefficient of linear expansion of the semiconductor chip 605 needs to be matched with that of the board 601 as far as possible. Otherwise an undesired stress occurs in the bump 603. However, such matching is troublesome, which increases the production cost of the board 601.
Further another problem associated with the flip chip bonding technique is the fact that an additional operation steps and an additional cost related thereto are brought about. That is to say, the semiconductor chip 605 and the board 601 need to be interconnected through the intervention the bumps 603, followed by pouring the resin material (underfill agent) 607 into the clearance gap formed between the semiconductor chip 605 and the board 601, which in itself leads to increase in the number of operation steps as well as the production cost. Further another problem is the fact that the semiconductor chip 605 is less likely to adequately release heat therefrom due to an existence of the bumps 603 located between the semiconductor chip 605 and the board 601. The semiconductor chip 605 is connected to the board 601 in a point-contact mode, not in a plane-contact mode for the case of the wire bonding technique. This is why the heat is not effectively released in the case of the flip chip bonding technique. Further another problem associated with the flip chip bonding technique is the fact that the formation of the bump 600 in itself is hard to perform.
In the third place, the TAB technique will be hereinafter described. Japanese Patent Kokai Publication No.8-88245, for example, discloses the TAB technique. In this technique, the semiconductor chip is connected to an elongated tape having lead wirings thereon, and subsequently the resulting semiconductor provided with the lead wirings is punched out from the elongated tape to form a connection between the lead wiring and a board. Basically, these steps of the TAB technique are automatically carried out by means of a so-called reel-to-reel process.
With reference to
The semiconductor device shown in
In the shown semiconductor device 700, a solder bump 706 acts as an outer lead. Therefore, as shown in
There are, however, a few problems associated with the TAB technique. One of them is the fact that the TAB technique is troublesome to perform since an inner lead bonding (ILB) step is carried out independently of an outer lead bonding (OLB) step. Such two steps are essential for the TAB technique, one of which is a step for connecting the inner lead 703a to the electrode 701a of the semiconductor IC chip 701, and the other of which is a step for forming the solder bump 706 on the land 703b (see
It is, therefore, a main object of the present invention to provide a semiconductor module and a process for producing the same by means of a novel fine-pitch connection technique which is different from the wire bonding technique, the flip chip bonding technique and the TAB technique. Another object of the present invention is to provide a film interposer which is obtained by using of such a novel fine-pitch connection technique.
In order to achieve the object, the present invention provides a semiconductor module, comprising:
a semiconductor element (or a plurality of semiconductor elements) having a principal face on which an element electrode is formed; and
a film member composed of an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the layer (i.e. a wiring pattern embedded in the layer on the rear face),
wherein the semiconductor element is superposed on the film member so that the principal face of the semiconductor element is in contact with the front face of the insulating resin layer of the film member; and
a part of the wiring pattern of the film member extends through the insulating resin layer, so that said part is in contact with the element electrode of the semiconductor element.
In this semiconductor module, a pitch is defined or formed by means of the wiring pattern of the film member, and thus the fine-pitch is relatively easy to achieve. Incidentally, a junction obtained due to being in contact between a part of the wiring pattern and the element electrode serves to electrically interconnect the wiring pattern and the element electrode, and thereby the film member used in the present invention serves as an intermediate board located between the semiconductor element and the wiring board (e.g. motherboard). Therefore, the term “film member” is hereinafter referred to as a film interposer.
Such semiconductor module is produced by a process comprising the steps of:
(a) preparing a semiconductor element (or a plurality of semiconductor elements) having a principal face on which an element electrode is formed;
(b) preparing a film member composed an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the insulating resin layer;
(c) superposing the semiconductor element on the film member so that the principal face of the semiconductor element is in contact with the front face of the insulating resin layer of the film member; and
(d) pressing a part of the wiring pattern into the film member so that said part is in contact with the element electrode of the semiconductor element.
This process is a novel process for producing a semiconductor module in that it differs from the wire bonding technique, the flip chip bonding technique and the TAB technique of the prior art. According to the process, there is provided not only the above-mentioned semiconductor module but also a film interposer.
In a preferred embodiment, it is preferred that the film member be transparent. For example, the film member is made of a transparent resin such as a polyimide resin or an aramid resin, in which case the step (d) can be visually carried out. That is to say, an alignment between a part of the wiring pattern and the electrode of the semiconductor element is visually performed through the transparent film member. Incidentally, the insulating resin layer of film member may be a coating film obtained by applying an insulating resin over the principal face of the semiconductor element.
By pressing a part of the wiring pattern toward the interior of the insulating resin layer by means of a pressing tool (or pressure welding tool), said part of the wiring pattern extends through the insulating resin layer so that said part is in contact with the element electrode of the semiconductor element. Therefore, a cross-section of said part of the wiring pattern (i.e. cross-section of the junction) may be generally “U” in shape.
It is preferred that an ultrasonic wave be applied to the junction obtained by the pressing, in which case an ultrasonic bonding of the junction is formed. Prior to applying the ultrasonic wave, a plurality of metals may be disposed around the junction (i.e. around or on said part of the wiring pattern), which metals are selected from the group consisting of an aluminum, a gold, a silver, a platinum and a vanadium. In this case, during the application of the ultrasonic wave, the junction is melted to contain an alloy consisting of the above-mentioned plurality of metals and the wiring material (e.g. copper). It is preferred that a physical characteristic of said part of the wiring pattern be measured during the application of the ultrasonic wave. This leads to an understanding of the strength of the junction during pressing a part of the wiring patterns. As a result, the ultrasonic wave can be applied to such a degree that a desired strength of the junction is obtained.
In a preferred embodiment, a front face of the film member and a rear face of the film member which face is opposite to the front face may be approximately the same as the principal face of the semiconductor element in size. This will lead to achievement of a semiconductor module having a relatively small mounting area.
In a preferred embodiment, a front face of the film member and a rear face of the film member which face is opposite to the front face may be larger than the principal face of the semiconductor element in size. In this case, it is preferred that a solder ball be formed on the rear face of the film member.
In a preferred embodiment, the semiconductor of the present invention can further comprise a conventional interposer that is electrically connected to a wiring board wherein the film member is electrically connected to the interposer.
In a preferred embodiment, another film member may be superposed on said film member so that they are laminated to each other. In this case, the film member is considered as a film interposer, which will lead to achievement of a semiconductor module comprising a multilayer film interposer. The semiconductor element in this case may be a semiconductor wafer.
In a first modified embodiment of the above-mentioned semiconductor module and film interposer, there is provided a semiconductor module, comprising:
a semiconductor element having a principal face on which an element electrode is formed and a rear face of the semiconductor element which face is opposite to the principal face;
a film member composed of an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the insulating resin layer; and
a wiring board,
wherein the semiconductor element is mounted on the wiring board so that the rear face of the semiconductor element is in contact with the wiring board;
a front face of the film member and a rear face of the film member which face is opposite to the front face are larger than the principal face of the semiconductor element in size;
the film member is mounted over the semiconductor element so that the principal face of the semiconductor element is in contact with the front face of the insulating resin layer of the-film member;
the film member extends up to the wiring board around the semiconductor element; and
at least a part of the wiring pattern of the film member extends through the insulating resin layer so that said part of the wiring pattern is in contact with the element electrode of the semiconductor element, whereas at least a part of the wiring pattern other than said part of the wiring pattern extends through the insulating resin layer so that said at least a part of the wiring pattern other than said part of the wiring pattern is in contact with an electrode formed on said wiring board.
In a second modified embodiment of the above-mentioned semiconductor module, there is provided a semiconductor module, comprising:
a semiconductor element having a principal face and a rear face which is opposite to the principal face, on each of which an element electrode is formed; and
a film member composed of an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the insulating resin layer,
wherein the front face of the insulating resin layer of the film member is in contact with the principal face as well as the rear face of the semiconductor element so that the film member extends from the principal face of the semiconductor element through around a side face of the semiconductor element up to the rear face of the semiconductor element;
at least a part of the wiring pattern of said film member extends through said insulating layer so that said part is in contacted with the element electrode formed on the principal face of said semiconductor element; and
at least another part of the wiring pattern of said film extends through said insulating resin layer so that said at least another part of the wiring patter is in contact with the element electrode formed in the rear face of said semiconductor element.
To sum up the above, according to the present invention, there is provided a semiconductor module wherein the principal face of the semiconductor element is in contact with the front face of the film member having the wiring pattern formed on the rear face thereof, and a part of the wiring pattern of the film member extends through the insulating resin layer so that said part is in contact with the element electrode of the semiconductor element. Therefore, there is also provided a fine-pitch connection technique that differs from the wire bonding technique, the flip chip bonding technique and the TAB technique.
The foregoing objects, features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description of preferred embodiments thereof, taken in conjunction with the accompanying drawings, in which:
FIGS. 6(a) to (d) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
FIGS. 8(a) to (c) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
FIGS. 9(a) and (b) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
FIGS. 10(a) to (c) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
FIGS. 11(a) and (b) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
FIGS. 12(a) and (b) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100.
In the drawings, the reference numbers correspond to the following elements: 10 . . . film interposer (film member), 11 . . . insulating resin layer, 11′ . . . coating film, 12 . . . element electrode, 18 . . . carrier sheet, 19 . . . metal layer, 20 . . . wiring pattern, 22, 23 . . . a part of wiring pattern, 24 . . . land, 25 . . . interlaminar junction, 26 . . . wiring, 28 . . . terminal, 30 . . . semiconductor element, 30a . . . principal face of semiconductor element (electrode-forming surface), 32 . . . element electrode, 35 . . . semiconductor wafer, 40 . . . solder ball, 41 . . . wiring board, 42 . . . electrode of wiring board, 45 . . . interposer, 50 . . . pressing tool, 100 . . . semiconductor module, 200 . . . electronic circuit device, 205a . . . external electrode terminal layer, 207 . . . insulating resin layer, 209 . . . wiring circuit conductive layer, 500 . . . semiconductor module (semiconductor element), 600 . . . semiconductor device and 700 . . . semiconductor device.
With reference to the attached figures, a few embodiments of the present invention will be hereinafter described in more detail. As to the drawings, the constituent elements having a substantially similar function carry the same reference number for ease of the description. It will be noted that the present invention will not necessarily be limited to the following embodiments.
Turning now to
The semiconductor module 100 shown in
As shown in
The semiconductor element 30 used in the semiconductor module 100 of the present invention may be a semiconductor bare chip or a chip size package (CSP), for example. The thickness of the semiconductor element 30 may be for example 20 to 400 μm, preferably 50 to 400 μm. To be more specific, the semiconductor element 30 may be a memory IC chip, a logic IC chip, a system LSI chip or a LED chip (i.e. light emitting diode chip).
It is preferred that the element electrode 32 formed on the principal face 30a of the semiconductor module 100 be made of Al or Au, in which case the thickness of the element electrode may be for example 0.01 to 0.1 μm, preferably 0.05 to 0.1 μm.
The insulating resin layer 11 of the film member 10 used in the semiconductor module 100 of the present invention may be made of an insulating resin used for a conventional semiconductor module. Preferably, the insulating resin layer 11 is made of a transparent insulating resin, and thereby it is preferably made of a film (or core film) consisting of a polyimide or an aramid. Furthermore, the insulating resin layer 11 may be made of a polyphenylene sulfide (PPS), a polypropylene or a polymethl methacrylate. It will be noted that the insulating resin layer 11 may contain any other resin or material in addition to the above resin or material. The thickness of the insulating resin layer 11 is for example 1 to 30 μm, preferably 1 to 10 μm.
The wiring pattern 20 of the film member 10 used in the semiconductor module 100 of the present invention is preferably made of a copper, for example. The thickness of the wiring pattern 20 is preferably 1 to 35 μm, more preferably 1 to 12 μm.
In the semiconductor module 100 shown in
In order to obtain the semiconductor 100 shown in
In the semiconductor module 100, said part 22 of the wiring pattern 20 is in contact with the element electrode 32 of the semiconductor element 30, and preferably they are jointed or pressure-welded to each other. Thus, the resulting junction 25 serves to electrically interconnect the element electrode 32 of the semiconductor element 20 and the wiring pattern 20 of the film member 10. The term “junction” is also hereinafter referred to as “interlaminar junction”. As described above, the film member 10 corresponds to “film interposer” or “filmy interposer” since the film member 10 serves as an intermediate board located between the semiconductor element 30 and the wiring board (e.g. motherboard). Therefore, the film interposer of the present invention is composed of a sheet-like film (e.g. transparent or translucent film) 11 consisting of an insulating resin and the wiring patterns 20 formed on one face (i.e. rear face 10b) of the film 11, in which case a part 22 of the wiring pattern 20 extends through the film 11 so that said part 22 is exposed on the front face 10a of the film 11. A cross-section of the part 22 of the wiring pattern 20 is generally “U” in shape, in which case the bottom part of said “U”-shaped wiring pattern 20 is in contact with (or connected to) the element electrode 32 of the semiconductor element 30.
In this way, for the purpose of producing the semiconductor module 100 of the present invention, a connection technique using the film interposer is performed. It will be understood that such connection technique is different from the wire bonding technique, the flip chip bonding technique and the TAB technique.
Hereinafter, the applied or modified examples of the above-mentioned semiconductor module of the present invention will be described.
In the semiconductor 100 of the present invention, some solder balls 40 may be formed on the rear face of the film member 10. It is preferred that the solder balls 40 be two-dimensionally arranged. As shown in
In the embodiment shown in
As to the embodiment shown in
Even in the case where the principal face 30a of the semiconductor element 30 is approximately the same the front face 10a of the film interposer, a broader pitch than that of the element electrode 32 of the semiconductor element 30 can be obtained, when the wiring patterns 20 are arranged to form the grid alignment of lands on the film interposer 10 in which case the element electrodes 12 are arranged on the peripheral part of the semiconductor element 30.
Furthermore, in the case where the semiconductor element 30 is used as a semiconductor bare chip, a so-called PGA (pin grid array) package or BGA (ball grid array) package can be easily obtained when the film interposer 10 having the two-dimensionally arranged wiring pattern 20 (typically, the film interposer 10 having the grid alignment of the wiring patterns 20) is used. In addition, in the case of the semiconductor module 100 having a configuration shown in
In the semiconductor module 100 shown in
In
As with
In the configuration of
In the embodiment shown in
Unlike the case where the interlaminar junction 25 is composed of a via consisting a conductive paste material, the interlaminar junction 25 according to the present invention prevents a discordance of an impedance between wirings (wiring patterns) and vias (interlaminar junctions) because the interlaminar junction in the latter case consists of the same material as the wiring patterns in a seamless state. Also, due to fact that the interlaminar junctions 25 are made of the same material as that of the wiring patters 20 in the present invention, there is no difference between a thermal expansion coefficient of the interlaminar junction 25 and that of the wiring pattern 20, which will lead to a better reliability in connection.
Turning now to FIGS. 6(a) to (d), the production process of the semiconductor module 100 according to the present invention will be hereinafter described. FIGS. 6(a) to (d) show cross-sectional views illustrating the steps in a process for producing a semiconductor module 100 shown in
First, as shown in
Next, as shown in
Through the above-mentioned steps, the semiconductor module 100 of the present invention can be obtained. It will be understood that the film interposer 10 as shown in
In the embodiment of the present invention, the film 11 (i.e. insulating resin layer 11) of the film member 10′ is made of a polyimide or an aramid for example, in which case the film 11 is substantially transparent. Therefore, during the step for superposing the semiconductor 30 on the film member 10′, an alignment between the element electrode 32 and a part 22 of the wiring pattern 20 is easy to perform since the element electrode 32 can be seen through the transparent film 11.
It is possible to apply an ultrasonic wave upon pressing of the wiring patterns with the pressing tool 50. The application of the ultrasonic wave causes a contacting area of the interlaminar junction 20 to be ultrasonically-bonded, which will lead to achievement of the semiconductor module having a better connecting reliability. For example, in the case where the pressing tool 50 provided with a function of applying an ultrasonic wave is used, it is possible to carry out a pressing process and an ultrasonically-bonding process simultaneously. In order to obtain a stronger junction caused by the application of the ultrasonic wave, some metals (e.g. an aluminum, a gold, a silver, a platinum and/or a vanadium) except for copper of the wiring pattern may be disposed around a part 22 of the wiring pattern 20. This means that the resulting interlaminar junction 25 can contain an alloy consisting of the plural metals selected from the group consisting of a copper an aluminum, a gold, a silver, a platinum and a vanadium, due to the fact that such metals are melted when the ultrasonic wave is applied.
The frequency of the ultrasonic vibration is for example 40 kHz to 1 MHz, preferably 40 to 800 kHz. The generating power is for example 10 to 50 W, preferably 20 to 40 W. Furthermore, the applying time is for example 0.1 to 1 second, preferably 0.1 to 0.5 second.
It is preferred that a physical characteristic of a part of the wiring pattern 20 be measured during the application of the ultrasonic wave. The measured physical characteristic is a resistance of a part of each wiring pattern 20, or a degree of the dent or depression of each wiring pattern 20, for example. In the case where the application of the ultrasonic wave and the measurement of the physical characteristic (e.g. resistance) are concurrently carried out, a strength characteristic of the interlaminar junction 25 can be obtained in real time. This allows the ultrasonic wave to be applied to such a degree that a desired strength of the interlaminar junction 25 is obtained. It is only necessary to carry out the measurement of the physical characteristic at first one time or a few times, in which case, on the basis of the result of such measurement, an amount of the energy of the ultrasonic wave or a applying time and the like can be subsequently adjusted.
In the semiconductor module of the present invention and the process for the same, the junction ensures an electrical connection between a part of the wiring pattern 20 and the semiconductor module 30. Therefore, a procedure for a wire connection using thin metallic lines (gold wire) one by one, which is peculiar to the wire bonding technique, is excluded from the present invention. This results in a less labor for a process operation, compared with the wire bonding technique. To put it more clearly in perspective, in recent years, the number of the pins (input-output terminals) used in the semiconductor has been substantially increasing. It is speculated that the number of the pins will reach to 1000 (i.e. 1000 pin) in 2006, and reach to 2000 (i.e. 2000 pin) in 2010. It will be therefore understood that the wire bonding technique will be very hard to perform in terms of a handling or processing for lots of pins. In the meanwhile, the semiconductor module of the present invention and the process for the same are advantageous in that lots of pins are easy to handle or process because lots of interlaminar junctions can be obtained all at once by means of a plurality of the needle-like members.
The semiconductor module of the present invention and the process for the same are advantageous in that the pitch can be defined by the wiring patterns 20, and thereby a fine-pitch connection technique whose pitch is finer than that for the case of the wire bonding technique can be achieved. It is speculated that the pin pitch of the semiconductor element will reach to 40 μm in 2006, and also reach to 20 μm in 2010. Therefore, the wire bonding technique will be very hard or virtually impossible to perform in terms of a handling for such fine-pitch, considering the diameter of the gold wire. In this respect, the semiconductor module of the present invention and the process for the same are advantageous in that such fine-pitch is easy to achieve because the fine pitch in this case can be defined or obtained by means of the wiring patterns.
Furthermore, the semiconductor module of the present invention and the process for the same are advantageous in that a mounting area can be smaller than that of the semiconductor for the case of the wire bonding technique because the film interposer can be properly superposed on the semiconductor element (e.g. bare chip). For example, on the basis of the semiconductor module 100 shown in
Furthermore, the semiconductor module of the present invention and the process for the same are advantageous in that the position or arrangement of the element electrode 32 of the semiconductor element 30 can be confirmed through the transparent film 11 upon superposing the semiconductor 30 on the film member 10′. That is to say, an alignment is easy to perform, compared with the case of the flip chip bonding technique. As a result, the semiconductor module of the present invention and the process for the same are easy to meet a tolerance requirement concerning the semiconductor element, compared with the case of the flip chip bonding technique.
As shown in
In the configuration of
a semiconductor element 30 having a principal face 30a on which an element electrode 32 is formed and a rear face 30b of said element which face is opposite to said principal face 30a;
a film member 10b composed of an insulating resin layer 11 having a front face 10a of said layer 11 and a rear face 10b of said layer 11 which face is opposite to said front face 10a, and a wiring pattern 20 formed on the rear face 10b of said insulating resin layer 11; and
a wiring board 41,
wherein said semiconductor element 30 is mounted on said wiring board 41 so that the rear face 30b of said semiconductor element 30 is in contact with said wiring board 41;
a front face 10a of said film member 10 and a rear face 10b of said film member 10 which face is opposite to said front face 10a are larger than the principal face 30a of said semiconductor element 30 in size, and said film member 10 is mounted over said semiconductor element 30 so that the principal face 30a of said semiconductor element 30 is in contact with the front face 10a of said film member 10, said film member 10 extending up to said wiring board 41 around said semiconductor element 30;
at least a part 22 of the wiring pattern 20 of said film member 10 extends through said insulating resin layer 11 so that said part 22 of the wiring pattern 20 is in contact with the element electrode 32 of said semiconductor element 30, whereas at least a part 23 of the wiring pattern 20 extends through said insulating resin layer 11 so that said part 23 of the wiring pattern 20 is in contact with an electrode 42 formed on said wiring board 41.
In the case of the flip chip bonding technique, the connection between the semiconductor element and the wiring board is hard to visually confirm due to the fact that the electrode-forming surface of the semiconductor element faces toward the wiring pattern of the wiring board. In the meanwhile, in the case of the semiconductor as shown in
The semiconductor module of the present invention and the process for the same are advantageous in that the cost concerning the wiring board is alleviated compared with the case of the flip chip bonding technique, because the fine-patterned wirings, which are supposed to be formed on the wiring board for the case of the flip chip bonding technique, can be formed on the film interposer (i.e. film member) in the case of the present invention. Furthermore, in the case of the flip chip bonding technique, the more the number of the terminals increases at a particular region (i.e. the wiring board region facing toward the principal face of the semiconductor element), the more the number of layers of the wiring boards is required. Meanwhile, in the case of the semiconductor module of the present invention and the process for the same, the wiring can be provided by means of the wiring pattern of the film interposer, which leads to less number of layers of the wiring boards. From this standpoint, the cost of the wiring board is furthermore alleviated in the case of the semiconductor module of the present invention and the process for the same. According to the present invention, a multilayer film interposer can be obtained with comparative ease, as shown in FIGS. 3 or 4. In addition, as shown in
The semiconductor module of the present invention and the process for the same are advantageous in that the matching between a linear thermal expansion coefficient of the semiconductor element 30 and that of the film interposer 10 is relatively alleviated, compared with the case of the flip chip bonding technique. That is to say, the film interposer (or film) of the present invention is so thin that it has less effect on the semiconductor element. And also, the flexibility of the film can absorb a stress that may occur due to the disparity between the linear thermal expansion coefficients of the semiconductor element and the film interposer.
Furthermore, the semiconductor module of the present invention and the process for the same are advantageous in that the connection between the semiconductor element and the wiring board is formed without an underfill agent (sealing resin) that is essential in the case of the flip chip bonding technique. It will be noted that, in the case of the semiconductor module of the present invention, the film interposer can protect the principal face of the semiconductor element on which face the element electrodes are formed.
In the semiconductor module of the present invention and the process for the same, a bump (e.g. solder bump or gold bump) may be on the element electrode of the semiconductor element. However, the element electrode having no bump can be alternatively used. Therefore, unlike the case of the flip chip bonding technique, it is possible to electrically interconnect the semiconductor element and the wiring board without forming the bump on the element electrode.
Next, the comparison with the TAB technique will be hereinafter described. In the TAB technique, it is required that the inner lead bonding step and the outer-lead bonding step are independently carried out. In contrast to that, the semiconductor module of the present invention does not require such separate steps. Furthermore, in the case of the semiconductor module of the present invention, there is no need to use the sealing resin used for case of the TAB technique. In addition, a smaller mounting area can be achieved.
Although the examples of the attached figures (e.g.
Turning now to FIGS. 8 to 12, another production process of the present invention and semiconductor module obtained by such process will be hereinafter described.
In the production process described above with reference to FIGS. 6(a) to (d), the film member 10′ comprises the insulating resin layer 11, but not limited to that. By applying an insulating resin over the principal face 30a of the semiconductor 30, a coating film can be used as the insulating resin layer 11. The relevant production process will be hereinafter described.
First of all, as shown in
Subsequently, as shown in
Subsequently, as shown in
According to such process, the coating film 11′ is used as a film 11, and therefore there is no need to prepare the film member 10′ having the wiring patterns 20. In the case where a facility or means for transferring the wiring pattern is already prepared, such production process is relatively convenient.
Alternatively, the semiconductor module of the present invention can be produced by means of another process shown in FIGS. 10(a) to 12(b). Such process will be hereinafter described.
First of all, the patterning process for forming wiring patterns 20 from the metal layer 19 on the carrier sheet 18 is carried out (see FIGS. 10(a) and 10 (b)). Subsequently, such wiring patterns 20 are transferred to an insulating resin layer 11A superposed on an film 11B in the direction indicated by the arrow 60 of
In parallel with that, the semiconductor element 30 as shown in
Subsequently, as shown in
Alternatively, the semiconductor module of the present invention can be obtained without the step shown in
As described above, it is preferred that an aramid film be used as the film 11B. The reason for this is that, even in the case where the aramid film is thinner than a polyimide film, a desired strength is easy to achieve, and that the aramid film is cheaper than the polyimide film. To put it another way, the aramid has a high elasticity-strength so that it is suitable for forming a thin film. For example, about 4 μm of the aramid film thickness corresponds to about 12.5 μm of the polyimide film thickness in terms of their strengths. Furthermore, even in terms of a low absorptivity and a dimensional stability, the aramid film is preferable.
The aramid film has a high heat-resisting characteristic. Thus, in the case where the heat-resisting properties are required, it is more preferable to use the aramid film, than to use the polyimide film.
According to the production process using the above-mentioned transferring technique, the resulting wiring patterns 20 are advantageous in terms of a better surface flatness since the wiring patterns are transferred to bury them in the insulating resin layer 11 (or 11A). Furthermore, such transferring technique can give a finer pitch of the wiring pattern than that for the case of a wet etching technique because the wiring patterns 20 made of copper foil are used in the case of the transferring technique. For example, a line/space (L/S) of the wiring patterns for the case of the wet etching technique is 40 μm/40 μm, whereas a line/space (L/S) of the wiring patterns for the case of the transferring technique can be very fine 15 μm/15 μm (i.e. 30 μm pitch).
It will be noted that the wiring patterns 20 obtained by means of the wet etching technique can also be alternatively used. For example, for the purpose of obtaining the film member 10′ as shown in
Further another modified embodiment of the present invention will be hereinafter described with reference to FIGS. 13 to 17. For ease of explanation, the relevant matters similar to those of the above-mentioned embodiment 1 will be abbreviated or omitted.
In the above embodiment 1, one semiconductor element 30 is mounted or superposed on one-film interposer 10. In contrast to that, as shown in
a semiconductor element having a principal face on which an element electrode is formed;
a film member (i.e. film interposer) composed of an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the layer, and
one or more another semiconductor element(s) having a principal face on which an element electrode is formed,
wherein each of said semiconductor elements is superposed on the film member so that the principal face of each of said semiconductor elements is in contact with the front face of the insulating resin layer of the film member; and
a part of the wiring pattern of the film member extends through the insulating resin layer, so that said part is in contact with the element electrode of the former semiconductor element, and also at least another part of the wiring pattern of the film member extends through the insulating resin layer, so that said another part is in contact with the electrode of the latter semiconductor element(s) (i.e. said another semiconductor element(s)).
In the configuration shown in
In the example, shown in
As shown in
The film interposer 10 can be used according to the embodiment as shown in
Therefore, in other words, the semiconductor module 100 shown in
a semiconductor element (corresponding to the combination of semiconductor elements 30A and 30B) having a principal face and a rear face which is opposite to the principal face, on each of which an element electrode is formed; and
a film member composed of an insulating resin layer having a front face and a rear face which is opposite to the front face, and a wiring pattern formed on the rear face of the insulating resin layer,
wherein the front face of the insulating resin layer of the film member is in contact with the principal face as well as the rear face of the semiconductor element so that the film member extends from the principal face of the semiconductor element through around a side face of the semiconductor element up to the rear face of the semiconductor element;
at least a part of the wiring pattern of said film member extends through said insulating layer so that said part is in contacted with the element electrode formed on the principal face of said semiconductor element; and
at least another part of the wiring pattern of said film extends through said insulating resin layer so that said at least another part of the wiring patter is in contact with the element electrode formed in the rear face of said semiconductor element.
The semiconductor module and the film interposer as shown in
As described above with reference to
The film interposer 10 having the configuration shown in
Although the present invention has been hereinabove described with reference to preferred embodiments, it will be understood by those skilled in the art that the present invention is not limited to such embodiments and can be modified in various ways.
As an additional remark, Japanese Patent Kokai Publication No. 4-283987 will be hereinafter described, although an electronic circuit device disclosed in this publication is fundamentally different from the present invention in terms of their technical meanings. The structure of such electronic device is shown in
In the electronic circuit device 200 shown in
Furthermore, as another additional remark, Japanese Patent Kokai Publications Nos. 4-283987 and 49-27866 will be hereinafter described although technologies disclosed in these publications are fundamentally different from the present invention in terms of their technical meanings. They substantially relate to the technology wherein a part of the wiring pattern is crashed through the insulative layer and then connected to the metal substrate (e.g. aluminum substrate) for the purpose of ensuring an electrical connection between the wiring pattern and the metal substrate. In this technology, a screw tool is not used. By means of a connecting tool for connecting between a part of the wiring pattern and the metal substrate, the relatively soft surface of the aluminum substrate is deeply caved so that the surface of the substrate is deformed. Thus, in the case where this technology is carried out with respect to the element electrode the semiconductor element used in the present invention, the semiconductor element will be damaged. Incidentally, what are disclosed in those publications are alternative ways of the connection technique using the screw. It is a matter of course that they are not related to the fine-pitch connection technique such as the wire bonding, flip chip bonding and TAB techniques, and therefore they are fundamentally different from the present invention.
The present invention provides the semiconductor module obtained by means of a novel fine-pitch connection technique, not the wire bonding, flip chip bonding and TAB techniques of the prior art. The present invention also provides the process for producing such semiconductor module.
In order to make full use of the characteristics of the semiconductor module of the present invention, such module can be mounted on a smaller and thinner electronic device whose mounting area is extremely limited. Thus, the semiconductor module of the present invention is used for various purposes. For example, the semiconductor module of the present invention is preferably used for a cellular phone. Furthermore, the semiconductor module of the present invention can be also used for a PDA, a notebook computer, a digital still camera, a thin-shaped television (i.e. FPD: flat-panel display) and the like.
In the case where a LED chip is used as the semiconductor element, the wiring pattern of the film interposer ensures an electrical continuity, which will lead to achievement of a luminescence device. That is to say, a semiconductor module or semiconductor device wherein light is emitted through the film can be obtained.
Furthermore, in the case where a LED chip is used as the semiconductor element, this will also lead to achievement of a luminescence device wherein two kinds of lights emitted from the LED chip and fluorescent material respectively are utilized. In the case where the semiconductor module of the present invention is used as a white light-emitting device, a blue LED chip serving to emit blue light is used as the semiconductor element, and also a yellow fluorescent material serving to emit yellow light is used as a fluorescent material serving to distribute light over the film. In this case, a gallium nitride (GaN)-based material may be appropriately used as the LED chip, and YAG-based fluorescent material and the like may be appropriately used as the fluorescent material. It will be noted that not only the blue LED chip but also an ultraviolet LED chip serving to emit ultraviolet light can be also used. In this case, the white light-emitting device can be obtained wherein the fluorescent material serving to emit red light (R), green light (G) and blue light (B) due to the excitation by means of light emitted from the ultraviolet LED chip is distributed over the film. It is a matter of course that a desired light-emitting device can be also obtained by selecting the LED chip and the fluorescent material appropriately.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2004-318891 | Nov 2004 | JP | national |
