Patent Application
20090001604
The present invention relates to a semiconductor package that carries one or a plurality of semiconductor elements on a wiring layer, and a method for producing same.
In recent years, the number of terminals in semiconductor devices has increased along with increasing speeds and levels of integration, and the pitch of regions between terminals has also narrowed. For this reason, higher density and finer detail is desired in the wiring substrates on which these semiconductor elements are to be mounted. Recently, ceramic substrates, build-up substrates, tape substrates, and the like have commonly been used as mounting substrates.
Ceramic substrates are composed of an insulating substrate made from alumina or the like and a wiring conductor made from high-melting metal material such as tungsten (W) or molybdenum (Mo) formed on this insulating substrate (e.g., refer to patent document 1). In patent document 1, a semiconductor package is described employing a ceramic multilayer substrate produced by alternate layering of wiring layers and insulating layers composed of aluminum nitride.
Build-up substrates are produced by forming an insulating layer composed of resin on both surfaces of a printed substrate and then using an etching method and plating method to produce multiple layers by forming fine circuits of copper wiring on this insulating layer. The circuits on the front surface and circuits on the back surface are connected via through holes or the like (e.g., refer to patent documents 2 and 3). For example, patent document 2 describes a BGA (ball grid array) package in which semiconductor elements are carried on the surface of a build-up substrate, and molding resin seals the semiconductor elements and bonding wires that connect the semiconductor elements with the wiring formed on the surface of the substrate. With this BGA package, solder bumps are connected with the wiring formed on the back surface of the build-up substrate. In addition, patent document 3 describes a package for semiconductor devices that employs a build-up substrate in which an insulating layer composed of polyimide or the like is provided on one surface of a metal base composed of copper or aluminum in which a prescribed pattern is formed, with a wiring pattern formed on this insulating substrate. With this package for semiconductor devices, solder bumps are connected with the metal base pattern along with connection of semiconductor chips on the wiring pattern, and the semiconductor elements and wiring patterns are sealed with a cap formed from metal or resin.
In addition, tape substrates have wiring composed of copper or the like formed on an insulating film composed of polyimide or the like (e.g., refer to patent document 4). Patent document 4 describes a carrier tape in which a wiring pattern composed of copper is formed on one surface of a polyimide film, with a frame-form reinforcing part composed of copper formed on the other surface. In addition, via holes are provided to the inside of the frame-form reinforcing part from the side of the polyimide film.
Furthermore, in the past, semiconductor devices and methods for their production have been offered in which a thinner profile and improved semiconductor element dimensional stability prior to mounting have both been achieved by forming the wiring layer on a support substrates and then removing the support substrate after mounting the semiconductor elements (e.g., refer to patent documents 5 to 7).
In addition, in the method for producing semiconductor devices described in patent document 6, a resin layer with poor adhesion with respect to silicon is formed on a support substrate composed of silicon, and a wiring layer is formed on this resin layer. In addition,
[Patent document 1] Japanese Laid-Open Patent Application No. 8-330474
[Patent document 2] Japanese Laid-Open Patent Application No. 11-17058
[Patent document 3] Japanese Patent Publication No. 2679681
[Patent document 4] Japanese Laid-Open Patent Application No. 2000-58701
[Patent document 5] Japanese Laid-Open Patent Application No. 2003-142624
[Patent document 6] Japanese Laid-Open Patent Application No. 2000-347470
[Patent document 7] Japanese Laid-Open Patent Application No. 2003-174153
However, the above prior art has the following problems. Firstly, when a ceramic substrate such as the semiconductor package described in patent document 1 has been used, damage such as breakage or defects readily occurs in the substrate during production and transport because the ceramic is hard and brittle, and problems are accordingly presented in regard to loss of yield. In addition, when a ceramic substrate is used, the substrate is produced by printing wiring on a green sheet prior to firing, layering each of the sheets, and then firing. In this production process, however, shrinkage occurs as a result of high-temperature firing, causing warping of the fired substrate, which tends to produce shape defects such as deformation and dimensional variability. Due to the occurrence of these shape defects, the ceramic substrate is not sufficiently amenable to the extremely high levels of planarity required of substrates such as high density circuit substrates and flip chips. Specifically, due to shape defects, using ceramic substrates makes it more difficult to increase the density, the level of detail, and the pin numbers in the circuits. The planarity of the mounting regions for the semiconductor elements is also inferior. As a result, cracking, separation, and the like tend to occur in the regions of contact between the semiconductor elements and the substrate, and there are problems with loss of semiconductor element reliability.
In addition, when a build-up substrate is used, as with the semiconductor package described in patent documents 2 and 3, there are problems with the generation of substrate warping due to differences in thermal expansion between the printed substrate used as the core material and the resin insulating film formed on the surface thereof. As described above, substrate warping leads to damage during connection with semiconductor elements having large pin numbers and also reduces yield and impedes higher circuit density and detail.
When a tape substrate such as the carrier tape described in patent document 4 is used, shifting during mounting of the semiconductor elements increases as a result of shrinkage of the tape substrate, and a problem arises in that the substrate is not sufficiently amenable to increased circuit density.
When semiconductor package thickness is reduced by utilizing the poor adhesion between Cu and ceramics, as with the semiconductor device production method described in patent document 5, with certain ceramic materials the Cu disperses into the ceramic plate during production of the wiring regions, which increases binding in these regions and causes problems in regard to eventually achieving reliable separation. A further problem is presented in that the sputtered Cu layer is oxidized during processing, and separation occurs during wiring layer formation, making reliable production impossible.
As with the production method for semiconductor devices described in patent document 6, when a separation layer formed from a resin, specifically, the polyimide film exemplified in patent document 6, is used, swelling (floating) occurs between the resin layer and the silicon substrate during thermal treatment of the separating layer. A problem accordingly arises in that wiring layers cannot be produced thereupon.
When the thickness of a semiconductor package is reduced by utilizing the poor adhesion between oxide layers and metal layers or nitride layers, as with the production method for semiconductor devices described in patent document 7, the film formation temperature of the oxide layer is higher than the film formation temperature of the metal layer or nitride layer, leading to increased binding at the interface between the oxide layer and the metal layer or nitride layer, and causing problems with separation. The oxide layer remaining on the wiring layer side after separation is brittle; therefore, cracking loci tend to arise in subsequent steps, and a problem arises in that reliable production is not possible.
With the foregoing problems in view, it is an object of the invention to provide a semiconductor package and method for producing same, whereby higher densities, increased detail and reduced thickness can all be realized.
The semiconductor package pertaining to the first invention of this application has a substrate; an oxide layer formed on this substrate; a metal layer that is formed on this oxide layer and is composed of at least one metal selected from the group consisting of gold, platinum, palladium, rhodium, ruthenium, iridium and osmium; a wiring body formed on this metal layer and provided with at least one wiring layer; and one or a plurality of semiconductor elements mounted on this wiring body.
The wiring body is formed on the substrate in the present invention; therefore, the incidence of warping or other shape defects is low, and favorable planarity can be realized, making the invention well-suited for narrow pitches of about 20 to 50 μm in the gaps between the contact pads. As a result, an increase in the density and detail of the wiring body patterns can be realized while favorable connection reliability is preserved in the semiconductor device and semiconductor package yield is improved. In addition, with the semiconductor package, an oxide layer and a metal layer composed of a gold- or platinum-group metal are provided, so reliable separation can occur at the interface between the oxide layer and the metal layer, and the thickness can be dramatically reduced relative to semiconductor packages that employ conventional build-up substrates. In addition, the substrates that are used at this time can be reused, dramatically reducing production costs. Because the oxide layer and metal layer have appropriate binding strength, separation will not occur unless force is applied, allowing reliable performance of the wiring body formation step and semiconductor element mounting step.
The interface between the oxide layer and the metal layer preferably has lower binding strength relative to the other interfaces. Separation is thereby facilitated at the interface between the oxide layer and the metal layer.
The oxide layer can be formed from at least one oxide selected from the group consisting of TiO2, Ta2O5, Al2O3, SiO2, ZrO2, HfO2, Nb2O5, perovskite-type oxides, and Bi-based layered oxides. In this case, the perovskite oxide is, for example, at least one oxide selected from the group consisting of BaxSr1-xTiO3 (where 0≦x≦1), PbZrxTi1-xO3 (where 0≦x≦1), and Pb1-yLayZrxTi1-xO3 (where 0≦x≦1 and 0<y<1). The Bi-based layered oxide is, for example, at least one oxide selected from the group consisting of BaxSr1-xBi2Ta2O9 (where 0≦x≦1) and BaxSr1-xBi4Ti4O15 (where 0≦x≦1).
In addition, the substrate can be formed from one material selected from the group consisting of semiconductor materials, metals, quartz, ceramics, and resins. In this case, examples of semiconductor materials include silicon, sapphire, and GaAs.
With these semiconductor packages, the wiring body may have insulating layers formed as top layers and/or bottom layers on the wiring layers. The wiring body also has electrodes that are electrically connected with the wiring layer formed on the surface on which the semiconductor element is mounted, and the semiconductor element may be electrically connected with the electrodes by means of one material selected from the group consisting of low-melting metals, conductive resins, and metal-containing resins. In this case, the semiconductor element can be connected as a flip chip.
In addition, there may also be a sealing resin layer that seals the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted. In this case, the thickness of the sealing resin layer is preferably greater than the thickness of the semiconductor elements. In addition, the sealing resin layer, for example, can be formed from epoxy resin containing silica filler. Separation at the interface between the oxide layer and metal layer can accordingly be made to occur via the force generated when the resin cures during sealing resin layer formation.
The method for producing the semiconductor package according to the second invention of this application involves forming an oxide layer on the substrate, forming a metal layer composed of at least one metal selected from the group consisting of gold, platinum, palladium, rhodium, ruthenium, iridium, and osmium on the oxide layer, forming a wiring body having at least one layer of wiring layer on the metal layer, and mounting one or a plurality of semiconductor elements on the wiring body.
In the present invention, an oxide layer is formed on the substrate, and a metal layer formed thereupon is composed of at least one metal selected from the group consisting of gold, platinum, palladium, rhodium, ruthenium, iridium, and osmium. Consequently, a suitable force is applied, thereby bringing about separation. As a result, a high-density detailed wiring body can be reliably formed, and the substrate can be readily removed after the semiconductor element has been mounted.
This semiconductor package production method may also have a step involving separation at the interface between the oxide layer and the metal layer, thereby facilitating a reduction in thickness. In this case, patterning of the metal layer can be carried out after separation at the interface between the oxide layer and metal layer, thereby forming wiring or electrodes. Other semiconductor devices and semiconductor components can also be mounted, and increased functionality as a semiconductor device can be realized. Moreover, the wiring body is thin; therefore, the wiring distance between semiconductor devices mounted on both sides is shortened, allowing realization of high-speed signal transmission and increased bus width.
In the separation step referred to above, separation may be carried out by mounting the semiconductor elements and then forming a sealing resin layer so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element has been mounted. In this case, the thickness of the sealing resin layer can be greater than the thickness of the semiconductor elements, and the sealing resin layer can be formed from an epoxy resin containing silica filler.
The oxide layer can be formed from at least one oxide selected from the group consisting of TiO2, Ta2O5, Al2O3, SiO2, ZrO2, HfO2, Nb2O5, perovskite-type oxides, and Bi-based layered oxides. In this case, the perovskite oxide is, for example, at least one oxide selected from the group consisting of BaxSr1-xTiO3 (where 0≦x≦1), PbZrxTi1-xO3 (where 0≦x≦1), and Pb1-yLayZrxTi1-xO3 (where 0≦x≦1 and 0<y<1). The Bi-based layered oxide is, for example, at least one oxide selected from the group consisting of BaxSr1-xBi2Ta2O9 (where 0≦x≦1) and BaxSr1-xBi4Ti4O15 (where 0≦x≦1).
In addition, the substrate can be formed using one material selected from the group consisting of a semiconductor material, metal, quartz, a ceramic, and a resin. In this case, the semiconductor material is, for example, one semiconductor material selected from the group consisting of silicon, sapphire, and GaAs.
Moreover, the semiconductor element and electrodes that are electrically connected with the wiring layer provided in the wiring body may be connected together using one material selected from the group consisting of a low-melting metal, a conductive resin, and a metal-containing resin. In this case, the semiconductor element can be connected as a flip chip.
According to the present invention, a wiring body is formed on a substrate, thereby allowing a wiring body provided with high density and high detail to be formed without any shape defects. Moreover, a laminated film formed from an oxide layer and a gold- or platinum-group metal can be provided between the substrate and wiring body. As a result, the substrate can be separated at the interface between the oxide layer and metal layer by applying a force after mounting the semiconductor elements on the wiring body, thus allowing the thickness to be easily reduced.
1: substrate
2, 113: oxide layer
3: metal layer
4
a, 4b, 44, 102, 115: wiring layer
5
a, 5b: insulating layer
6, 36: electrode
7: wiring body
8
a, 8b: via
9: underfill
10: solder ball
11, 103, 104: semiconductor element
12: sealing resin
20, 30, 40, 50: semiconductor package
100: semiconductor device
101, 111: support substrate
105: solder bump
106: package substrate
112: metal layer or nitride layer
114: insulating layer
The semiconductor package according to the embodiments of the present invention is described in detail below in reference to the attached drawings. First, the semiconductor package of Embodiment 1 of the present invention will be discussed.
The substrate 1 of the semiconductor package 20 of this embodiment preferably has suitable rigidity, and a substrate composed of a semiconductor wafer material such as silicon, sapphire, GaAs, or the like; a metal substrate; a quartz substrate; a glass substrate; a ceramic substrate; or a printed wiring board may be used. When the semiconductor elements are to be connected at a narrow pitch of 100 □m or less, it is preferable to use a substrate composed of a semiconductor wafer material such as silicon, sapphire, GaAs, or the like; and it is particularly preferable to use the silicon substrate that is used in the semiconductor element.
The oxide layer 2 is a layer for optimizing the binding force with the metal layer 3, while also preventing the substrate 1 and the metal layer 3 formed thereupon from reacting. The layer may be formed, for example, from at least one oxide selected from the group consisting of perovskite oxides such as BaxSr1-xTiO3 (BST; where 0≦x≦1), PbZrxTi1-xO3 (PZT; where 0≦x≦1), and Pb1-yLayZrxTi1-xO3 (PLZT; where 0≦x≦1 and 0<y<1); Bi-based layered oxides such as BaxSr1-xBi2Ta2O9 (where 0≦x≦1) and BaxSr1-xBi4Ti4O15 (where 0≦x≦1); and TiO2, Ta2O5, Al203, SiO2, ZrO2, HfO2, and Nb2O5. Examples of formation methods that are suitable for use include sputtering methods, PLD (pulsed laser deposition) methods, MBE (molecular beam epitaxy) methods, ALD (atomic layer deposition) methods, MOD (metal organic deposition) methods, sol-gel methods, CVD (chemical vapor deposition) methods and anodizing methods.
The film thickness of the oxide layer 2 is preferably 10 to 600 nm, more preferably 50 to 300 nm. If the thickness of the oxide layer 2 is less than 10 nm, then it will not be possible to form a connected film on the substrate 1 due to roughness and steps present in the substrate 1. On the other hand, if the thickness of the oxide layer 2 exceeds 600 nm, then cracking will tend to occur due to internal stresses, and production costs will increase due to the extended film formation time.
The metal layer 3 can be formed from at least one metal selected from the group consisting of gold, platinum, palladium, rhodium, ruthenium, iridium, and osmium, thereby allowing optimization of the binding force between the oxide layer 2 and the metal layer 3. Specifically, the binding force at the interface of the oxide layer 2 and metal layer 3 is made lower than the binding forces at the other interfaces, and a value of 1.9 J/m2 or greater is produced based on binding evaluation using the four-point bend test. By decreasing the binding strength at the interface between the oxide layer 2 and the metal layer 3 to below the binding forces of the other interfaces, the substrate 1 can be readily and reliably separated. In addition, by making the binding force at the interface between the oxide layer 2 and metal layer 3 at least 1.9 J/m2, it is possible to prevent defects such as separation from occurring in subsequent steps. The method for evaluating binding carried out using the four-point bend test referred to above involves supporting the test piece between two rollers, and then measuring the maximum load until the point at which the test piece breaks while supplying the load using the two rollers from above the center of the test piece. From this maximum load, the externally released energy resulting from the occurrence of separation per unit surface area is determined as part of the elastic energy accumulated in the system due to flexural deformation. In this embodiment, the energy value determined by this method is used as the binding strength.
In addition, the metal layer 3 can be formed, for example, by using a sputtering method, colloidal method, CVD method, ALD method, or the like. The film thickness is preferably 10 to 400 nm, more preferably 100 to 200 nm. If the thickness of the metal layer 3 is less than 10 nm, then a connected film will not be formed on the oxide layer 2, whereas if the thickness of the metal layer 3 is greater than 400 nm, then production costs will increase due to an extended film formation time.
The oxide layer 2 and metal layer 3 need not be formed over just one surface of the substrate 1. For example, the oxide layer 2 and metal layer 3 may be formed over regions other than the periphery of the substrate 1, and the peripheral regions of the substrate 1 may be used for direct contact between the substrate 1 and insulating layer 5. The stability during package production can accordingly be increased.
The wiring body 7 is composed of wiring layers 4a and 4b, insulating layers 5a and 5b, vias 8a and 8b, electrodes 6, and the like. Specifically, the wiring layer 4a is formed on the metal layer 3, and the insulating layer 5a is formed so as to cover the metal layer 3 and wiring layer 4a. In addition, the wiring layer 4b is formed on the insulating layer 5a, and the wiring layer 4b is electrically connected with the wiring layer 4a by using the via 8a formed in the insulating layer 5a. In addition, the insulating layer 5b is formed so as to cover the insulating layer 5a and wiring layer 4b, and a plurality of electrodes 6 are formed on the insulating layer 5b. These electrodes 6 are electrically connected with the wiring layer 4b using the via 8b formed in the insulating layer 5b.
The wiring layers 4a and 4b in the semiconductor package 20 of this embodiment can be formed from at least one metal selected from the group consisting of copper, aluminum, nickel, gold, and silver, but copper is particularly preferred from the standpoint of electrical resistance and cost. When the wiring layers 4a and 4b are formed from nickel, reactions at the interface between the insulating layers 6a and 6b and other layers can be prevented, and it is possible to form an inductor or resistance wire having the characteristics of a magnetic material. In addition, the wiring 4a and 4b may be formed by means of a subtractive method, semi-additive method, or full-additive method. With subtractive methods, a resist of the prescribed pattern is formed on copper foil provided on a substrate composed of ceramic, resin, or the like. After etching the unwanted copper foil, the resist is removed to obtain the prescribed pattern. With semi-additive methods, electroless plating, sputtering or CVD is carried out in order to form a power supply layer, whereupon a resist that is open in the prescribed pattern is formed, and the electrolytic plating is deposited inside the open regions of the resist. After removing the resist, the power supply layer is then etched to obtain the prescribed wiring pattern. With full-additive methods, an electroless plating catalyst is adsorbed onto a substrate composed of ceramic, resin, or the like, whereupon a pattern is formed using a resist. Catalyst activation is then carried out with the resist remaining as an insulating film, and metal is deposited on the open regions of the resist film using an electroless plating method, thereby producing the prescribed wiring pattern.
In addition, insulating layers 5a and 5b are formed using photosensitive or non-photosensitive organic material such as polynorbornene, PBO (polybenzoxazole), BCB (benzocyclobutene), polyimide resin, phenol resin, polyester resin, urethane acrylate resin, epoxy acrylate resin, or epoxy. Of these photosensitive or non-photosensitive organic materials, polyimide resin and PBO can provide high reliability due to their superior mechanical characteristics such as film strength, tensile modulus, and break elongation.
The electrodes 6 can have a multilayered structure, for example. In this case, from the standpoint of solder ball wettability or ease of joining to the bonding wire, the top-most layer of the electrodes 6 is preferably formed from at least one metal selected from gold, silver, copper, aluminum, tin, and soldering material, or an alloy containing one or more of these metals.
The sealing resin layer 12 used in the semiconductor package 20 of this embodiment can be formed, for example, from epoxy resin containing silica filler. This sealing resin layer 12 is able to prevent water infiltrating the semiconductor element 11, while also protecting the semiconductor element from mechanical shock such as impact. After forming the sealing resin layer 12, it is preferable for the residual stress after sealing to be 0.3 to 34 MPa, specifically, 3 to 20 MPa.
Although corresponding wiring layers and insulating layers are provided to the wiring body 7 of the semiconductor package 20 in this embodiment, the present invention is not restricted to such cases. One or more individual wiring layer or insulating layer may also be provided. In addition, there are no particular restrictions on the sequence, and the insulating layer may be formed on the metal layer 3, whereupon the wiring layer may be formed thereupon.
With the semiconductor package 20 of this embodiment, the semiconductor 11 is connected as a flip chip using solder balls, but the present invention is not restricted to such a case. The semiconductor 11 may be attached to the wiring body 7 in a face-up condition, and may be connected to the wiring body 7 using wire bonding. In addition, when connecting as a flip chip, a method may be used involving bump connection or the like using low-melting metal or anisotropic conductive film rather than solder. In order to improve package rigidity, a stiffener composed of a metal frame or the like may be attached to the surface on which the semiconductor element 11 has been mounted.
Because the wiring body 7 is formed on the substrate 1 in the semiconductor package 20 of this embodiment, shape defects do not readily form, and detailed wiring layers 4a and 4b can be formed tightly, densely and at high density. In addition, a metal layer 3 composed of gold- or platinum-group metal and an oxide layer 2 are formed between the substrate 1 and the wiring body 7. Consequently, when a sealing resin layer 12, for example, is formed after mounting a semiconductor element on the wiring body 7, the substrate 1 can be separated off at the interface between the oxide layer 2 and the metal layer 3 using force, thereby allowing the thickness to be easily reduced.
The method for producing the semiconductor package 20 of this embodiment is described below.
As shown in
As shown in
Moreover, the binding strength at the interface between the oxide layer 2 and the metal layer 3 is lower than the binding strength at the other interfaces, and is preferably 1.9 J/m2 or greater based on binding evaluation carried out using the four-point bend test method. As a result, the substrate can be readily and reliably separated, and separation can be prevented from occurring in subsequent steps, specifically, steps prior to the formation of the sealing resin layer 12.
As shown in
Next, for example, an insulating layer 5a composed of a photosensitive or non-photosensitive organic material such as epoxy resin, epoxy acrylate resin, urethane acrylate resin polyester resin, phenol resin, polyimide resin, BCB, PBO, or polynorbornene resin is formed on the metal layer 3 so as to cover the wiring layer 4a, and a via 8a is then formed in this insulating layer 5a. When the insulating layer 5a is formed from photosensitive organic material, the opening region for forming the via 8a can be formed by photolithography. In addition, when the insulating layer 5a is formed from a non-photosensitive organic material or a photosensitive organic material having low pattern resolution, the opening for forming the via 8a can be formed using a laser processing method, dry etching method, or blast method. In addition, the via 8a can be formed by forming a plating post in advance in the position of the via 8a, then forming a resist layer 5a, and cutting away the insulating layer 5a by polishing to expose the plating post. With this method, it is not necessary to provide an opening region in advance in the insulating layer 5a.
Next, by a method similar to the method used for the wiring layer 4a described above, a wiring layer 4b that connects with the wiring layer 4b through the via 13a and is composed of at least one metal selected from the group consisting of, for example, copper, aluminum, nickel, gold, and silver is formed on the insulating layer 5a. In addition, by a method similar to the method used for the wiring layer 5a described above, an insulating layer 5b is formed that is composed of a photosensitive or non-photosensitive material such as epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB, PBO, polynorbornene resin, or the like so as to cover this wiring layer 4b. A via 8b is then formed on the insulating layer 5b by a method similar to the method used for the via 8a described above.
Next, for example, a copper thin film having a thickness of 2 μm, a nickel thin film having a thickness of 3 μm, and a gold thin film having a thickness of 1 μm are layered in sequence on the insulating layer 5b, and electrodes 6 are formed that are electrically connected with the wiring layer 4b through the via 8b. In the method for forming the semiconductor package in this embodiment, the top-most layer of the electrodes 6 is formed from gold, but the present invention is not restricted to such a case. The top-most layer of the electrodes 6 can be formed from at least one metal selected from the group consisting of gold, silver, copper, aluminum, tin, and solder material, or an alloy containing at least one of these metals. The wettability of the solder balls formed on the electrodes 6 or the connections thereof with the bonding wire is accordingly improved.
Next, as shown in
Next, as shown in
In the production method for the semiconductor package of this embodiment, the wiring layer 4a is provided to the metal layer 3, but the present invention is not restricted to such a case. An insulating layer may be formed on the metal layer 3, and the wiring layer may be formed thereupon. In addition, the oxide layer 2 and metal layer 3 need not be formed so as to cover one surface of the substrate 1. For example, the oxide layer 2 and metal layer 3 may be formed over regions other than the peripheral region of the substrate 1, and the peripheral region of the substrate 1 may be formed so that the substrate 1 and insulating layer 5 are in direct contact. The stability during package production can accordingly be improved.
In the method for producing the semiconductor package 20 of this embodiment, the wiring body 7 is formed on the substrate 1, and thus shape defects were inhibited, allowing detailed wiring layers 4a and 4b to be formed at high density. In addition, the oxide layer 2 and the metal layer 3 composed of gold- or platinum-group metal are formed in sequence on the substrate 1; therefore, the binding strength between these layers is not excessive, and the interface between the oxide layer 2 and the metal layer 3 can have a lower degree of binding than the other layers, with a value of 1.9 J/m2 or greater based on binding evaluation carried out using the four-point bend test method. As a result, the semiconductor element will not separate before being mounted on the wiring body 7. For example, forming the sealing resin layer 12 and applying force enables separation to occur at the interface between the oxide layer 2 and the metal layer 3.
The semiconductor package of Embodiment 2 of the present invention is described below.
The method for producing the semiconductor package 30 of this embodiment is described below.
In the production method for the semiconductor package of this embodiment, the stress generated as a result of molding the semiconductor element 11 using the sealing resin layer 12 is utilized for separation, but the present invention is not restricted to such a case. At the stage where the semiconductor element 11 has been formed, an external stress that is equivalent to the stress generated by contraction upon curing of the sealing resin layer 12 can be applied physically, thereby separating the oxide layer 2 and the metal layer 3. The method whereby a stress equivalent to the stress in the sealing resin layer is applied in this manner, for example, is a method in which a removable thick film resist is formed on the surface of the wiring body 7 on which the semiconductor element 11 has been mounted. A semiconductor package that does not have a sealing resin layer can accordingly be produced using a stiffener or heat spreader, as with FCBGA (flip chip ball grid array) packages and the like for semiconductors having in excess of 1000 connection pads.
In addition, at the stage where the wiring body 7 is formed, an external stress that is equivalent to the stress generated by shrinkage upon curing of the sealing rosin layer 12 may be physically applied to separate the oxide layer 2 and the metal layer 3. A thin substrate that is able to be employed in various applications can accordingly be produced. Moreover, after the substrate 1 has been separated, the form may be processed to the desired size, and, in cases where a plurality of semiconductor elements is mounted, separation between the elements can be carried out by dicing or the like.
A semiconductor package according to a first modified example of Embodiment 2 of the present invention is described below.
The method for forming the back surface electrodes 36 by processing the metal layer 3, for example, is a method wherein a resist that has been patterned into the desired form is used as a mask, and unwanted regions are removed by dry etching or wet etching. In addition, a wiring layer may be formed rather than the back surface electrodes 36. The metal layer 3 is a thin film, and the resist film used for etching can be made thin, thereby allowing detailed pattern formation of the type used for forming semiconductor wiring and also allowing an increase in the wiring utilization ratio. Moreover, because the metal layer 3 is formed from a gold- or platinum-group metal, oxidation does not readily occur and reliable metal bonding can be produced. In addition, because dense films can be formed by the film formation method, connections can be made using wire bonding, solder, or the like without performing a pretreatment.
Semiconductor elements can be mounted on both surfaces of the wiring body 7 in the semiconductor package of this modified example, thereby realizing higher functionality as a semiconductor device. In addition, because the wiring body 7 is thin, the wiring distance between semiconductor devices mounted on the two surfaces is short, and high-speed signal transmission and a broad bus width can be realized. Other configurations and effects of the semiconductor package of this modified example are similar to the semiconductor package of Embodiment 2 described above.
The semiconductor package according to a second modified example of Embodiment 2 of the present invention is described below.
Increased functionality as a semiconductor device can be realized in the semiconductor package 50 of this modified example. In addition, because the wiring body 7 is thin, the wiring distance between semiconductor devices mounted on the two surfaces is short, and high-speed signal transmission and a broad bus width can be realized. Other configurations and effects of the semiconductor package of this modified example are similar to the semiconductor package of Embodiment 2 described above.
The present invention is effective for increasing density, detail, and thinness in semiconductor packages.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-056233 | Mar 2005 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2006/303882 | 3/1/2006 | WO | 00 | 1/22/2008 |
