Semiconductor package containing multi-layered semiconductor chips

Abstract

According to this invention, a semiconductor package includes: a plurality of semiconductor chips, each having through electrodes; and a semiconductor interposer, on which the plurality of semiconductor chips are mounted. Each of the semiconductor chips includes: a semiconductor substrate; a wiring layer formed on the semiconductor substrate; an opaque resin layer sealing the wiring layer and a side surface of the semiconductor chip; and conductive bumps to be connected to the through electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plane view illustrating a semiconductor package, viewed from a semiconductor chip side, according to a first preferred embodiment of this invention;

FIG. 1B is a plane view (bottom view) illustrating a semiconductor package, viewed from a semiconductor interposer side, according to the first preferred embodiment of this invention;

FIG. 2A is a cross-sectional view taken on line A-A in FIG. 1A;

FIG. 2B is an enlarged cross-sectional view of region “B” in FIG. 2A;

FIGS. 3A-3C are cross-sectional views showing a part of fabrication process of a semiconductor package according to the first preferred embodiment of this invention;

FIG. 4A is a cross-sectional view illustrating a semiconductor package according to a second preferred embodiment of this invention;

FIG. 4B is an enlarged cross-sectional view of region “B” in FIG. 4A;

FIGS. 5A-5D are cross-sectional views showing a part of fabrication process of a semiconductor package according to the second preferred embodiment of this invention;

FIGS. 6A-6F are cross-sectional views showing a part of another fabrication process of a semiconductor package according to the second preferred embodiment of this invention;

FIG. 7A is a plane view illustrating a semiconductor package, viewed from a semiconductor chip side, according to a third preferred embodiment of this invention;

FIG. 7B is a plane view (bottom view) illustrating a semiconductor package, viewed from a semiconductor interposer side, according to the third preferred embodiment of this invention;

FIG. 8 is a cross-sectional view taken on line B-B in FIG. 7A;

FIG. 9 is a cross-sectional view illustrating a semiconductor package according to the third preferred embodiment, shown in FIG. 8, mounted on a mount board;

FIG. 10 is a cross-sectional view illustrating a semiconductor package, according to the third preferred embodiment, mounted on a mount board in another manner.

FIG. 11 is a cross-sectional view illustrating a semiconductor package according to a fourth preferred embodiment of this invention.

Claims

1. A semiconductor package, comprising: a plurality of semiconductor chips, each having through electrodes; anda semiconductor interposer, on which the plurality of semiconductor chips are mounted,wherein each of the semiconductor chips comprises: a semiconductor substrate; a wiring layer formed on the semiconductor substrate; an opaque resin layer sealing the wiring layer and a side surface of the semiconductor chip; and conductive bumps to be connected to the through electrodes.

2. A semiconductor package according to claim 1, wherein the semiconductor substrate is shaped to have a beveling portion at a peripheral corner surrounding the substrate, andthe opaque resin layer is formed on a surface of the beveling portion.

3. A semiconductor package according to claim 1, wherein the opaque resin layer is formed to have a uniform thickness at a side surface of the semiconductor substrate entirely.

4. A semiconductor package according to claim 1, wherein the semiconductor chips are memory chips.

5. A semiconductor package according to claim 1, wherein the semiconductor interposer has first and second surfaces, which are opposite to each other;the plurality of semiconductor chips is mounted on the first surface of the semiconductor interposer;a plurality of solder terminals are formed on the second surface of the semiconductor interposer; andthe plurality of solder terminals are to be connected electrically to a mount board.

6. A semiconductor package according to claim 1, wherein the semiconductor interposer has first and second surfaces, which are opposite to each other;the plurality of semiconductor chips is mounted on the first surface of the semiconductor interposer;a plurality of solder terminals are formed on the first surface of the semiconductor interposer;the plurality of solder terminals are to be connected electrically to a mount board;the mount board is shaped to have a hollow portion, in which the semiconductor package is contained; andthe semiconductor package is mounted in the hollow portion of the mount board so that the semiconductor interposer faces up.

7. A semiconductor package according to claim 6, wherein a heat radiating member, having a high thermal conductivity, is arranged between a bottom of the hollow portion and the semiconductor package.

8. A semiconductor package according to claim 7, wherein the heat radiating member is of a metal resin.