DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a known integrated circuit package after mounting process.
FIG. 2 is a cross-sectional view of a SIP package with small dimension in accordance with the first embodiment of the present invention.
FIG. 3 is a plan view of the SIP package in accordance with the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of another SIP package with small dimension in accordance with the second embodiment of the present invention.
FIG. 5 is a plan view of the SIP package with small dimension in accordance with the second embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
In the first embodiment of the present invention, as showed in FIGS. 2 and 3, a SIP package 200 mainly comprises a substrate 210, a carrying chip 220, one or more small size chips 230 and an encapsulant 240. The substrate 210 generally may be a multi-layer PCB and has an upper surface 211, a lower surface 212 and a slot 213. A plurality of fingers 214 is formed on the upper surface 211 and a solder resist layer 215 partially covers the traces that connect to the fingers 214. A plurality of fingers and a plurality of ball pads (not showed in the drawings) are formed on the lower surface 212.
The carrying chip 220 is disposed on the upper surface 211 of the substrate 200. The carrying chip 220 has an active surface 221 and a back side 222 opposing to the active surface 221. The active surface 221 is a surface with a plurality of integrated circuit components (not showed in the drawings) formed and the carrying chip 220 also has a plurality of bonding pads 223 on the active surface 221 serving as external electrodes. While performing chip-attaching process, the active surface 221 faces toward the substrate 210 allowing the bonding pads 223 to align within the slot 213. A plurality of third bonding wires 253 electrically connect the bonding pads 223 of the carrying chip 220 to the substrate 210 through the slot 213. Preferably, the active surface 221 of the carrying chip 220 occupies more than 70% of the upper surface 211 of the substrate 210 in area that achieves CSP (Chip Scale Package) in size. In this embodiment, the carrying chip 220 may be a memory chip.
The small size chips 230 are disposed on the back side 222 of the carrying chip 220 and the chip-attached area thereof is smaller than half of that of the back side 222. In this embodiment, the small size chip 230 may be micro controller chips, logic chips or RF chips, which may be packaged into SIP of various functions.
Referring to FIG. 3, the carrying chip 220 further includes a back side pattern 224 formed on the back side 222 of the carrying chip 220 to electrically connect the small size chips 230 to the substrate 210 and shorten length of bonding wires 252. The back side pattern 224 can be formed by applying existent integrated circuit fabricating process, in which it is formed during wafer fabrication process before the carrying chip 220 is sawed to separate. In addition, the carrying chip 220 further includes a passivation layer 226 on the back side 222 to cover the trace sections of the back side pattern 224, which may be made of PI, BCB or a solder resist layer.
Also, the back side pattern 224 has a plurality of transfer fingers 225 formed at the periphery of the back side 222 for electrically connecting the small size chips 230 to the substrate 210. The bonding pads 231 on the small size chips 230 are electrically connected to the back side pattern 224 via a plurality of first bonding wires 251 and also the transfer fingers 225 of the back side pattern 224 are electrically connected to the fingers 214 of the substrate 210 via a plurality of second bonding wires 252. Accordingly, loop height of the first bonding wires 251 will be reduced, and the wire length of the second bonding wires 252 will be shorter and regulated.
The encapsulant 240 is formed over the upper surface 211 of the substrate 210 to encapsulate the carrying chip 220, the small size chips 230, the first bonding wires 251 and the second bonding wires 252. Besides, the encapsulant 240 may further be formed in the slot 213 to encapsulate the third bonding wires 253. In this embodiment, the SIP package 200 further comprises a plurality of solder balls 260 disposed on the lower surface 212 of the substrate 210 to serve as external connections.
As a result, the small size chips 230 are integrated onto the back side 222 of the carrying chip 220 to form a SIP package with window BGA configuration, that decreases the length of used bonding wires to achieve miniaturization of SIP package and shorten conductive paths electrically between the carrying chip 220 and the small size chips 230 without increasing package size and thickness, and may even be surface mounted on a PCB 30 with still smaller size.
The second embodiment of the present invention is illustrated as showed in FIG. 4. Another SIP package 300 mainly comprises a substrate 310, a carrying chip 320, one or more small size chips 330 and an encapsulant 340. The substrate 310 has an upper surface 311, a lower surface 312 and a slot 313. The carrying chip 320 is disposed on the upper surface 311 of the substrate 310 and has an active surface 321 and a back side 322. The active surface 321 faces toward the substrate 310 that allows a plurality of bonding pads 323 of the carrying chip 320 to align within the slot 313. The bonding pads 323 are electrically connected to the substrate 310 via a plurality of third bonding wires 353 through the slot 313. The small size chips 330 are disposed on the back side 322 of the carrying chip 320 and the chip-attached area of the small size chips 330 is smaller than half of that of the back side 322 in area. The encapsulant 340 is formed over the upper surface 311 of the substrate 310 to encapsulate the carrying chip 320 and the small size chips 330. The carrying chip 320 further includes a back side pattern 324 which is formed on the back side 322 of the carrying chip 320 and connects to a plurality of PTHs 325 (Plated Through Holes) in the carrying chip 320 that are located at the periphery of the back side 322. The bonding pads 331 on the small size chips 330 are electrically connected to the back side pattern 324 via a plurality of first bonding wires 351 and also the PTHs 325 are electrically connected to the substrate 310 via a plurality of second bonding wires 352 so as to perform electrical interconnections between the small size chips 330 and the substrate 310. Moreover, at least partial signals from the small size chips 330 can be directly transmitted to the inner integrated circuit of the carrying chip 320 via the PTHs 352 to obtain a still faster transmission.
In this embodiment, the SIP package 300 further comprises a plurality of solder balls 360 disposed on the lower surface 312 of the substrate 310 to act as external connections. In addition, the SIP package 300 may further comprises one or more passive components 370 that is disposed at the periphery of the upper surface 311 of the substrate 310 and encapsulated by the encapsulant 340.
Referring to FIG. 5, the SIP package 300 preferably further comprises a plurality of fourth bonding wires 354 disposed on the back side 322 of the carrying chip 320 to jumper connect the back side pattern 324 across one or more traces of the back side pattern 324 without using multi-layer back side trace. That is to say, the back side pattern 324 may be single layer structure on the back side 322.
While the present invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that various changed in form and details may be made without departing from the spirit and scope of the present invention.
Patent Application
20080088005
