1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for connecting a semiconductor chip to a circuit board.
2. Description of the Related Art
Conventional semiconductor chips are often mounted on and electrically connected to a printed circuit board of one sort or another. Examples include package substrates or chip carriers, motherboards, application specific cards and others. Surface mounting is one type of mounting/interconnect technique and there are several variants of this basic technique. One very widely-used technique is flip-chip controlled collapse chip connection (C4) in which electrical connections between the chip and the package substrate, board etc. are established by creating an array of C4 solder joints. In one type of conventional lead-based process, an array of high lead content tin-lead (97Pb 3Sn) solder bumps are formed on conducting I/O bump pads of the chip. A corresponding array of eutectic tin-lead (63Sn 37Pb) solder structures are formed on conducting I/O pads of the package substrate. The chip is placed bump side down on the package substrate so that the two arrays of solder structures line up and reflow is performed above the melting point of the eutectic package bumps, but below the melting point of the chip bumps. The eutectic bumps melt and wet to the chip bumps. A subsequent cool down yields the finished solder joints.
In a typical conventional semiconductor chip package, the solder joints connect materials of highly disparate thermal expansion properties. For example, a silicon chip typically has a coefficient of thermal expansion of about 3.0 10−6 K−1, while a typical organic package substrate has a CTE of about 15.0 to 20.0 10−6 K−1. The solder joints themselves will typically have CTE's that are different still. Consequently, fatigue stresses due to thermal expansion mismatch is of great concern.
To help alleviate some of the CTE mismatch issues, an underfill material is often placed in the interstitial space between the chip and the board/substrate to which it is attached. A typical underfill is composed of an epoxy that, upon hardening, has a CTE that is as low as possible and preferably very close to the CTE of the solder joints. In many conventional processes, the underfill is dispensed at the edges of the chip and capillary action relied upon to fill the chip-to-substrate interstitial space. Any voids remaining in the underfill after solidification can adversely impact product reliability. Consequently, an extensive pre-bake is performed in the chip-substrate combination following the C4 reflow but before underfill application. A typical pre-bake may involve two or more hours of heating at temperatures of 170° C. or so. The goal is to liberate any water or other contaminants that might create voids, or inhibit underfill adhesion or capillary flow. The pre-bake, though necessary, introduces another issue: grain coarsening.
Conventional flip-chip solder joints are generally non-homogeneous structures. From the bottom up, a typical solder joint consists of (1) the base metal of the package substrate bump pad, (2) one or more solid solutions of a solder constituent—typically tin—with the package substrate bump pad base metal, (3) the solder grain structure, consisting of at least two phases containing different proportions of the solder constituents as well as any deliberate or inadvertent contaminations, (4) one or more solid solutions of a solder constituent—typically tin—with the chip bump pad base metal, and (5) the base metal of the chip bump pad. The grain structure of solder is inherently unstable, particularly for the portion of the joint associated with the eutectic solder composition. The tin grains will grow in size over time as the grain structure reduces the internal energy of a fine-grained structure. This grain growth process is enhanced by elevated temperatures, such as those associated with the underfill pre-bake, as well as strain energy input during cyclic loading. Larger grains translate into reduced fatigue life for the joints.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints whereby an interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit board are heated at a first temperature lower than a melting point of constituents of the plural solder joints to liberate contaminants from the interstitial space. The semiconductor chip and the circuit board are heated again at a second temperature higher than a melting point of at least one the constituents but not all of the constituents of the plural solder joints to shrink grain sizes of the at least one constituent. An underfill is placed in the interstitial space.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes coupling a first plurality of tin-lead solder bumps to a side of a semiconductor chip and coupling a second plurality of tin-lead solder bumps to a side of semiconductor chip package substrate. The first and second pluralities of tin-lead solder bumps are brought into proximity and a reflow is performed to melt and wet the second plurality of tin-lead solder bumps to the first plurality of tin-lead solder bumps whereby an interstitial space is left between the semiconductor chip and the semiconductor chip package substrate. The semiconductor chip and the semiconductor chip package substrate are heated at a first temperature lower than a melting point of the first and second pluralities of tin-lead solder bumps to liberate contaminants from the interstitial space. The semiconductor chip and the semiconductor chip package substrate are heated again at a second temperature higher than a melting point of the second plurality of tin-lead solder bumps but not the first plurality of tin-lead solder bumps to shrink grain sizes of tin in the second plurality of tin-lead solder bumps. An underfill is placed in the interstitial space.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints. Each of the plural solder joints has a conductive pillar coupled to the semiconductor chip and a solder structure coupled to the circuit board. The conductive pillar and the solder structure are metallurgically bonded. An interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit board are heated at a first temperature lower than a melting point of constituents of the solder structures solder joints to liberate contaminants from the interstitial space. The semiconductor chip and the circuit board are heated again at a second temperature higher than a melting point of plural solder structures joints to shrink grain sizes of the at least one constituent of the plural solder structures. An underfill is placed in the interstitial space.
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to
The chip 15 may be configured as virtually any type of device, such as a microprocessor, a graphics processor, a combined microprocessor/graphics processor, a memory device, an application specific integrated circuit or the like. Such devices may be multiple core and multiple dice. The chip 15 is depicted as being mounted in a flip-chip fashion, however, multiple dice could be stacked or mounted to the substrate 20 in a stack or unstacked configuration as desired.
The substrate 20 may interconnect electrically with some other device 44, such as a circuit board, a computing device or other electronic device, by way of variety of interconnect schemes. In this illustrative embodiment, plural interconnect structures in the form of a ball grid array consisting of a plurality of solder balls 43 are coupled to the substrate 20 in order to interface the package 10 with the other device 44. However, other interconnect schemes, such as a pin grid array, a land grid array or others may be used. Structurally speaking, the substrate 20 may be composed of ceramics or organic materials. If an organic design is selected, the substrate 20 may consist of a core/build-up configuration. In this regard, the substrate 20 may consist of a central core upon which one or more build-up layers are formed and below which an additional one or more build-up layers are formed. The core itself may consist of a stack of one or more layers. One example of such an arrangement may be termed a so called “2-4-2” arrangement where a four-layer core laminated between two sets of two build-up layers. The number of layers in the substrate 20 can vary from four to sixteen or more, although less than four may be used. So-called “coreless” designs may be used as well. The layers of the substrate 20 consist of an insulating material, such as various well-known epoxies, interspersed with metal interconnects.
Additional details of the solder joint 25 may be understood by referring now to
As described in conjunction with subsequent figures, the solder joint 25 is not a homogeneous structure. Rather, the solder joint 25 is a combination of two solder structures, one that is previously attached to the chip 15 and the other which is previously attached to the substrate 20. The two structures are brought together and a reflow is performed. The solder joint 25 consists of a large region of relatively small grain lead 65 that is depicted with a weave pattern in the figure, and a smaller and irregularly shaped region of majority tin 70 that is cross-hatched. There are smaller grains of lead also depicted with a weave pattern. A couple of the lead grains are numbered 75 and 77. The lead grains 75 and 77 and others are interspersed within the tin grains 70. Conversely, a few tin grains 80, 85 and 90, that are too small in the
Process steps that lead to the formation of the solder joint 25 are described in conjunction with
The reflow to establish the metallurgical bonding between the bumps 95 and 100 is typically performed by heating the package 10, for example in a furnace, using a thermal cycle that produces the following temperatures in the joint 25: the temperature is ramped up to 140 to 150° C. in about 4 to 5 minutes, then held at that temperature for a minute or two, then ramped up to a peak of about 220 to 240° C. for about 1 to 2 minutes, and then ramped down to room temperature in about 5 to 6 minutes. These times and temperatures may be varied. The reflow is of sufficient duration to activate flux present on the interfacing surfaces of the bumps 95 and 100 that must be activated and out gassed sufficiently in order for the metallurgical bond between the bumps 95 and 100 to fully form.
After the reflow to establish the solder joint 25, a prebake process is performed on the package 10 as a precursor to application of the underfill material layer 40 depicted in
Following the underfill prebake, the solder joint 25 is subjected to a second brief reflow process. Attention is turned now to
The exemplary method just described may be briefly summarized in conjunction with the flow chart depicted in
It may be useful at this point to consider a conventional die bump attach and underfill process. Attention is turned to
An alternate exemplary embodiment of a semiconductor chip package 10 that uses conductive pillars in conjunction with solder structures to establish an electrical interconnects between a semiconductor chip 15′ and a package substrate 20′ may be understood by referring now to
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.