This is a continuation-in-part of application “Discrete Three-Dimensional One-Time-Programmable Memory”, application Ser. No. 15/062,118, filed Mar. 6, 2016.
1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional one-time-programmable memory (3D-OTP).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory cells. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). Depending on the number of times it can be electrically programmed, 3D-EPROM can be further categorized into three-dimensional one-time-programmable memory (3D-OTP) and three-dimensional multiple-time-programmable memory (3D-MTP). 3D-M may be a 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memory), 3D-PCM (phase-change memory), 3D-PMC (programmable metallization-cell memory), or 3D-CBRAM (conductive-bridging random-access memory).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-ROM, more particularly a 3D-OTP. As illustrated in
The memory levels 16A, 16B are stacked above the substrate circuit OK. They are coupled to the substrate 0 through contact vias (e.g. 1av). Each of the memory levels (e.g. 16A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 1aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest because they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally located at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In other disclosures, diode is also referred to as steering device or selection device. In one exemplary embodiment, diode is a semiconductor diode, e.g. p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g. titanium-oxide diode, nickel-oxide diode.
The memory levels 16A, 16B collectively form at least a 3D-OTP array 16, while the substrate circuit OK comprises the peripheral circuit for the 3D-OTP array 16. A first portion of the peripheral circuit is located underneath the 3D-OTP array 16 and it is referred to as under-array peripheral circuit. A second portion of the peripheral circuit is located outside the 3D-OTP array 16 and it is referred to as outside-array peripheral circuits 18. Because the outside-array peripheral circuit 18 generally comprises fewer back-end-of-line (BEOL) levels than the 3D-OTP array 16, the space 17 above the outside-array peripheral circuits 18 is empty and completely wasted. Hereinafter, a BEOL level refers to a level of conductive lines above the substrate, e.g. an address-line level in the memory levels 16A, 16B; or, an interconnect level in the interconnects 0i. In
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-OTP die, whose 3D-OTP arrays and peripheral circuit are integrated into a single die. Generally, this design methodology is known as full integration. As is illustrated in
The peripheral-circuit region 28 comprises all necessary peripheral-circuit components for a standalone integrated 3D-OTP die 20 to perform basic memory functions, i.e. it can directly use the voltage supply 23 provided by a user (e.g. a host device or a controller), directly read and/or write data 27 for the user. It includes a read/write-voltage generator (VR/VW-generator) 21 and an address/data (A/D)-translator 29. The VR/VW-generator 21 provides read voltage VR and/or write (programming) voltage VW to the 3D-OTP array(s). The A/D-translator 29 converts address and/or data from a logical space to a physical space and/or vice versa. Hereinafter, the logical space is the space viewed from the perspective of a user of the 3D-OTP, while the physical space is the space viewed from the perspective of the 3D-OTP.
It is a prevailing belief in the field of integrated circuit that more integration is better, because integration lowers cost, improves performance and reduces size. However, this belief is no longer true for 3D-OTP. As the 3D-OTP 20 is optimized for the 3D-OTP array 16, the cost, performance and size of the peripheral circuit 18 are sacrificed. First of all, because the 3D-OTP array 16 comprises significantly more BEOL levels than the peripheral circuit 18, full integration would force a relatively simple peripheral circuit 18 to use the expensive BEOL manufacturing process of the 3D-OTP array 16. This increases the overall 3D-OTP cost. Secondly, because it comprises only a small number of interconnect levels (two in
It is a principle object of the present invention to provide a three-dimensional one-time-programmable memory (3D-OTP) with a lower overall cost.
It is a further object of the present invention to provide a 3D-OTP with an improved overall performance.
It is a further object of the present invention to provide a 3D-OTP with a smaller overall size.
In accordance with these and other objects of the present invention, a discrete 3D-OTP is disclosed.
To lower its overall cost, improve its overall performance and reduce its overall size, the present invention follows this design guideline for the 3D-OTP: separate the 3-D circuit and 2-D circuit into different dice in such a way that they could be optimized separately. For example, the 3D-OTP array (3-D circuit) and at least a peripheral-circuit component thereof (2-D circuit) are separated into different dice. Accordingly, the present invention discloses a discrete 3D-OTP. It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die is formed in a 3-D space and comprises a plurality of functional levels. It comprises at least a 3D-OTP array and at least a first peripheral-circuit component thereof, which is referred to as the in-die peripheral-circuit component. The peripheral-circuit die is formed on a 2-D plane and comprises just a single functional level. It comprises at least a second peripheral-circuit component of the 3D-OTP array, which is referred to as the off-die peripheral-circuit component. This off-die peripheral-circuit component is an essential circuit for the 3D-OTP to perform basic memory functions, e.g. directly using the voltage supply provided by a user, directly reading data from the user and/or directly writing data to the user. It could be a read/write-voltage generator (VR/VW-generator), an address/data translator (A/D-translator), a portion of the VR/VW-generator, and/or a portion of the A/D-translator. Without this off-die peripheral-circuit component, the 3D-array die per se is not a functional memory.
Designed and manufactured separately, the 3D-array die and the peripheral-circuit die in a discrete 3D-OTP comprise substantially different back-end-of-line (BEOL) structures. Since the 3D-array die and the integrated 3D-OTP die have similar structures, the peripheral-circuit die (of the discrete 3D-OTP) and the integrated 3D-OTP die have substantially different BEOL structures, too. The BEOL structures of the peripheral-circuit die could be independently optimized in such a way that the off-die peripheral-circuit components have lower cost, better performance and/or smaller size than their counterparts in the integrated 3D-OTP. Hence, the discrete 3D-OTP has a lower overall cost, a better overall performance and/or a smaller overall size of than the integrated 3D-OTP of the same storage capacity.
In terms of different BEOL structures, the peripheral-circuit die could differ from the 3D-array die in at least three scenarios. In a first scenario, the peripheral-circuit die comprises substantially fewer BEOL levels than the 3D-array die (or, the integrated 3D-OTP die). Because the wafer cost is roughly proportional to the number of BEOL levels, the peripheral-circuit die would have a much lower wafer cost than the 3D-array die and the integrated 3D-OTP die. Hence, the total die cost of the discrete 3D-OTP (including at least two dice: a 3D-array die and a peripheral-circuit die) is lower than that of the integrated 3D-OTP (which is a single die comprising both the 3D-OTP arrays and the peripheral circuit). In one preferred embodiment, the number of BEOL levels in the 3D-array die is preferably at least twice as much as the number of interconnect levels in the peripheral-circuit die. In another preferred embodiment, the number of address-line levels in the 3D-array die is substantially larger than the number of interconnect levels in the peripheral-circuit die. These large differences ensure that the reduction in the total die cost (from the integrated 3D-OTP to the discrete 3D-OTP) could offset the extra bonding cost (for two separate dice in the discrete 3D-OTP). As a result, the discrete 3D-OTP has a lower overall cost than the integrated 3D-OTP for a given storage capacity.
In a second scenario, the peripheral-circuit die comprises more interconnect levels than the 3D-array die (or, the integrated 3D-OTP die). Accordingly, the off-die peripheral-circuit components of the discrete 3D-OTP are easier to design, have better performance and occupy less die area than their counterparts in the integrated 3D-OTP. Hence, the discrete 3D-OTP has a better overall performance and a smaller overall size than the integrated 3D-OTP. Similar to the integrated 3D-OTP, the interconnects of the 3D-array die do not include any memory structures. The number of interconnect levels in the 3D-array die is the larger of its under-array peripheral-circuit components and its outside-array peripheral-circuit components. It should be reminded that, although a large number is desired, the number of the interconnect levels in the peripheral-circuit die is still bounded by the overall cost of the discrete 3D-OTP. To ensure that the discrete 3D-OTP has a lower overall cost than the integrated 3D-OTP, the peripheral-circuit die should comprise substantially fewer BEOL levels than the 3D-array die (referring to the first scenario). For example, the number of interconnect levels in the peripheral-circuit die is substantially less than the number of address-line levels in the 3D-array die.
In a third scenario, the peripheral-circuit die comprises different interconnect materials than the 3D-array die (or, the integrated 3D-OTP die). To be more specific, the peripheral-circuit die comprise high-speed interconnect materials (e.g. copper and/or high-k dielectric), whereas the 3D-array die and the integrated 3D-OTP die comprise high-temperature interconnect materials (e.g. tungsten and/or silicon oxide). Because the high-speed interconnect materials are generally faster than the high-temperature interconnect materials, the off-die peripheral-circuit components of the discrete 3D-OTP have a faster speed than their counterparts in the integrated 3D-OTP. Hence, the discrete 3D-OTP has a better overall performance than the integrated 3D-OTP.
Accordingly, the present invention discloses a discrete 3D-OTP, comprising: a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-OTP array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of BEOL levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and, said 3D-array die and said peripheral-circuit die are separate dice.
The present invention further discloses another discrete 3D-OTP, comprising: a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-OTP array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of BEOL levels in said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.
The present invention further discloses yet another discrete 3D-OTP, comprising: a 3D-array die comprising at least a 3D-OTP array and an in-die peripheral-circuit component of said 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-OTP array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein said off-die peripheral-circuit component and said in-die peripheral-circuit component comprise different interconnect materials; and, said 3D-array die and said peripheral-circuit die are separate dice.
It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments.
Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.
In the present invention, the symbol “/” means a relationship of “and” or “or”. For example, the read/write-voltage generator (VR/VW-generator) could generate either only the read voltage, or only the write voltage, or both the read voltage and the write voltage. In another example, the address/data (A/D)-translator could translate either only address, or only data, or both address and data.
Referring now to
Referring now to
The discrete 3D-OTP 50 comprises at least a 3D-array die 30 and at least a peripheral-circuit die 40/40*. In these figures, at least an off-die peripheral-circuit component of the 3D-OTP is located on the peripheral-circuit die 40/40* instead of the 3D-array die 30. This off-die peripheral circuit is an essential circuit for the 3D-OTP to perform basic memory functions, e.g. directly using the voltage supply provided by a user, directly reading data from the user and/or directly writing data to the user. It could be a read/write-voltage generator (VR/VW-generator), an address/data translator (A/D-translator), a portion of the VR/VW-generator, and/or a portion of the A/D-translator. Without this off-die peripheral circuit, the 3D-array die 30 per se is not a functional memory.
The preferred discrete 3D-OTP 50 in
The preferred discrete 3D-OTP 50 in
The preferred discrete 3D-OTP 50 in
The preferred discrete 3D-OTP 50 in
Referring now to
The in-die peripheral circuit 38 comprises transistors 0t and interconnects 0i. As the interconnects of the 3D-array die 30 include the BEOL structures above the substrate 0 except all memory structures, the interconnects 0i in the in-die peripheral circuit 38 of
Because the 3D-OTP array 36 is formed above the in-die peripheral-circuit component 38, the total number of BEOL levels in the 3D-array die 30 would be equal to the sum of the number of its address-line levels and the number of its interconnect levels. In this case, the total number of BEOL levels in the 3D-array die 30 is ten, including eight address-line levels 1a-8a and two interconnect levels 0M1-0M2.
Referring now to
The interleaved 3D-OTP uses fewer address-line levels to achieve the same memory levels and therefore, has a lower manufacturing cost. Besides being fully interleaved, the interleaved 3D-OTP could be partially interleaved, i.e. some adjacent memory levels are separated while other adjacent memory levels are interleaved. More details on the interleaved 3D-OTP can be found in U.S. patent application “Hybrid-Level Three-Dimensional Memory”, application Ser. No. 11/736,767, filed Apr. 18, 2007.
Although the cross-sectional views of
Referring now to
In the preferred embodiments of
Furthermore, because the peripheral-circuit die 40 (
In addition, because its BEOL process does not have to go through any high-temperature BEOL processing steps, the peripheral-circuit die 40 may use high-speed interconnect materials for its interconnects 0i′ (e.g. copper and/or low-k dielectric). These high-speed interconnect materials can improve the performance of the peripheral-circuit die 40, as well as the overall 3D-OTP performance.
For a conventional two-dimensional memory (2D-M, whose memory cells are arranged on a 2-D plane, e.g. flash memory), although it is technically possible to form at least a peripheral-circuit component in a peripheral-circuit die instead of a 2D-array die, doing so will raise the overall cost, degrade the overall performance and increase the overall size. This is because the 2D-array die and the peripheral-circuit die have similar BEOL structures, similar wafer costs and similar performance. Adding the extra bonding cost and delay, a discrete 2D-M has a higher cost, a slower speed and a larger size than an integrated 2D-M. This is in sharp contrast to the 3D-OTP. The 3D-array die 30 and peripheral-circuit die 40 of a discrete 3D-OTP 50 have substantially different BEOL structures (e.g. different number of BEOL levels, different number of interconnect levels, different interconnect materials). As a result, a discrete 3D-OTP has a lower overall cost, a better overall performance and a smaller overall size than an integrated 3D-OTP.
Different from the integrated 3D-OTP 20, at least a peripheral-circuit component of the discrete 3D-OTP 50 is located on the peripheral-circuit die 40 instead of the 3D-array die 30. In other words, the peripheral-circuit components of 3D-OTP are partitioned between the 3D-array die 30 and the peripheral-circuit die 40. Several preferred partitioning schemes are disclosed in
Referring now to
Referring now to
The preferred discrete 3D-OTP package 60 of
The preferred discrete 3D-OTP package 60 of
The preferred discrete 3D-OTP module 60 of
Referring now to
In
In
In
Referring now to
While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.
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2016 1 0640347 | Aug 2016 | CN | national |
Number | Name | Date | Kind |
---|---|---|---|
4404655 | Naiff | Sep 1983 | A |
4424579 | Roesner | Jan 1984 | A |
4598386 | Roesner et al. | Jul 1986 | A |
4603341 | Bertin et al. | Jul 1986 | A |
4646266 | Ovshinsky et al. | Feb 1987 | A |
4796074 | Roesner | Jan 1989 | A |
4939568 | Kato et al. | Jul 1990 | A |
5257224 | Nojiri et al. | Oct 1993 | A |
5272370 | French | Dec 1993 | A |
5375085 | Gnade et al. | Dec 1994 | A |
5455435 | Fu et al. | Oct 1995 | A |
5468983 | Hirase et al. | Nov 1995 | A |
5721169 | Lee | Feb 1998 | A |
5751012 | Wolstenholme et al. | May 1998 | A |
5825686 | Schmitt-Landsiedel et al. | Oct 1998 | A |
5835396 | Zhang | Nov 1998 | A |
5838530 | Zhang | Nov 1998 | A |
5841150 | Gonzalez et al. | Nov 1998 | A |
5843824 | Chou et al. | Dec 1998 | A |
5847442 | Mills, Jr. et al. | Dec 1998 | A |
5854111 | Wen | Dec 1998 | A |
5904526 | Wen et al. | May 1999 | A |
5907778 | Chou et al. | May 1999 | A |
5943255 | Kutter et al. | Aug 1999 | A |
6015738 | Levy et al. | Jan 2000 | A |
6021079 | Worley | Feb 2000 | A |
6034882 | Johnson et al. | Mar 2000 | A |
6049481 | Yamasaki | Apr 2000 | A |
6055180 | Gudesen et al. | Apr 2000 | A |
6185122 | Johnson et al. | Feb 2001 | B1 |
6221723 | Kunitou | Apr 2001 | B1 |
6236587 | Gudesen et al. | May 2001 | B1 |
6380597 | Gudesen et al. | Apr 2002 | B1 |
6624485 | Johnson | Sep 2003 | B2 |
6717222 | Zhang | Apr 2004 | B2 |
6903427 | Zhang | Jun 2005 | B2 |
7386652 | Zhang | Jun 2008 | B2 |
7423304 | Cleeves et al. | Sep 2008 | B2 |
7449376 | Isobe et al. | Nov 2008 | B2 |
7728391 | Zhang | Jun 2010 | B2 |
8325527 | Jin et al. | Dec 2012 | B2 |
8345479 | Maejima | Jan 2013 | B2 |
8519472 | Jeong et al. | Aug 2013 | B2 |
8638611 | Sim et al. | Jan 2014 | B2 |
9024425 | Zhang | May 2015 | B2 |
9093129 | Zhang | Jul 2015 | B2 |
9117493 | Zhang | Aug 2015 | B2 |
9305604 | Zhang | Apr 2016 | B2 |
9396764 | Zhang | Jul 2016 | B2 |
20070252153 | Koyama | Nov 2007 | A1 |
20080130342 | Zhang | Jun 2008 | A1 |
20080159722 | Zhang | Jul 2008 | A1 |
20090073795 | Pyeon | Mar 2009 | A1 |
20100208503 | Kuo | Aug 2010 | A1 |
20110298037 | Choe et al. | Dec 2011 | A1 |
20120155168 | Kim et al. | Jun 2012 | A1 |
20120218817 | Kang et al. | Aug 2012 | A1 |
20130003480 | D'Abreu et al. | Jan 2013 | A1 |
20130126957 | Higashitani et al. | May 2013 | A1 |
20130151760 | Cho et al. | Jun 2013 | A1 |
20130188415 | Zhang | Jul 2013 | A1 |
20130258740 | Zhang | Oct 2013 | A1 |
20140036566 | Zhang | Feb 2014 | A1 |
20140063938 | Oh et al. | Mar 2014 | A1 |
20160085444 | Tanzawa | Mar 2016 | A1 |
Number | Date | Country | |
---|---|---|---|
20170047127 A1 | Feb 2017 | US |
Number | Date | Country | |
---|---|---|---|
61529929 | Sep 2011 | US |
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