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Methods or arrangements for processing data by operating upon the order or content of the data handled
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CPC
G06F7/00
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Parent Industries
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PHYSICS
G06
Computing
G06F
ELECTRICAL DIGITAL DATA PROCESSING
Current Industry
G06F7/00
Methods or arrangements for processing data by operating upon the order or content of the data handled
Sub Industries
G06F7/02
Comparing digital values
G06F7/023
adaptive
G06F7/026
Magnitude comparison, i.e. determining the relative order of operands based on their numerical value
G06F7/06
Arrangements for sorting, selecting, merging or comparing data on individual record carriers
G06F7/08
Sorting
G06F7/10
Selecting
G06F7/12
with provision for printing-out a list of selected items
G06F7/14
Merging
G06F7/16
Combined merging and sorting
G06F7/20
Comparing separate sets of record carriers arranged in the same sequence to determine whether at least some of the data in one set is identical with that in the other set or sets
G06F7/22
Arrangements for sorting or merging computer data on continuous record carriers
G06F7/24
Sorting
G06F7/26
the sorted data being recorded on the original record carrier within the same space in which the data had been recorded prior to their sorting, without using intermediate storage
G06F7/32
Merging
G06F7/36
Combined merging and sorting
G06F7/38
Methods or arrangements for performing computations using exclusively denominational number representation
G06F7/381
using cryogenic components
G06F7/383
using magnetic or similar elements
G06F7/385
magnetic bubbles
G06F7/386
decimal, radix 20 or 12
G06F7/388
using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant
G06F7/40
using contact- making devices
G06F7/405
binary
G06F7/42
Adding Subtracting
G06F7/44
Multiplying Dividing
G06F7/443
by successive additions or subtractions
G06F7/446
by partial product forming (with electric multiplication table)
G06F7/46
using electromechanical counter-type accumulators
G06F7/461
Adding; subtracting
G06F7/462
Multiplying; dividing
G06F7/463
by successive additions or subtractions
G06F7/465
by partial product forming (with electric multiplication table)
G06F7/466
by successive multiplication or division by 2
G06F7/467
by using preset multiples of the multiplicand or the divisor
G06F7/468
for evaluating functions by calculation
G06F7/48
using non-contact-making devices
G06F7/4806
Computations with complex numbers
G06F7/4812
Complex multiplication
G06F7/4818
using coordinate rotation digital computer [CORDIC]
G06F7/4824
using signed-digit representation
G06F7/483
Computations with numbers represented by a non-linear combination of denominational numbers
G06F7/4833
Logarithmic number system
G06F7/4836
Computations with rational numbers
G06F7/485
Adding Subtracting
G06F7/487
Multiplying Dividing
G06F7/4873
Dividing
G06F7/4876
Multiplying
G06F7/49
Computations with a radix, other than binary, 8, 16 or decimal
G06F7/491
Computations with decimal numbers radix 12 or 20.
G06F7/4912
Adding; Subtracting
G06F7/4915
Multiplying; Dividing
G06F7/4917
Dividing
G06F7/492
using a binary weighted representation within each denomination
G06F7/4925
Adding; Subtracting
G06F7/493
the representation being the natural binary coded representation
G06F7/494
Adding Subtracting
G06F7/495
in digit-serial fashion
G06F7/496
Multiplying Dividing
G06F7/498
using counter-type accumulators
G06F7/4981
Adding; Subtracting
G06F7/4983
Multiplying; Dividing
G06F7/4985
by successive additions or subtractions
G06F7/4986
by successive multiplication or division by 2
G06F7/4988
by table look-up
G06F7/499
Denomination or exception handling
G06F7/49905
Exception handling
G06F7/4991
Overflow or underflow
G06F7/49915
Mantissa overflow or underflow in handling floating-point numbers
G06F7/49921
Saturation
G06F7/49926
Division by zero
G06F7/49931
Modulo N reduction of final result
G06F7/49936
Normalisation mentioned as feature only
G06F7/49942
Significance control
G06F7/49947
Rounding
G06F7/49952
Sticky bit
G06F7/49957
Implementation of IEEE-754 Standard
G06F7/49963
Rounding to nearest
G06F7/49968
Rounding towards positive infinity
G06F7/49973
Rounding towards negative infinity
G06F7/49978
Rounding towards zero
G06F7/49984
Rounding away from zero
G06F7/49989
Interval arithmetic
G06F7/49994
Sign extension
G06F7/50
Adding Subtracting
G06F7/501
Half or full adders
G06F7/5013
using algebraic addition of the input signals
G06F7/5016
forming at least one of the output signals directly from the minterms of the input signals
G06F7/502
Half adders Full adders consisting of two cascaded half adders
G06F7/503
using carry switching
G06F7/504
in bit-serial fashion
G06F7/5045
for multiple operands
G06F7/505
in bit-parallel fashion
G06F7/5052
using carry completion detection, either over all stages or at sample stages only
G06F7/5055
in which one operand is a constant
G06F7/5057
using table look-up using programmable logic arrays
G06F7/506
with simultaneous carry generation for, or propagation over, two or more stages
G06F7/507
using selection between two conditionally calculated carry or sum values
G06F7/508
using carry look-ahead circuits
G06F7/509
for multiple operands
G06F7/5095
word-serial
G06F7/52
Multiplying Dividing
G06F7/523
Multiplying only
G06F7/5235
using indirect methods
G06F7/525
in serial-serial fashion
G06F7/527
in serial-parallel fashion
G06F7/5272
with row wise addition of partial products
G06F7/5275
using carry save adders
G06F7/5277
with column wise addition of partial products
G06F7/53
in parallel-parallel fashion
G06F7/5306
with row wise addition of partial products
G06F7/5312
using carry save adders
G06F7/5318
with column wise addition of partial products
G06F7/5324
partitioned
G06F7/533
Reduction of the number of iteration steps or stages
G06F7/5332
by skipping over strings of zeroes or ones
G06F7/5334
by using multiple bit scanning
G06F7/5336
overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation
G06F7/5338
each bitgroup having two new bits
G06F7/535
Dividing only
G06F7/537
Reduction of the number of iteration steps or stages
G06F7/5375
Non restoring calculation, where each digit is either negative, zero or positive
G06F7/544
for evaluating functions by calculation
G06F7/5443
Sum of products
G06F7/5446
using crossaddition algorithms
G06F7/548
Trigonometric functions Co-ordinate transformations
G06F7/552
Powers or roots
G06F7/5525
Roots or inverse roots of single operands
G06F7/556
Logarithmic or exponential functions
G06F7/57
Arithmetic logic units [ALU]
G06F7/575
Basic arithmetic logic units
G06F7/58
Random or pseudo-random number generators
G06F7/582
Pseudo-random number generators
G06F7/584
using finite field arithmetic
G06F7/586
using an integer algorithm
G06F7/588
Random number generators
G06F7/60
Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix Computing devices using combinations of denominational and non-denominational quantity representations
G06F7/602
using delta-sigma sequences
G06F7/605
Additive or subtractive mixing of two pulse rates into one
G06F7/607
number-of-ones counters
G06F7/62
Performing operations exclusively by counting total number of pulses; Multiplication, division or derived operations using combined denominational and incremental processing by counters
G06F7/64
Digital differential analysers
G06F7/66
wherein pulses represent unitary increments only
G06F7/68
using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
G06F7/70
using stochastic pulse trains
G06F7/72
using residue arithmetic
G06F7/721
Modular inversion, reciprocal or quotient calculation
G06F7/722
Modular multiplication
G06F7/723
Modular exponentiation
G06F7/724
Finite field arithmetic
G06F7/725
over elliptic curves
G06F7/726
Inversion; Reciprocal calculation; Division of elements of a finite field
G06F7/727
Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1
G06F7/728
using Montgomery reduction
G06F7/729
using representation by a residue number system
G06F7/74
Selecting or encoding within a word the position of one or more bits having a specified value
G06F7/76
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
G06F7/762
having at least two separately controlled rearrangement levels
G06F7/764
Masking
G06F7/766
Generation of all possible permutations
G06F7/768
Data position reversal
G06F7/78
for changing the order of data flow
G06F7/785
having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Issue date
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Systems and methods for secure random number generation
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Surface code computations using Auto-CCZ quantum states
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Issue date
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Rapid sorting-based supply assignment tool for order fulfillment wi...
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Apparatus and method for fully parallelized simulated annealing usi...
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Apparatus and method for complex multiplication
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Time domain multiply and accumulate system
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Issue date
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Issue date
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Method, apparatus, and computer program stored in computer readable...
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Issue date
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Issue date
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Issue date
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Publication date
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
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G06 - COMPUTING CALCULATING COUNTING
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication number
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication number
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication number
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
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Publication number
20240137345
Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
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Publication number
20240134931
Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
ANALOG MAC AWARE DNN IMPROVEMENT
Publication number
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Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
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Publication number
20240134604
Publication date
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Theo Drane
G06 - COMPUTING CALCULATING COUNTING
Information
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Publication number
20240134608
Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
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Publication number
20240134609
Publication date
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G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
METHOD AND SYSTEM FOR DATA COMMUNICATION WITH DIFFERENTIALLY PRIVAT...
Publication number
20240135024
Publication date
Apr 25, 2024
ALIPAY (HANGZHOU) INFORMATION TECHNOLOGY CO., LTD.
Jian DU
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
REINFORCEMENT LEARNING WITH MULTIPLE OBJECTIVES AND TRADEOFFS
Publication number
20240135234
Publication date
Apr 25, 2024
International Business Machines Corporation
Radu Marinescu
G06 - COMPUTING CALCULATING COUNTING