Patent Grant
10580723
Disclosed embodiments relate to flat no-lead semiconductor packages and assembly processes for such packages.
A variety of semiconductor chip packages are known that provide support for an integrated circuit chip (IC) or die and associated bond wires, provide protection from the environment, and enable surface mounting of the die to and Interconnection with a printed circuit board (PCB). One conventional package configuration is a flat no-leads package such as quad-flat no-lead (QFN) or and dual-flat no-lead (DFN). Flat no-lead packages, also known as micro leadframe (MLF) and SON (small-outline no leads), is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Perimeter lands or terminals exposed on the package bottom provide electrical connections to the PCB. Flat no-lead packages also include an exposed thermal die pad to improve heat transfer out of the IC (into the PCB).
QFNs and DFNs are relatively difficult to solder to because all the terminal connections are on the bottom of the package. Some designs have small extensions for these terminals that wrap around the bottom corner of the package and come up along the edge of the package somewhat. As QFN and DFN packages conventionally comprise copper leadframes, to allow soldering thereto they have added terminal finishes, such as comprising Matt Sn (100% tin) which is applied to the terminals using an electroless (or auto-catalytic by only chemical means) plating process. The QFN/DFN tin coated terminals can then be soldered to a PCB.
Inspection of QFN and DFN packages soldered onto a PCB is typically done with X-ray equipment for an assembly process monitor. The X-ray can detect solder bridging, shorts, opens, voids and solder joint fillets under the leads and exposed pads which are determined as the critical area of termination. For example, the J-STD-002C solderablity standard includes a proposed (In ballot) soldering criteria for the QFN/DFN. Some customers (e.g., automotive customers) for QFN packaged semiconductor devices besides requiring a terminal underside solder inspection also require a side solder inspection.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed embodiments recognize the use of electroless 100% Sn (tin) for terminal finishes for flat no-lead packages (QFN or DFN) is susceptible to the phenomenon known as tin whiskering. Tin whiskers are known to be electrically conductive single crystal tin eruptions that can grow from surfaces where tin is deposited on a substrate surface, typically being 1 μm to 5 μm in diameter and between 1 μm and 500 μm in length. Such whiskers can cause shorting (e.g., whisker bridging) that reduces yield and can cause reliability problems. Disclosed embodiments recognize an electrolytic (electroplating) terminal finishing process instead of a conventional electroless plating process would remove Sn whiskering, however the need for electrical contact to all surfaces to enable electroplating to take place on all such surfaces eliminates the possibility of using conventional electroplating.
Disclosed methods overcome this barrier to electroplating a terminal finishing metal with an electroplating method by including a removably shorting together step that shorts together al surfaces to be plated which enables electroplating a metal or metal alloy finish onto the QFN/DFN terminals including their edges of a packaged semiconductor device. Disclosed methods include a first partial saw process that exposes sides of the package terminals, followed by removably shorting together (e.g., using a Jig or wire bonds) to electrically connect together all the surfaces to be electroplated, removing of the shorting together, and a second sawing step that finishes sawing through the plastic encapsulation to provide singulation to form a plurality of packaged semiconductor devices.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some Illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an Indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via Intervening items Including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.
The lead frames typically comprise copper or a copper alloy. Plastic encapsulation is Included except on a back side of the lead frame sheet to expose a back side of the die pad to provide an exposed thermal pad and to expose a back side of the terminals. The lead frames can comprise quad-flat no-lead (QFN) or dual-flat no-lead (DFN).
Step 102 comprises partial sawing in the saw lanes beginning from the back side through the terminals ending with saw lines having a line width terminating within the plastic encapsulation to provide exposed side walls of the terminals and exposed side walls of the plastic encapsulation. The partial sawing can comprise mechanical sawing or laser sawing.
Step 103 comprises shorting together (e.g., using a jig (essentially a bed of nails), jumper, or wire bonding) all the exposed thermal pad(s) and exposed back side of the terminals to form electrically Interconnected metal surfaces (Interconnected surfaces).
Step 104 comprises electroplating the interconnected surfaces with a solder wetable metal or metal alloy plating layer on the back side and on the exposed side walls of the terminals. Electroplating as known in the art is a process that uses electrical current from a power supply to reduce dissolved metal cations in a plating solution so that they form a metal coating on the desired surface to be plated that is configured as a cathode.
Although the plating layer 520 is shown as a single layer, the plating layer can comprise a stack of different plating layers, such as the stack of plating layers in one particular embodiment being NiPdAu (3 layers).
Step 105 comprises decouping the interconnected surfaces. When the shorting together comprises using bond wires, the decoupling can comprise using a metal brush for shearing off the bond wires. In the case of a jig, the jig is lifted up to remove the contacts of its nails or probes with the terminals.
Step 106 comprises a second sawing in the saw lanes to finish sawing beginning from the bottom of the saw lines through the plastic encapsulation 211 to provide singulation to form a plurality of packaged semiconductor devices.
Advantages of disclosed methods and packaged semiconductor devices therefrom include the elimination of tin whiskering. Side wetting is also provided to enable a visual solder inspection Instead of having to conventionally rely on an x-ray inspection for electrolytic processes.
Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor Integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as package on package (PoP) configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
This application is a Divisional of Ser. No. 15/438,533 filed Feb. 21, 2017, which is a Continuation of Ser. No. 15/162,807 filed May 24, 2016, that is now U.S. Pat. No. 9,576,886 (granted Feb. 21, 2017), which is a Divisional of and claims benefit to U.S. patent application Ser. No. 14/842,460, flied Sep. 1, 2015 that is now U.S. Pat. No. 9,373,569 (granted Jun. 21, 2016), the contents of all are incorporated herein by reference in their entirety.
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| Number | Date | Country | |
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| 20190295935 A1 | Sep 2019 | US |
| Number | Date | Country | |
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| Parent | 15438533 | Feb 2017 | US |
| Child | 16427172 | US | |
| Parent | 14842460 | Sep 2015 | US |
| Child | 15162807 | US |
| Number | Date | Country | |
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| Parent | 15162807 | May 2016 | US |
| Child | 15438533 | US |
