Patent Application
20130050227
This disclosure relates to structures and processes for glass packaging of electromechanical systems and integrated circuit devices.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (including mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of EMS device is called an interferometric modulator (IMOD). The term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. For example, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
Packaging protects the functional units of the system from the environment, provides mechanical support for the system components, and provides an interface for electrical interconnections.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in a package for a device. In some implementations, a package includes a glass substrate and a cover glass. The glass substrate and the cover glass can be joined to form a glass package with a cavity between the cover glass and glass substrate. A device can be disposed within the cavity. The package also can include a signal transmission pathway between the device and an exterior of the package. In some implementations, the package can have a largest dimension of less than about 10 mm, for example, about 5 mm or less.
The device can be any type of device, for example, an integrated circuit (IC) device or an electromechanical systems (EMS) device. In some implementations, two or more devices can be disposed with the cavity. In some implementations, the package can include a second cavity between the cover glass and the glass substrate. In implementations including multiple cavities, a pressure and/or gas composition can differ between the cavities.
In some implementations, the package can further include one or more joining rings between the cover glass and the glass substrate. In some implementations, a joining ring includes at least one of an epoxy, glass or metal. Example widths of a joining ring can range from about 20 and 500 microns. Example thicknesses of a joining ring can range from about 0.1 to 100 microns. A joining ring can provide a hermetic or non-hermetic seal between the cover glass and glass substrate.
A signal transmission pathway can be configured to transmit signals such as electrical, pressure, light and thermal signals according to the desired implementation. In some implementations, a signal transmission pathway includes a port in at least one of the cover glass and the glass substrate that provides fluid access to a device, such that a gas or liquid can reach the device. In some implementations, a signal transmission pathway includes through-glass via interconnects in at least one of the cover glass or the glass substrate.
In some implementations, the package also can include surface mount device (SMD) pads on an exterior surface of the package. The SMD pads can be electrically connected to a device disposed between the cover glass and the glass substrate. In some implementations, the package is configured for direct mounting on a printed circuit board (PCB).
Another innovative aspect of the subject matter described in this disclosure can be implemented in a package that includes means for encapsulating a device inside an all-glass package and means for electrically connecting the device to an exterior of the package. In some implementations, the package can further include means for transmitting a pressure, light or thermal signal between the device and an exterior of the all-glass package. The package can include means for hermetically sealing the device inside the all-glass package.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a package including an EMS device fabricated on a glass substrate, a cover glass sealed to the glass substrate and forming a lid over the EMS device, and an IC device attached to one of the glass substrate and cover glass. The IC device can be configured for electrical communication with the EMS device. The package can further include a connection through at least one of the cover glass or glass substrate configured for signal transmission with the EMS device. In some implementations, the IC device can overlie the EMS device. The IC device can be attached to the glass substrate bonds such as flip chip bonds. In some implementations, the cover glass is bonded to the glass substrate at a joining ring. The connection can include a through-glass via interconnect located outside the joining ring.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Although the examples provided in this disclosure are primarily described in terms of electromechanical systems (EMS) and microelectromechanical systems (MEMS)-based displays, the concepts provided herein may apply to other types of displays, such as liquid crystal displays, organic light-emitting diode (“OLED”) displays and field emission displays. Other features, aspects, and advantages will become apparent from the description, the figures and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device or system that can be configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (i.e., e-readers), computer monitors, auto displays (including odometer and speedometer displays, etc.), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS), microelectromechanical systems (MEMS) and non-MEMS applications), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of EMS devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
Some implementations described herein relate to packaging of electromechanical systems (EMS) and integrated circuit (IC) devices. Some implementations described herein relate to glass packages including one or more IC and EMS devices encapsulated between a cover glass and a glass substrate. In some implementations, a glass substrate is a substrate on which an MEMS or other EMS device is fabricated as well as, with the cover glass, a package for the device. In some implementations, a glass substrate is a substrate on which an IC device is attached or fabricated, as well as, with the cover glass, a package for the device. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by standard surface mount technology.
In some implementations, a glass package includes one or more pads configured to attach to a flexible connector. A flexible connector, such as a flat flexible connector, can be used to electrically connect a device within the glass package to an electrical component, such as an integrated circuit (IC) device or PCB, outside the glass package. In some implementations, the electrical component is at a location remote from the glass package.
In some implementations, a glass package includes an electrical connection from an encapsulated device to an exterior surface of the package. The electrical connection can include through-glass via interconnects through a cover glass and/or glass substrate, and conductive traces formed on one or more surfaces of a cover glass and/or glass substrate.
In some implementations, a glass package includes a non-electrical signal transmission pathway between an encapsulated device and the exterior of the package. For example, a non-electrical signal transmission pathway can include one or more of a fluid access pathway, a light transmissive pathway, and a thermally transmissive pathway. In some implementations, a glass package includes a coating, such as a polymer, non-organic dielectric, or metal coating, on one or more exterior surfaces of the glass package. A coating can be used to increase opacity, provide package markings, provide a uniform package appearance, increase package visibility, increase package durability, increase scratch resistance of the package, increase shock resistance of the package, impart hermeticity to the package, provide electrical isolation package, provide heat transfer to or from the package and provide thermal isolation of the package.
In some implementations, methods of fabricating glass packages described herein include joining a cover glass panel to a glass substrate panel. A glass substrate panel can have tens to hundreds of thousands or more EMS or IC devices fabricated thereon or attached thereto. A cover glass panel can have tens to hundreds of thousands or more recesses configured to accommodate such devices. Once joined, the cover glass and glass substrate panels can be singulated to form individual glass packages, each including one or more encapsulated devices. In some implementations, all or most of the processing to fabricate or attach devices, to form electrical connections on or through a glass package, and to form other signal transmission pathways on or through a glass package, occurs at the panel level.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. A glass package can provide low cost, small size, and low profile devices. In some implementations, batch level processing methods can be used to eliminate or reduce die-level processing. Advantages of encapsulation and packaging in a batch process at a panel or sub-panel level include a large number of units fabricated in parallel in the batch process, thus reducing costs per unit as compared to individual die-level processing. The use of batch processes such as lithography, etching and plating over a large substrate in some implementations allows tighter tolerances and reduces die-to-die variation. The formation of through-glass interconnects and other metal components of a package in a single plating process stage can reduce costs per package. In some implementations, smaller and/or more reliably packaged devices can be fabricated. Smaller devices can result in a larger number of units fabricated in parallel in the batch process. In some implementations, package-related stresses on a MEMS or other device can be reduced or eliminated. For example, in some implementations, concerns related to molding-related process stresses on a device can be eliminated by providing a glass package with surface mount pads without molding.
An example of a suitable EMS or MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity. One way of changing the optical resonant cavity is by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, such as chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be approximately 1-1000 um, while the gap 19 may be approximately less than 10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
Implementations described herein relate to glass packaging of EMS devices, including IMODs, IC devices and other devices. In some implementations, a cover glass is sealed against a glass substrate, with an EMS and/or IC device situated between the glass substrate and cover glass. The sealed glass substrate and cover glass may provide the entire packaging for the device. The packaged devices can include dies embellished with leads and/or pads for connecting the device to another package, directly to a printed wiring board or flex tape, or for stacked or multi-substrate configurations. While implementations of the packages and methods of fabrication are described chiefly in the context of glass packaging of MEMS and IC devices, the packages and methods are not so limited and may be applied in other contexts.
As used herein, a glass package is a package including a cover glass attached to a glass substrate to encapsulate a device between the cover glass and the glass substrate. In some implementations, the glass packages described herein are all-glass packages, without any non-glass substrates or lids such as plastic, ceramic or metal substrates or lids, packaging the device. In some implementations, an all-glass package can encapsulate a separately packaged device, such as a silicon chip. In some implementations, the glass packages described herein are suitable for surface mounting and/or deployment in a consumer product without any overmolding or other further packaging.
Implementations described herein relate to glass packages including a glass substrate, a cover glass, and one or more devices encapsulated between the glass substrate and the cover glass, and one or more signal transmission pathways between an encapsulated device and the package exterior.
The glass packaging described herein can be used to package a variety of device sizes. For example, a packaged device can be 5 mm or less, 10 mm or less, and sometimes even greater than 10 mm. Glass packages encapsulating pressure sensors, gyroscopes, accelerometers, for example, may have length and width dimensions each less than 10 mm, or even less than 5 mm. A glass package including a display device, for example, device may have length and width dimensions of greater than about 10 mm.
In some implementations, a length of the cover glass may be about 1 to 10 mm, or about 1 to 5 mm, and a width of the cover glass may be about 1 to 10 mm, or about 1 to 5 mm. In various implementations, the cover glass is about 50 to 700 microns thick, about 100 to 300 microns thick, about 300 to 500 microns thick, or about 500 microns thick. The cover glass may be or include, for example, a borosilicate glass, a soda lime glass, quartz, Pyrex, or other suitable glass material. The cover glass may be transparent or non-transparent. For example, the cover glass may be frosted, painted, or otherwise made opaque.
In some implementations, a length of the glass substrate may be about 1 to 10 mm, or about 1 to 5 mm, and a width of the substrate may be about 1 to 10 mm, or about 1 to 5 mm. In various implementations, the glass substrate is about 100 to 700 microns thick, about 100 to 300 microns thick, about 300 to 500 microns thick, or about 500 microns thick. The glass substrate may be or include, for example, a borosilicate glass, a soda lime glass, quartz, Pyrex, or other suitable glass material. The glass substrate may be transparent or non-transparent. For example, the glass substrate may be frosted, painted, or otherwise made opaque.
In some implementations, the length and/or the width of the cover glass may be the same or approximately the same as the length and/or the width of the glass substrate. In some other implementations, the length and/or the width of the cover glass may be different than the length and/or the width of the glass substrate. For example, one or the other of the cover glass and glass substrate has a dimension larger than the corresponding dimension of the cover glass and glass substrate such that the glass package includes a ledge.
The cover glass and glass substrate each have surfaces that lie interior to the glass package and surfaces that lie exterior to the glass package. An interior surface of a cover glass can face an interior surface of a glass substrate. One or both of a cover glass and a glass substrate can include one or more recesses in an interior surface to accommodate one or more devices, such as an EMS and/or an integrated circuit device. An interior surface of a glass substrate can be joined to an interior surface of the cover glass. The cover glass and glass substrate can be joined with an interface such as an epoxy, a glass frit, or a metal. In some implementations, a joined cover glass and glass substrate forms a glass package to encapsulate a device.
A glass package can include one or more sides. In some implementations, a glass package includes a first surface that is an exterior surface of a cover glass, a second surface that is an exterior surface of a glass substrate, and one or more sides between the first and second surfaces.
A signal transmission pathway between one or more devices encapsulated in a glass package and an exterior of the package can provide a pathway for one or more of electrical, pressure, light, fluid, and thermal signals. For example, a signal transmission pathway for pressure can include a port in one or both of a cover glass or glass substrate. In another example, a signal transmission pathway for light can include a transparent region in one or both of a cover glass or glass substrate.
An electrical connection between a device and an exterior of a glass package encapsulating the device can include any electrical component, including conductive traces (also referred to as conductive lines or leads), conductive vias and conductive pads. Conductive traces can be formed on one or more surfaces of a cover glass and/or glass substrate, including on any interior, exterior or side surface. Conductive lines and vias can be formed in one or more of a cover glass and glass substrate. In some implementations, an electrical connection includes a through-glass via interconnect that extends from an interior surface of a cover glass to an exterior surface of the cover glass. In some implementations, an electrical connection includes a through-glass via that extends from an interior surface of a glass substrate to an exterior surface of the glass substrate.
Conductive pads, also referred to as bond pads or contact pads, can be formed on one or more surfaces of a cover glass and/or glass substrate, including on any interior, exterior or side surface. In some implementations, a glass-encapsulated device includes one or more conductive pads on an exterior surface to which a connection can be wire bonding, soldering, or flip-chip attached and that can be configured for connection to external components such as printed circuit boards (PCBs), ICs, passive components and the like. In some implementations, a glass package includes one or more conductive pads configured to provide a connection point for flex tape. A glass package can include one or more electrically inactive, or dummy, bond pads on an exterior surface that are configured to bond to dummy solder balls or other electrically inactive joints.
These and other aspects of glass packages and related fabrication methods are described below with reference to
The device 100 can be any type of device, including any EMS device, such as a MEMS device, a nanoelectromechanical systems (NEMS) device, or an IC device. In some implementations, the device 100 can be a separate package, for example, a complementary metal oxide semiconductor (CMOS) device formed on a silicon substrate. In some implementations, the device 100 is formed on the interior surface 93 of the glass substrate 92. For example, the device 100 can be a MEMS device or an on-glass low-temperature-polycrystalline thin-film transistor (LTPS-TFT) fabricated on the interior surface 93 of the glass substrate 92. As described further below, in some implementations, the glass package 90 can include multiple devices 100, for example a MEMS device and an associated application specific integrated circuit (ASIC) device. In another example, the glass package 90 can include multiple EMS sensors, such as accelerometers, gyroscopes, pressure sensors, acoustic sensors and the like, and one or more ASIC devices. In some implementations, one or more devices 100 can be fabricated on or attached to the cover glass 96.
Each of the cover glass 96 and the glass substrate 92 can be or include, for example, a borosilicate glass, a soda lime glass, quartz, Pyrex, or other suitable glass material. In some implementations, the cover glass 96 is between 50 microns and 700 microns thick. The depth and area of the recess 99 is sufficient to accommodate the device 100 to be packaged. The device 100 can be of arbitrary thickness and area. For example, in some implementations, devices having thicknesses of about 1-300 microns and areas of 1 square micron to tens of square millimeters can be packaged. In some implementations, a depth of the recess 99 is between about 20 microns and 350 microns. The glass substrate 92 can be, for example, between 300 and 700 microns thick. An overall thickness of the glass package 90 can range, for example, from about 300-1,500 microns.
In some implementations, a glass package 90 is suitable for surface mounting, for example, on a PCB or other integration substrate. Due to the relative stiffness of glass, in some implementations the glass package 90 can isolate the packaged device 100 from stresses generated by the PCB better than plastic or other types of package materials. The glass package 90 also can protect the device 100 from harsh chemical environments better than plastic in some implementations. In some implementations, the glass substrate 92 or the cover glass 96 is a glass component of a display panel.
In some implementations, the glass substrate 92 includes electrical pads and associated routing on its interior surface 93. The device 100 can be connected to the electrical pads by any appropriate type of bond including a flip-chip bond, bump bond or wire bond.
As used herein, an IC device is any integrated collection of one or more electrical components including transistors, resistors, capacitors and diodes. In some implementations, an IC device is fabricated as a separate chip, which can be attached to one or more of a glass substrate or a cover glass of a glass package described herein. Any appropriate IC technology can be used, examples of which include but are not limited to transistor-transistor logic (TTL), CMOS, bipolar complementary metal oxide semiconductor (BiCMOS), laterally diffused metal oxide semiconductor (LDMOS), metal-oxide-semiconductor field-effect transistor (MOSFET) and the like. An IC device chip included in a package described herein can be between 50 and 300 microns thick in some implementations.
In some implementations, an electrical connection to a package exterior includes a connection to one or more bond pads or leads on an exterior surface of the package. Electrical connections to a package exterior can include any of plated, printed, screened, or dispensed conductive lines, and through-glass vias interconnects, including peripheral and non-peripheral through-glass via interconnects. An overview of various electrical connections are described below with respect to
In the example of
In some implementations, a glass package can include one or more through-glass via interconnects. In the example of
In some implementations, a package is configured for attachment to a flexible connector, also referred to as a ribbon cable, a flexible flat cable, or a flex tape. For example, in some implementations, the exterior pads 132 depicted in
While
As indicated above, in some implementations, a glass package includes multiple devices. For example, a glass package can include a MEMS sensor and an associated ASIC configured to process signals from the sensor. In some implementations, a MEMS device is formed on an interior surface of a glass substrate.
In the example of
In some implementations, one or more devices can be fabricated on or attached to the cover glass 96 of the glass package 90. In the example of
In some implementations, the IC device 102 can be attached to an exterior surface of the cover glass 96 or the glass substrate 92 of the glass package 90.
In some implementations, a package includes a signal transmission pathway for non-electrical signals, such as acoustic, thermal and light signals.
Transmission pathways for electrical and non-electrical signals can be incorporated through, on, or around either or both of a cover glass and a glass substrate of a glass package according to the desired implementation. Placement of conductive traces, through-glass via interconnects, pads, or other components of an electrical pathway, and ports or other components of a non-electrical signal pathway can vary according to the desired implementation. In some implementations, for example, a port can be disposed above or adjacent to a MEMS device or other device to provide direct access between a package exterior and the device. In some implementations, for example, a port can be positioned such that access to a device is indirect, with one or more obstructions between the device and the package exterior. In some implementations, positioning of a port can be determined by considerations including a particular application of the packaged device, device sensitivity to a signal, and protecting a device and other internal components of a package from environmental materials or energies such as dirt, dicing fluid, light, thermal radiation, and the like.
In some implementations, through-glass via interconnects can be disposed in a cover glass, with one or more on-glass devices such as a MEMS device and/or on-glass low-temperature-polycrystalline thin-film transistor (LTPS-TFT) on a device substrate. This configuration can allow through-glass via interconnect fabrication to occur on a separate glass from MEMS and/or LTPS-TFT fabrication. In some implementations, through-glass vias interconnects can be disposed in a device substrate, with one or more on-glass devices such as a MEMS device and/or on-glass LTPS-TFT on a surface of the device substrate. This configuration can facilitate streamlined metallization operations, for example.
The glass substrate 92 includes an interior surface 93 and an exterior surface 94. A MEMS device 104, conductive traces 122 and 122a, IC bond pads 120 and 120a, and interconnect bond pads 120b are formed on the interior surface 93. The IC bond pads 120 and 120a provide a connection to the IC device 102, with conductive traces 122a electrically connecting the MEMS device 104 to the IC bond pads 120a, and the conductive traces 122 providing electrical connection from the IC bond pads 120 to interconnect bond pads 120b. Interconnect bond pads 120b provide a point of connection for the through-glass via interconnects 124 in the cover glass 96. The interconnect bond pads 120b and the through-glass via interconnects 124 can be joined by solder bonds or other appropriate type of bonds. In the example of
The glass substrate 92 includes an interior surface 93, an exterior surface 94, and through-glass via interconnects 124. A MEMS device 104, conductive traces 122 and 122a, and IC bond pads 120 and 120a are formed on the interior surface 93. IC bond pads 120 and 120a provide a connection to the IC device 102, with the conductive traces 122a electrically connecting the MEMS device 104 to the IC bond pads 120a, and the conductive traces 122 providing electrical connection from the IC bond pads 120 to the through-glass via interconnects 124. Exterior pads 132 on the exterior surface 94 connect to the through-glass via interconnects 124 and provide an electrical interface for an external electrical connection. A joining ring 142 surrounds the through-glass via interconnects 124. The joining ring 142 joins the glass substrate 92 and the cover glass 96, forming a hermetic or non-hermetic seal around the IC device 102 and the MEMS device 104.
The glass substrate 92 includes an interior surface 93 and an exterior surface 94. A MEMS device 104, conductive traces 122 and 122a, IC bond pads 120 and 120a, and interconnect bond pads 120b are formed on the interior surface 93. The IC bond pads 120 and 120a provide a connection to the IC device 102, with the conductive traces 122a electrically connecting the MEMS device 104 to the IC bond pads 120a, and the conductive traces 122 providing electrical connection from the IC bond pads 120 to the interconnect bond pads 120b. The interconnect bond pads 120b provide a point of connection for the through-glass via interconnects 124 in the cover glass 96. The IC bond pads 120b and the through-glass via interconnects 124 can be joined by solder bonds or other appropriate type of bonds. A joining ring 142 surrounds the recess 99 and the through-glass via interconnects 124. The glass substrate 92 and the cover glass 96 are joined by the joining ring 142 as well as by bonds between the through-glass via interconnects 124 and the interconnect bond pads 120b.
In some implementations, a cover glass and a glass substrate can be sealed together using an intermediate material. For example, a cover glass and glass substrate can be sealed using an epoxy, including an ultraviolet (UV) curable epoxy or a heat-curable epoxy, a glass frit, or a metal. The intermediate material can contact an interior surface of a cover glass and an interior surface of a glass substrate to seal the cover glass and glass substrate together. In some implementations, a glass substrate, cover glass, or glass package includes one or more rings, referred to as bond rings or joining rings, of an epoxy, glass frit, or metal sealing material disposed between a cover glass and glass substrate. A joining ring can wholly or partially surround one or more of components of a partially or wholly fabricated package including one or more devices, recesses, or components of a conductive pathway. A joining ring can be shaped in any appropriate manner with example shapes including circles, ovals, rectangles, parallelograms and combinations thereof as well as irregular shapes. A joining ring can be continuous or can include breaks or other discontinuities according to the desired implementation. The joining ring can form a substantially hermetic seal or a non-hermetic seal according to the desired implementation. The term joining ring may be used to refer to a ring of sealing material formed on a cover glass or glass substrate prior to joining, as well as a ring of sealing material disposed between a cover glass and glass substrate after joining.
In some implementations, a joining ring includes an epoxy or other polymer adhesive. The width of an epoxy joining ring is sufficient to provide an adequate seal and can vary according to the desired implementation. In some implementations, a width of an epoxy joining ring is between about 50 microns and 1000 microns. In some implementations, an epoxy joining ring having a width of about 500 microns or greater provides a quasi-hermetic seal. In some other implementations, an epoxy joining ring provides a non-hermetic seal. A thickness of an epoxy joining ring can range from about 1-500 microns thick. In some implementations, a UV-curable or heat curable epoxy is used. Examples of UV-curable epoxies include XNR5570 and XNR5516 epoxies from Nagase ChemteX Corp., Osaka, Japan. An epoxy or other polymer adhesive can be screen printed or otherwise dispensed on one or both of a cover glass or glass substrate prior to joining the cover glass to the glass substrate. An epoxy seal can be formed when the cover glass and the glass substrate are then brought into contact and the epoxy is cured.
In some implementations, a joining ring includes a glass sealing material. In some implementations, a width of a glass joining ring is between about 20-500 microns. A thickness of a glass joining ring can range from about 0.1-100 microns thick. A glass joining ring can provide a hermetic seal or non-hermetic seal according to the desired implementation. A glass sealing material can be screen printed or otherwise dispensed on one or both of a cover glass or glass substrate prior to joining the cover glass to the glass substrate. A glass frit seal can be formed when the cover glass and the glass substrate are brought into contact under application of heat and/or pressure.
In some implementations, a joining ring includes a metal. A metal joining ring can be screen printed, plated or otherwise formed on a cover glass and glass substrate. Unlike epoxy and glass frit bonding, in which an epoxy or glass sealing material may be dispensed on only one of the glass substrate or cover glass prior to joining, corresponding metal joining rings are generally formed on each of the glass substrate and cover glass prior to joining to form a metal seal.
In some implementations, a joining ring includes a solderable metallurgy. Examples of solderable metallurgies include nickel/gold (Ni/Au), nickel/palladium (Ni/Pd), nickel/palladium/gold (Ni/Pd/Au), copper (Cu), palladium (Pd) and gold (Au). In some implementations, a joining ring includes a solder paste or preform. For example, a solder paste or preform can be printed on top of a joining ring including a solderable metallurgy.
In some implementations, a joining ring includes a eutectic metallurgy. Examples of eutectic alloys that may be used include indium/bismuth (InBi), copper/tin (CuSn), copper/tin/bismuth (CuSnBi), copper/tin/indium (CuSnIn), and gold/tin (AuSn). The composition of a metal joining ring that seals two glass components together can depend on the particular metallurgical systems used for joining rings on the glass components and the particular joining process used according to the desired implementation. Further description of metal joining rings in glass-to-glass bonding is given below with respect to
A joining ring can wholly or partially surround one or more of components of a glass package including one or more devices, recesses, or components of a conductive pathway.
In some implementations, one or more components of a partially or wholly fabricated glass package including one or more devices, recesses, or components of a conductive pathway may be outside a joining ring of the glass package.
In some implementations, there can be one or more discontinuities in a joining ring.
As indicated above, in some implementations, a glass package includes a signal transmission pathway between an encapsulated device and the package exterior. In some implementations, the signal transmission pathway provides fluid (i.e., gas and/or liquid) access between the package exterior and the device. For example, glass-encapsulated EMS devices including microphones, speakers and pressure sensors can include a pathway providing fluid access between the EMS device and the package exterior. Some examples of fluid access pathways are described above with respect to
In some implementations, a package includes one or more holes extending through a cover glass or glass substrate to provide fluid access to a device.
In some implementations, a recess in a cover glass or a glass substrate extends to a side edge of the cover glass or glass substrate to provide fluid access to a device accommodated by the recess.
In some implementations, one or more slots in a joining ring can provide fluid access to a device.
In some implementations, fluid access can be partially obstructed, for example, to provide some protection for one or more devices in a glass package from dicing fluid, dirt, debris and other environmental conditions during fabrication or use.
While
In some implementations, a signal transmission pathway is configured to transmit thermal energy. In some implementations, a heat transmissive pathway can include a hole through a glass substrate and/or a cover glass through which heat can be transmitted. The hole can be unfilled or filled. In some implementations, the presence, absence and/or type of fill material can be selected to transmit thermal energy by one or more of conduction, convection and radiation according to the desired implementation. For example, in some implementations, a hole is filled with a thermally conductive material.
As indicated above, in some implementations, a glass package includes one or more electrical connections from a device encapsulated by the glass package to an exterior of the glass package. An electrical connection between a device and an exterior of a glass package can include any electrical component, including wire bonds, conductive traces, conductive vias and conductive pads. Conductive traces can be formed on any surface of a glass package, including any surface of a glass substrate and any surface of a cover glass. In some implementations, metals are used to form conductive traces. In some other implementations, conductive traces are formed using a non-metallic material such as a conductive polymer.
Examples of metals that can be used include copper (Cu), aluminum (Al), gold (Au), niobium (Nb), chromium (Cr), tantalum (Ta), nickel (Ni), tungsten (W), titanium (Ti), palladium (Pd), silver (Ag) and alloys and combinations thereof. Examples of plated metal layers include Cu, Cu/Ni/Au, Cu/Ni/Pd/Au, Ni/Au, Ni/Pd/Au, Ni alloy/Pd/Au, and Ni alloy/Au. In some implementations, a conductive trace includes a bilayer of a main conductive layer overlying an adhesion layer. Examples of adhesion layers include chromium (Cr), titanium (Ti), and niobium (Nb). Examples of bilayers include Cr/Cu, Cr/Au and Ti/W. Adhesion layers may have thicknesses of a few nanometers to several hundred nanometers or more. The thickness of a conductive trace, including an adhesion layer if present, can be between about 1,000 Angstroms (Å) and 10,000 Å according the desired implementation. A width of a conductive trace can vary, for example, from less than 10 microns wide to over 100 microns wide. In various implementations, spaces between adjacent conductive traces can vary from less than 10 microns to 500 microns or larger. Conductive traces can be patterned in any appropriate manner to provide a desired connection. If multiple conductive traces are formed, the pitch can vary according to the desired implementation.
In some implementations, a package includes one or more conductive pathways on a side surface of a cover glass and/or glass substrate. In some implementations a package includes conductive traces on a side surface of a glass substrate and/or cover glass. An example of a package including conductive traces on a side surface is shown in
In some implementations, wire bonds, if present are located only on an interior of a glass package, such as the wire bond 136 depicted in
In some implementations, a glass package can include one or more metal wires inserted through a heated cover glass or glass substrate. In some implementations, one or more of a glass substrate and a cover glass of a glass package includes one or more through-glass via interconnects, which also may be referred to as through-glass vias or conductive through-glass vias. In some implementations, a through-glass via interconnect includes one or more conductive pathways that extend through a glass substrate or cover glass, as described above. A conductive pathway of a through-glass via interconnect can include metalized sidewalls of a through-glass via hole, a conductive fill material in a through-glass via hole, metal pins or posts embedded within a glass material, or a combination of these according to the desired implementation.
In some implementations, a package includes interior through-glass via interconnects, also referred to as non-peripheral through-glass via interconnects. Examples of non-peripheral through-glass via interconnects are shown in
In some implementations, a glass package includes peripheral through-glass via interconnects. In some implementations, a peripheral through-glass via interconnect can include via openings in top and bottom surfaces of a glass substrate or cover glass, a sidewall recessed from one or more side surfaces of the glass substrate or the cover glass, and one or more conductive pathways extending along the sidewall from the top surface to the bottom surface. Each of the top and bottom surfaces can be, for example, an exterior or interior surface of the glass substrate or cover glass.
The glass component 101 includes peripheral through-glass via interconnects 125. The peripheral through-glass via interconnects are multi-trace through-glass via interconnects, including multiple conductive traces 122c that extend between portions of the top surface 92a and the bottom surface 92b through the glass component 101. (For clarity, components behind glass surfaces in
As described above, non-peripheral and peripheral through-glass via interconnects can include via openings in opposing parallel surfaces of a glass substrate or cover glass.
In
The number, shape and placement of through-glass via interconnects may vary according to implementation. For example, one or more peripheral through-glass via interconnects may be located on the periphery of one, two, three or more sides of a glass substrate or cover glass. In some implementations, a glass package can include one or more peripheral through-glass via interconnects in addition to one or more non-peripheral through-glass via interconnects. In some implementations, multiple through-glass via interconnects can be arranged in an array. The orientation of through-glass via interconnects can vary according to the desired implementation.
The conductive traces 122c are continuous from the device 100 to the exterior pads 132. (A bottomside segment of each conductive trace 122c is obscured by a topside segment.) The shape and orientation of the through-glass via interconnects 124 with respect to a side surface can vary according to the desired implementation. In the example of
In some implementations, through-glass via holes are filled or partially filled by a metal, other conductive material, or a non-conductive material. In some other implementations, the interior of a through-glass via hole is left unfilled. If used, a filler material can be a metal, a metal paste, a solder, a solder paste, one or more solder balls, a glass-metal material, a polymer-metal material, a conductive polymer, a non-conductive polymer, an electrically conductive material, a non-conductive material, a thermally conductive material, a heat sink material, or a combination thereof. In some implementations, the filler material reduces the stress on a deposited thin film and/or plated layer. In some other implementations, a filler material seals the via holes to prevent transfer of liquids or gases through the via holes. A filler material may serve as a thermally conductive path to transfer heat from devices mounted on one side of a glass component to the other. In some implementations, in addition to or instead of sidewall metallization, a conductive pathway of a through-glass via interconnect includes a conductive filler material. In some implementations, one or more through-glass via holes can include a non-conductive filler material, such as a thermally conductive or sealing material. In some implementations, a through-glass via hole does not include a conductive pathway and is not used as a through-glass via interconnect, but can serve as a thermal transmission pathway or other pathway.
Cross-sectional profiles of through-glass via holes and through-glass via interconnects can vary according to the desired implementation. In some implementations, the through-glass via holes have sidewalls with a concave curvature extending from a planar glass substrate or cover glass surface to a point in the interior of the glass substrate or cover glass. In some implementations, the through-glass via holes have a tapered or v-shaped profile, with the sidewalls tapering from a larger via opening at one surface to a smaller via opening at the other surface. In some implementations, the through-glass via holes have a substantially uniform area throughout the glass substrate or cover glass, with the via holes having substantially straight, vertical sidewalls.
Additional details of through-glass via interconnects and methods of forming through-glass interconnects that may be used in accordance with various implementations are given in U.S. patent application Ser. No. 13/048,768, filed Mar. 15, 2011, and entitled “Thin Film Through-Glass Via And Methods For Forming Same,” and in U.S. patent application Ser. No. ______, filed concurrently with this application, and entitled “Die-Cut Through-Glass Via And Methods For Forming Same,” both of which are incorporated by reference herein.
In some implementations, a glass package includes a flexible connector or is configured to connect to a flexible connector. A flexible connector also may be referred to as a ribbon cable, a flexible flat cable or a flex tape. A flexible connector may include a polymer film with embedded electrical connections, such as conducting wires or traces, running parallel to each other on the same flat plane. A flexible connector also may include flex pads at one end, and contacts at the other end, with the conducting wires or traces electrically connecting individual flex pads with individual contacts. One example of a glass package configured to attach to a flexible connector is described above with respect to
A glass package 90 in the example of
The glass substrate 92 is generally a planar substrate having two substantially parallel surfaces, an interior surface 93 and an exterior surface 94. A ledge 162 having flex-attach pads 133 thereon allows for electrical connections to portions of the interior surface 93 that are enclosed by the cover glass 96. Conductive traces 122 on the interior surface 93 connect IC bond pads 120 to the flex-attach pads 133 on the ledge 162. The IC bond pads 120 may be used for connections to the IC device 102. The MEMS device 104 and the IC device 102 may be electrically connected to one or more of the flex-attach pads 133 directly or indirectly by the conductive traces 122 on the glass substrate 92. In the example shown, conductive traces 122a connect the MEMS device 104 to IC bond pads 120a and the IC bond pads 120a may be used for connections to the IC device 102. The particular arrangement of the electronic components associated with the glass substrate 92 is an example of one possible arrangement, with other arrangements possible.
In some implementations, portions of the conductive traces 122 that are exposed to the outside environment may be passivated. For example, the conductive traces 122 may be passivated with a passivation layer, such as a coating of an oxide or a nitride.
The glass package 90 shown in
In some implementations, the glass package 90 with the ledge 162 for connection to a flexible connector 103 may allow the glass package 90 to be located away from a PCB or other electronic component. This can allow the PCB or other electronic component to be located in a protected environment or can allow the glass package 90 to be located in a small enclosure, for example.
The glass substrate 92 is generally a planar substrate having two substantially parallel surfaces, an interior surface 93 and an exterior surface 94. A ledge 162 allows for electrical connections to portions of the interior surface 93 that enclosed by the cover glass 96. Conductive traces 122 on the interior surface 93 connect bond pads 120 to flex-attach pads 133. The MEMS device 104 may be electrically connected to one or more of the flex-attach pads 133 by the conductive traces 122 on the glass substrate 92. A flexible connector 103 may be bonded to the flex-attach pads 133 by an anisotropic conductive film (ACF) or solder, for example.
In some implementations, the flexible connector 103 can be attached to one or more IC devices (not shown). For example, the flexible connector 103 can be attached to one or more chip scale package (CSP) silicon dies for signal conditioning and formatting. This can allow further reduction of the dimensions of the glass package 90, as it does not accommodate an IC device. For example, a glass-packaged MEMS microspeaker can be located in the ear of a user, with associated control electronics in an IC device located outside the ear.
Implementations of methods of fabricating glass packages are described below with respect to
A glass substrate panel refers to a glass substrate that is configured to eventually be singulated. Glass substrate panels can include sub-panels cut from larger glass substrates. For example, in some implementations, a glass substrate panel can be a square or rectangular sub-panel cut from a larger panel of glass. In some implementations, a glass substrate panel can glass plate having an area on the order of four square meters. In some implementations, a glass substrate panel can be a round substrate with a diameter of 100 millimeters, 150 millimeters, or other appropriate diameter. In some implementations, a glass substrate panel thickness may be between about 300 and 700 microns, such as about 500 microns, though thicker or thinner substrates can be used according to the desired implementation.
As described above, devices such as IC devices and/or EMS devices can be fabricated on or otherwise attached to the interior surface of the glass substrate. In some implementations, for example, a glass substrate includes an array of EMS devices and associated IC devices, with the EMS devices fabricated on the glass substrate and the IC devices attached by flip-chip attachment. In some other implementations, for example, a glass substrate includes an array of EMS devices and associated IC devices, with the EMS devices and the IC devices fabricated on the glass substrate. In some other implementations, a glass substrate includes an array of EMS devices fabricated on or attached to the glass substrate with no IC devices, or an array of IC devices fabricated on or attached to the glass substrate with no EMS devices.
In addition to devices on the interior surface of the glass substrate panel, any number of other components such as joining rings, conductive traces, pads, traces, interconnects, ports, other signal transmission pathways and the like may be present on any surface of or through the glass substrate panel. Any number of devices can be arrayed on the glass substrate panel. For example, tens, hundreds, thousands or more devices may be on a single glass substrate panel. The devices and associated components may all be the same or may differ across the glass substrate panel according to the desired implementation.
The process 200 continues at block 204 with providing a cover glass panel having an array of recesses in an interior surface. As described above, a recess can be configured to accommodate one or more devices on a glass substrate according to the desired implementation. The cover glass panel can include additional features and components including joining rings, conductive traces, pads, interconnects, ports, other signal transmission pathways and the like.
A cover glass panel refers to a glass substrate that is configured to eventually be singulated. Cover glass panels include sub-panels cut from larger glass substrates. In some implementations, a cover glass panel can be approximately the same shape and area as the glass substrate panel to which it will be joined. In some implementations, a cover glass panel thickness may be between about 300 and 700 microns, such 500 microns, though thicker or thinner substrates can be used according to the desired implementation.
The process 200 continues at block 206 with alignment of the cover glass panel with the glass substrate panel. The cover glass panel is aligned with the glass substrate panel such that recesses configured to accommodate devices are each positioned over the one or more devices to be accommodated and other corresponding components on the cover glass panel and glass substrate panel are aligned. In some implementations, joining rings on the cover glass panel are aligned with corresponding joining rings on the glass substrate panel. For example, if the cover glass panel is to be joined to the glass substrate panel by solder bonding, metal joining rings of each device unit of the glass substrate panel can be aligned with corresponding metal joining rings on the cover glass panel. Aligning the cover glass panel and the device substrate panel can involve standard flip-chip placement techniques, including the use of alignment marks and the like.
The process 200 continues at block 208 with joining the cover glass panel to the glass substrate panel. In some implementations, after joining the cover glass panel to the glass substrate panel, the devices on the glass substrate panel are encapsulated between the cover glass panel and the glass substrate panel. Any appropriate method of joining the cover glass panel to the glass substrate panel can be used, with examples including solder bonding, adhesive bonding, and thermocompression bonding. Solder bonding involves contacting the cover glass panel and glass substrate panel to a solder paste or other solderable material in the presence of heat. One type of solder bonding that can be used is eutectic metal bonding, which involves forming a eutectic alloy layer between the cover glass panel and the glass substrate panel. This is discussed further below with respect to
Process conditions such as temperature and pressure during a joining process can vary according to the particular joining method and desired characteristics of the area surrounding an encapsulated device. For example, for solder bonding, including eutectic bonding, the joining temperature can range from about 100° C. to about 500° C. as appropriate. Example temperatures can be about 150° C. for indium/bismuth (InBi) eutectic, about 225° C. for CuSn eutectic and about 305° C. for AuSn.
In some implementations, the joining operation involves setting a defined pressure in the encapsulated area. This may involve pumping a gas in or out of a chamber in which the joining occurs to set the desired pressure. After the joining operation, the pressure in the encapsulated area to which the device is exposed can be below atmospheric, above atmospheric or at atmospheric pressure. The composition of the gas also can be tailored to a desired composition. For example, a desired inert gas and pressure to damp a proof mass of a MEMS accelerometer can be dialed in during the joining process. The process 200 continues at block 210 by singulating the joined cover glass and glass substrate panels to form individual glass packages, also referred to as dies, each glass package including one or more encapsulated devices and associated components.
In some implementations, the glass substrate panel is a sub-panel of a larger panel. On-glass device fabrication can occur at a first panel level, with a joining operation occurring at a sub-panel level.
In another example of a fabrication process, MEMS accelerometers can be fabricated directly on a glass substrate, for example, by sequentially depositing a seed layer and a resist mask, plating through the resist mask, then stripping the resist and etching the unplated seed layer. This sequence can be repeated to build a device including, a plated proof mass and springs, layer by layer, with gaps for capacitance change sensing fabricated by plating copper (Cu) or another metal, then selectively etching the Cu layer, to release the plated proof mass. The proof mass and springs can be fabricated with nickel (Ni) or a nickel based alloy such as nickel manganese (NiMn).
Associated components including conductive traces, pads, through-glass via interconnects, and joining rings also can be fabricated in block 302. The fabrication of any associated component can be performed prior to, during or after fabrication of the MEMS devices. For example, joining rings can be plated during a plating operation in a MEMS device fabrication process. Examples of MEMS devices that can be fabricated include pressure sensors, microphones, speakers, accelerometers, gyroscopes, RF electrical filters, other electrical filters, medical devices, field sensing devices, and displays.
In some implementations, a first glass substrate panel can be sized such that the length and width dimensions, also referred to as the lateral dimensions, of the first glass substrate panel are each greater than 200 mm. In some implementations, the first glass substrate panel is rectangular. In some implementations, the lateral dimensions of the first glass panel can be at least 600 mm×800 mm. In some implementations, one or both of the width and length can be 1 meter or greater.
The process 300a continues at block 304 with scribing and breaking the first glass substrate panel to form a glass substrate sub-panel. In some implementations, the sub-panel has length and width dimensions both less than 200 mm. For example, a glass panel of 680 mm×880 mm can be divided into 20 sub-panels of 170 mm×176 mm. In some implementations, the sub-panel has lateral dimensions of greater than 200 mm. Standard scribe and break processes can be used. The process 300a continues at block 306 with attaching IC devices to the glass substrate sub-panel. Flip-chip attachment or other appropriate attachment processes can be used. This forms a glass substrate sub-panel having an array of MEMS devices and associated IC devices disposed on its interior surface. In some other implementations, operation 306 is not performed. For example, processes for fabricating packages that do not include IC devices enclosed within package cavities do not include operation 306.
The process 300c for forming a cover glass sub-panel starts at block 308 with etching recesses in a cover glass sub-panel. The term sub-panel is used to indicate that the cover glass sub-panel is the same size as the glass substrate sub-panel formed in operation 304 of the process 300a; the cover glass sub-panel may or may not be formed a larger panel according to the desired implementation. In the example of
The process 300c continues at a block 310 with metallization of the cover glass sub-panel. Metallization can include formation of any of joining rings, through-glass via interconnects, conductive routing and pads, on one or more surfaces on or through the cover glass sub-panel. In some implementations in which the cover glass is not metalized, such as cover glass 96 depicted in
The process 300 then continues at block 312 with joining the cover glass sub-panel to the glass substrate sub-panel. Joining techniques are described above with respect to
In
The process 300b begins at block 303 with fabrication of MEMS and IC devices and associated components on a first glass substrate panel. Examples of dimensions of a first glass substrate panel are described above with respect to
Eliminating a separately packaged, attached IC device from a package can facilitate smaller packages in some implementations. In addition to allowing elimination of space to accommodate separate packaging, spacing between a MEMS device and an IC device can be reduced. Tolerances for on-glass device placement can be lithographic tolerances in some implementations, which can be on the order of 3-5 microns. This is contrasted with separately packaged IC devices for which mechanical tolerances used for attachment of an IC device to a glass substrate can be on the order of 20-40 microns, for example. The process 300b continues at block 304 with scribing and breaking the first glass panel to form a glass substrate sub-panel, as described above with respect to
In the examples of
In some other implementations, devices can be fabricated on a glass panel that undergoes further processing without being divided into sub-panels. For example, in some implementations, panels having lateral dimensions of greater than 200 mm can undergo post-device fabrication processing. In some other implementations, devices can be fabricated on panels having lateral dimensions of less than 200 mm.
The plan view depicted in
In some implementations, formation of the MEMS device 104, the conductive traces 122 and 122a, the IC bond pads 120 and 120a, the interconnect pad 120b, and the joining ring 142a on the interior surface 93 is performed across all device units 212 of the glass substrate panel 192 in one or more batch processes.
In some implementations, the IC device 102 can be attached by a flip chip bonding process in which flux is applied to the pads 120 and 120a, the IC device is placed on the interior surface 93 of the glass substrate panel 192, and the glass substrate panel 192 is reflown in a reducing atmosphere to form solder bond 134 between the IC bond pads 120 and 120a (not shown) and the IC device 102. The underfill material 216 can then be dispensed around the IC device 102 and cured. In some implementations, attachment of IC devices 102 to device units 212 is performed across all device units 212 of the glass substrate panel 192 in a batch process.
In some implementations, formation of the recesses 99 and through-glass via holes 152 is performed across all cover glass units 213 of a cover glass panel 192. Details of various implementations of forming recesses and through-glass via holes in a cover glass panel are discussed below with respect to
Forming the through-glass via holes and recesses can involve wet etching or sandblasting, or a combination of these techniques to remove material from the cover glass panel. Wet etch solutions include hydrogen fluoride based solutions, e.g., concentrated hydrofluoric acid (HF), diluted HF (HF:H2O), buffered HF (HF:NH4F:H2O), or other suitable etchant with reasonably high etch rate of the glass substrate and high selectivity to the masking material. The etchant also may be applied by other techniques such as spraying and puddling. A wet etch sequence to form through-glass via holes may be performed consecutively on one side and then the other, or on both sides simultaneously. If sandblasting is used, masking and sandblasting each side may be performed simultaneously or consecutively.
The recesses and through-glass via hole openings can be formed in the same or different operations. For example, in some implementations, the through-glass via holes can be etched, followed by patterning and etching of the recesses. In some other implementations, the through-glass via holes and recesses can be patterned and sandblasted simultaneously. Moreover, the techniques to pattern and form the recesses can be the same or different techniques as used to pattern and form the through-glass via holes.
In some implementations, multiple recesses for each cover glass unit on the cover glass panel are fabricated, such that each of the resulting individual packages includes multiple cavities. In some implementations in which multiple cavities are formed, all or some of multiple cavities can be independently and hermetically closed to the ambient, all or some of the cavities can share a closed and hermetic environment, or all or some of the cavities can partially or completely be open to ambient. In some implementations, one or more of the recesses and/or through-glass via holes can span two adjacent cover glass units, such that after die singulation, these recesses or through-glass via holes are open at a side of the glass package. In some implementations, a port or peripheral through-glass via hole can be formed.
The process 330 then continues at block 334 with deposition of a metal seed layer on the cover glass panel, including on the interior and exterior surfaces of the cover glass panel and on the sidewalls of the through-glass via holes. The metal seed layer provides a conductive substrate on which a metal layer can be plated. The metal seed layer is generally conformal to the underlying exterior, interior and sidewall surfaces of the cover glass panel to form a continuous metal seed layer connecting the interior and exterior surfaces of the cover glass panel. Examples of metals include Cu, Al, Au, Nb, Cr, Ta, Ni, W, Ti and Ag. In some implementations, an adhesion layer is conformally deposited to prior to deposition of the metal seed layer. For example, for a Cu seed layer, examples of adhesion layers include Cr and Ti. The adhesion layer and seed layer may be deposited by sputter deposition though other conformal deposition processes, including atomic layer deposition (ALD), evaporation and other chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes may be used. Example thicknesses of the adhesion layer range from about 100 Å to about 500 Å, or more particularly from about 150 Å to 300 Å, though the adhesion layer can be thinner or thicker according to the implementation. Example seed layer thicknesses range from about 800 Å to 10000 Å, or more particularly from about 1000 Å to about 5000 Å, though the metal seed layer can be thinner or thicker according to the desired implementation. In one example, a Cr/Cu adhesion/seed layer having a thickness of about 200 Å/2000 Å is deposited.
The process 330 then continues at block 336 with patterning joining rings, traces and pads on the cover glass panel. Block 336 can include applying and patterning a mask on the interior and exterior surfaces of the cover glass panel. In some implementations, a laminate photoresist that tents over the through-glass via hole openings and recesses is used as a mask material. The photoresist can be patterned by techniques including masked exposure to radiation and chemical development. The laminate photoresist can be developed to allow plating inside the through-glass via holes, as well as patterned on the exterior and interior surfaces to form the electrical routing, pads (including dummy pads and electrically connected pads) and joining rings according to the desired implementation. One example of a laminate photoresist that tents is a DuPont® WBR2000 dry film photoresist, which is applied to the substrate surface by lamination. Other resists may be used including dry film, liquid and epoxy-based resists.
The process 330 then continues at block 338 with plating the cover glass panel to simultaneously form the through-glass via interconnects, joining rings, traces and pads. Examples of metals that can be plated to form the through-glass via interconnects, joining rings, traces and pads include Cu, Ni and Ni alloys including nickel cobalt (NiCo), nickel manganese (NiMn) and nickel iron (NiFe), and combinations of these. In some implementations, block 338 includes plating a thin layer of one or more metals such as Au or palladium Pd on a thicker layer of a main conductor metal. Examples of metal stacks that can be formed in block 336 include Cu, Cu/Ni/Au, Cu/Ni alloy/Au, Ni/Au, Ni alloy/Au, Ni/Pd/Au, Ni alloy/Pd/Au, Ni/Pd and Ni alloy/Pd.
The process 330 then continues at block 340 with removing the remaining resist and unplated metal seed layer. Block 340 can involve exposing the resist to an appropriate solvent and the metal seed layer to a wet or dry etch, and can be performed on a single side at a time or on both sides simultaneously.
As indicated above, in some implementations, a metal joining ring is used to join a cover glass and a glass substrate. A metal joining ring can provide a hermetic seal around one or more devices in some implementations. A metal joining ring can include a solder bond in some implementations. A solder bond can be formed from a eutectic or non-eutectic solder material according to the desired implementation. A metal joining ring can include an intermetallic compound in some implementations.
The joining rings 142a and 142b each include one or more solderable metals, and can have the same or different metallurgies. Examples of metals that can be included in a joining ring 142a or 142b include Cu, Al, Au, Nb, Cr, Ta, Ni, W, Ti, Pd, Ag and alloys thereof.
In some implementations, one or more layers of Cu, Cu alloys, Ni, Ni alloys, or a combinations of these to provide most of the thickness of the joining rings 142a and 142b. In some implementations, one or more layers of an easily soldered metal such as Pd or Au can be used to provide a top thickness of the joining rings 142a and 142b prior to soldering. Examples of joining ring metallurgies include Cu, Cu/Ni/Au, Cu/Ni/Pd/Au, Ni/Au, Ni/Pd/Au, Cu/Ni alloy/Au, Cu/Ni alloy/Pd/Au, Ni alloy/Au, and Ni alloy/Pd/Au. Examples of Ni alloys include NiCo, NiMn and NiFe. Example thicknesses of each layer can be between about 1 and 10 microns for Cu or Cu alloy layers, between about 1 and 20 microns for Ni or Ni alloy layers, less than about 1 micron from Au layers, and less than about 0.5 microns for Pd layers. Other thicknesses can be used according to the desired implementation.
In some implementations, a width (W) of each of the joining rings 142a and 142b can be between about 20 microns and 500 microns. In the example depicted in
As indicated above, the solder bond 164 can have a non-eutectic or eutectic metallurgy. In some implementations, a lead-free metallurgy is used. Examples of eutectic solders include used include InBi, CuSn, CuSnBi, CuSnIn, and AuSn. Melting temperatures of these eutectic alloys can be about 150° C. for the InBi and CuSnIn eutectic alloys, about 225° C. for the CuSn eutectic alloy, and about 305° C. for the AuSn eutectic alloy. Examples of non-eutectic solders include indium (In), indium/silver (InAg) and tin (Sn) solders.
A solder material can be added to a joining ring on a glass component by a method such as plating, screen printing or solder jetting. In the case of eutectic or other alloys, the composite metals can be plated, printed or jetted sequentially or as a composite. A solder bond is formed by applying heat and reflowing the solder material. The solder material wets and alloys with the joining rings, forming a solid bond when solidified. In some implementations, a soldering process involves using a reducing agent to reduce oxidation, which can slow or prevent a solder bond from forming. In some implementations in which a eutectic alloy is used, no reducing agent is used. This can be desirable in implementations where reducing agent trapped in a package cavity can adversely affect the performance or durability of one or more devices disposed in the cavity.
In some implementations, the metal joining 142 is
In some implementations, a glass component of a package includes a coating on an exterior surface. For example, a glass substrate and/or cover glass as described above can be coated with a polymer coating. It should be noted that the implementations are not limited to all-glass packages as described above, but also can be implemented with any package including a glass component. For example, a package can include a coated glass substrate and a non-glass lid or cover.
A coating can be used to increase opacity, provide package markings, increase package visibility, increase package durability, and increase scratch-resistance. For example, in some implementations, a coated surface can be marked with industry standard marking process to provide a unique identification number for the packaged device. In another example, a surface is selectively coated in pattern to provide a signal transmission pathway to an encapsulated device and enable optical communication between a packaged device and the outside.
In
A coating can be applied to one or more surfaces of a glass package. For example, for a package that includes two major exterior surfaces connected by four side surfaces, any number of the major exterior and/or side surfaces can be wholly or partially coated.
In some implementations, a coating includes a vacuum-deposited film, including films deposited by sputter deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), evaporation, and plasma spray deposition. In some implementations, a coating includes an inorganic dielectric film. Examples include carbon (C) including diamond-like carbon and near-diamond-like carbon, silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN) and silicon nitride (SiN). In some implementations, a coating includes a metal film. Examples include titanium (Ti), tungsten (W), titanium/tungsten (TiW), chrome/gold (CrAu), and gold (Au). Metal films can be used in implementations in which the coated surface does not include through-glass vias, bond pads, conductive traces or other electrical components. Example thicknesses of vacuum-deposited dielectric or metal coatings can range from about 0.1 to about 5 microns. In some implementations, a vacuum-deposited coating has a thickness of less than about 2 microns.
In some implementations, a coating includes a polymer film. Polymer films can include spun-on films, dipped film, brushed-on films, spray-on films, rolled-on films and laminated films. Example of polymers include SU-8, polyimide, benzocyclobutene (BCB), polynorbornene (PNB), PID polymer available from Nippon Steel Corporation, particle-loaded polymers including polymers loaded with particles of metal, dielectric, or long chain polymer compounds such as a SiO2 particle filled epoxy available from Shin-Etsu Chemical Company, and other epoxies such as epoxies as Master Bond epoxy, polyurethanes, polycarbonates, and silicones. In some implementations, dyes or other additives can be added to make a polymer coating colored or black. Example thicknesses of a polymer coating range from about 10 to 100 microns. In some implementations, a polymer coating has a thickness of less than about 50 microns. In some implementations, a coating is formed from a photoimageable polymer film. Such a coating can be patterned by photolithography according to the desired implementation.
In some implementations, a coating includes an anisotropic conductive film (ACF). An ACF film can enable contact to an electrical feed-through or other electrically active components.
In some implementations, a coating can include an inorganic dielectric film and a polymer film. For example, a package can include a scratch resistant vacuum-deposited inorganic dielectric across one or more surfaces, with polymer coverage on package corners. An inorganic dielectric film can be under or over the polymer film according to the desired implementation. Similarly, in some implementations, a coating can include a metal film and a polymer film.
Coating can be performed at any appropriate time during a manufacturing process. For example, it can be performed at a panel level of a batch process at any appropriate point prior to singulation or at on an individual package level after singulation. A glass substrate and/or cover glass panel, for example, can be coated prior to or after joining the glass substrate and cover glass panel. A glass substrate panel can be coated, for example, prior to or after fabrication of one or more devices or other components on its interior surface. Similarly, a cover glass panel can be coated, for example, prior to or after formation of recesses or other components. In some other implementations, coating can be performed at a batch level after singulation.
As indicated above, in some implementations, a glass package as described herein can be part of a display device. In some other implementations, non-display devices fabricated on glass substrates can be compatible with displays and other devices that are also fabricated on glass substrates, with the non-display devices fabricated jointly with a display device or attached as a separate device, the combination having well-matched thermal expansion properties.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above also may be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other possibilities or implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of an IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, a person having ordinary skill in the art will readily recognize that such operations need not be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
