The present invention relates generally to integrated circuit packaging and more particularly to a thin array plastic package and a process for fabricating the thin array plastic package.
An etch back process for fabricating an integrated circuit package is disclosed in U.S. Pat. No. 6,498,099, assigned to the assignee of the present application, the entire contents of which are incorporated herein by reference. According to this process, a copper substrate strip is first subjected to a partial etch on one of both of the top and bottom surfaces to create a pattern of contact leads (pads) and a die attach pad (paddle). After wire bonding the contacts to a singulated semiconductor de, followed by overmolding and curing of the mold, the leadframe strip is exposed to a second immersion etch for exposing the contact pads in an array pattern (i.e., multi-row) or perimeter pattern (i.e., single row), as well as the die attach pad. In the case of a package with multi-row I/O leads, this etch back step eliminates the previously required two additional saw singulation operations (i.e., to sever the inner leads from the outer leads), and in both the single-row and multi-row configurations, the etch back step eliminates the previously required post mold processing steps (e.g., mold deflashing) and ensures superior device yield over prior processing techniques. Additionally, this technique allows for high I/O pad density and pad standoff from the package bottom, thereby reducing stress in the solder joint during PCB temp cycling. Further, the technique allows for the use of a pre-singulation strip testing technique since the electrical I/O pads are isolated from each other. This feature greatly increases the handling and throughput of the test operation as compared to prior processes.
According to co-pending U.S. patent application Ser. No. 09/802,678 for a Leadless Plastic Chip Carrier With Etch Back Pad Singulation, assigned to the assignee of the present application, the entire contents of which are incorporated herein by reference, a build up fabrication process is provided. The build up process is carried out on a copper substrate strip. Metal layers are selectively plated up on the copper substrate strip to provide build-up die attach pads, each circumscribed by at least one row of contact pads (I/P pads) on the copper strip. Semiconductor dice are fixed to respective die attach pads and gold wires are bonded between pads of the semiconductor dice and respective contact pads. The packages are then molded by placing the substrate strip in a mold. Following molding of the packages, the copper substrate strip is etched away to expose the die attach pad and the contact pads of each package.
These processes provide advantages not previously realized in the art. However, further developments in IC packaging are driven by specific applications and continued demand for improved reliability, electrical performance, decreased size and cost of manufacture.
According to one aspect of the present application, there is provided a process for fabricating an integrated circuit package. The process includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric: mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.
In accordance with another aspect of the present invention, there is provided an integrated circuit package that includes a package base including a non-conductive material and a plurality of contact pads extending through and protruding from the non-conductive material; a semiconductor die mounted to the package base and electrically connected to various ones of the contact pads; and a lid fixed to the package base and covering the semiconductor die in a cavity between the lid and the package base.
Advantageously, integrated circuit package according to embodiments of the present invention includes an air cavity through which the wire bonds travel. Thus, the wires between the semiconductor die and the contact pads span an air gap rather than traveling through mold compound. The air has a lower dielectric constant than mold compound and therefore the electrical impedance of the gold wire is much lower when the wire runs through air rather than through mold compound. Thus signal distortion at high frequencies is inhibited. Additionally, semiconductor dice that are sensitive to pressure, including MEMS (micro electromechanical systems), GaAs dice etc. are less likely to be damaged during assembly as there is no molding material molded in a pressurized molding step.
Also, the die attach pad provides a good thermal path for thermal dissipation from the semiconductor die. The contact pads allow for different design variations since there is no lead connection as in the leadless plastic chip carrier. In the embodiment including the moat around each contact pad, signals are shielded by grounding for increased electrical performance.
The present invention will be better understood with reference to the drawings and the following description, in which:
Reference is made to
A process for manufacturing the integrated circuit package 20 will now be described in more detail, with continued reference to
Referring now to
The etched away portions of the substrate 34 are then filled with a suitable dielectric (non-conductive) material 28. In the present embodiment, the etched away portions of the substrate 34 are filled with a liquid crystal polymer by locating the substrate 34 in a mold and injecting the liquid crystal polymer to fill out the etched away portions of the substrate 34, as shown in
The second side of the substrate 34 is selectively plated with a suitable metal or metals to act as an etch resist and suitable for wire bonding. Suitable metals include, for example, silver (Ag) or nickel and palladium (Ni/Pd) or nickel and gold (Ni/Au). To selectively plate with Ag, Ni/Pd or Ni/Au, a plating mask is first added to the second surface of the substrate 34. As will be appreciated, the plating mask is a photo-imageable plating mask and is applied to the entire top surface of the substrate 34. The photo-imageable plating mask is then imaged with a photo-tool by exposure to ultraviolet light masked by the photo-tool. The photo-imageable plating mask is then developed to provide the pattern with exposed areas of the substrate 34, as shown in
After patterning the plating mask, the second side of the substrate 34 is then plated with the suitable metal or metals for facilitating wire bonding and acting as an etch resist during subsequent etching. The remainder of the plating mask is then stripped away to provide the selectively plated substrate 34 shown in
The substrate 34 is then immersion or pressurized spray etched to fully pattern the die attach pad 24 and the contact pads 26. As shown in
Next, a barrier layer 21 is deposited on the second side of the dielectric material 28 and on edge or surrounding portions of the die attach pad 24 and the contact pads 26 (
A singulated semiconductor die 29 is then mounted to the die attach pad 24, on the second side of the substrate 34 using known means such as epoxy mounting followed by curing of the epoxy. Next, gold wire bonds 30 are bonded between the semiconductor die 29 and the contact pads 26 to electrically connect pads of the semiconductor die 29 to the contact pads 26 (
After mounting to the die attach pad 24 and electrically connecting the semiconductor die 29 to the contact pads 26, a lid 32 is fixed to the package base to cover the semiconductor die 29 and wire bonds 30, as shown in
Singulation of the individual integrated circuit package 20 is then performed either by saw singulation or die punching. In the present embodiment, the individual integrated circuit package 20 is saw singulated to provide the integrated circuit package shown in
Referring now to
In the embodiment shown in
After patterning the plating mask, the second side of the substrate 34 is plated with the suitable metal to act as an etch resist during subsequent etching. The remainder of the plating mask is then stripped away to provide the selectively plated substrate 34. As shown in
The substrate 34 is immersion or pressurized spray etched to fully pattern the plurality of die attach pads 24 and the contact pads 26 (
Next, a barrier layer 21 is deposited on the second side of the dielectric material 28 and on edge or surrounding portions of each of the die attach pads 24 and the contact pads 26 (
A singulated semiconductor die 29 is then mounted to the die attach pads 24, on the second side of the substrate 34 using known means such as epoxy mounting followed by curing of the epoxy. Gold wire bonds 30 are then bonded between the semiconductor die 29 and the contact pads 26 to electrically connect pads of the semiconductor die 29 to the contact pads 26 (
After mounting to the die attach pads 24 and electrically connecting the semiconductor die 29 to the contact pads 26, a lid 32 is fixed to the package base to cover the semiconductor die 29, as shown in
Singulation of the individual integrated circuit package 20 is then performed either by saw singulation or die punching. In the present embodiment, the individual integrated circuit package 20 is saw singulated to provide the integrated circuit package shown in
Referring now to
After mounting to the die attach pad 24 and electrically connecting the semiconductor die 29 to the contact pads 26, a lid 32 is fixed to the package base to cover the semiconductor die 29 and wire bonds 30, as shown in
Specific embodiments of the present invention have been shown and described herein. However, modifications and variations to these embodiments are possible. For example, rather than mounting the semiconductor die and then wire bonding as described in the embodiment shown in
Other modifications and variations are possible. For example, rather than filling out the etched away portions of the substrate by molding liquid crystal polymer, the etched away portions can be filled by screen printing or laminating any suitable dielectric material. Also, in the above-described embodiments, a soldermask barrier layer is deposited. It will be understood that this barrier layer is optional and further, other barrier layers can be used such as liquid crystal polymer to provide a moisture barrier. Advantageously, a liquid crystal polymer layer also improves adhesion and reliability. Also, other materials are possible for a barrier layer, for example to dampen or enhance radio frequency or electromagnetic interference. Rather than mounting the semiconductor die to the die attach pad using epoxy, other suitable mounting means can be used. Further, in the above-described embodiments, the lid is described as being liquid crystal polymer. Other lid materials such as glass, metal and ceramic are possible, however. The lid can be fixed to a periphery of the integrated circuit package using any suitable means such as epoxy or solder. Rather than using a photo-imageable etch-resistant mask on the copper substrate 34, as described with reference to, for example.
Still other modifications and variations may occur to those skilled in the art. All such modifications and variations are believed to be within the sphere and scope of the present invention.
This application is a divisional application of U.S. Ser. No. 11/183,290, filed Jul. 15, 2005, the entirety of which is referenced herein.
Number | Name | Date | Kind |
---|---|---|---|
4530152 | Roche et al. | Jul 1985 | A |
4685998 | Quinn et al. | Aug 1987 | A |
4812896 | Rothgery et al. | Mar 1989 | A |
5066831 | Spielberger | Nov 1991 | A |
5157480 | McShane et al. | Oct 1992 | A |
5200362 | Lin et al. | Apr 1993 | A |
5200809 | Kwon | Apr 1993 | A |
5214845 | King et al. | Jun 1993 | A |
5216278 | Lin et al. | Jun 1993 | A |
5221642 | Burns | Jun 1993 | A |
5273938 | Lin et al. | Dec 1993 | A |
5277972 | Sakumoto et al. | Jan 1994 | A |
5279029 | Burns | Jan 1994 | A |
5293072 | Tsuji et al. | Mar 1994 | A |
5332864 | Liang et al. | Jul 1994 | A |
5343076 | Katayama et al. | Aug 1994 | A |
5406124 | Morita et al. | Apr 1995 | A |
5424576 | Djennas et al. | Jun 1995 | A |
5444301 | Song et al. | Aug 1995 | A |
5457340 | Templeton, Jr. et al. | Oct 1995 | A |
5474958 | Djennas et al. | Dec 1995 | A |
5483099 | Natarajan et al. | Jan 1996 | A |
5578869 | Hoffman et al. | Nov 1996 | A |
5604376 | Hamburgen et al. | Feb 1997 | A |
5608267 | Mahulikar et al. | Mar 1997 | A |
5639990 | Nishihara et al. | Jun 1997 | A |
5640047 | Nakashima | Jun 1997 | A |
5641997 | Ohta et al. | Jun 1997 | A |
5646831 | Manteghi | Jul 1997 | A |
5650663 | Parthasarathi | Jul 1997 | A |
5683806 | Sakumoto et al. | Nov 1997 | A |
5696666 | Miles et al. | Dec 1997 | A |
5701034 | Marrs | Dec 1997 | A |
5710064 | Song et al. | Jan 1998 | A |
5710695 | Manteghi | Jan 1998 | A |
5777382 | Abbott et al. | Jul 1998 | A |
5894108 | Mostafazadeh et al. | Apr 1999 | A |
5976912 | Fukutomi et al. | Nov 1999 | A |
6001671 | Fjelstad | Dec 1999 | A |
6008068 | Yamada | Dec 1999 | A |
6057601 | Lau et al. | May 2000 | A |
6124637 | Freyman et al. | Sep 2000 | A |
6194786 | Orcutt | Feb 2001 | B1 |
6229200 | McLellan et al. | May 2001 | B1 |
6294830 | Fjelstad | Sep 2001 | B1 |
6306685 | Liu et al. | Oct 2001 | B1 |
6459163 | Bai | Oct 2002 | B1 |
6489557 | Eskildsen et al. | Dec 2002 | B2 |
6498099 | McLellan et al. | Dec 2002 | B1 |
6528877 | Ernst et al. | Mar 2003 | B2 |
6585905 | Fan et al. | Jul 2003 | B1 |
6635957 | Kwan et al. | Oct 2003 | B2 |
6762118 | Liu et al. | Jul 2004 | B2 |
7070340 | Crane et al. | Jul 2006 | B2 |
20030015780 | Kang et al. | Jan 2003 | A1 |
20030183920 | Goodrich et al. | Oct 2003 | A1 |
Number | Date | Country |
---|---|---|
59-208756 | Nov 1984 | JP |
Number | Date | Country | |
---|---|---|---|
Parent | 11183290 | Jul 2005 | US |
Child | 11798417 | US |