Patent Application
20130020711
The present disclosure is in the field of semiconductor packaging and more particularly in the field of copper pillar interconnects in semiconductor packaging.
Integrated circuit (IC) fabrication processes have produced ICs with reduced node spacing in the range of 48 nm and 28 nm nodes, for example. Material having an extremely low dielectric constant (ELK) has been used to accommodate the reduced node spacing and to enhance electrical performance of the ICs that are produced with such small node spacing. The ELK material may include relatively porous material which may be susceptible to cracking in response to certain stresses.
Interconnect pillars constructed from more rigid conductive materials such as copper have been used along with solder in certain solder bump connections between a semiconductor die and a substrate. In electronic packaging, for example, a flip chip can include a pillar that extends from a contact on a die or wafer to a solder connection on a substrate. The solder connection can be a solder on pad (SOP) connection, for example.
The use of pillars provides an improvement over earlier semiconductor interconnect techniques by allowing a very high density of interconnects. The metallurgical properties of the pillars compared to earlier solder structures allow the smaller pitch connections to maintain an appropriate standoff distance between a semiconductor die and a substrate to which it is connected. The use of copper pillars also reduces electromigration (EM) in the interconnects. However, the use of copper pillars can make a backend silicon structure more susceptible to cracking during package assembly.
During the processing of flip chips, the substrate and semiconductor die are subject to substantial heating and cooling. The semiconductor die may be constructed from a material such as silicon which has a coefficient of thermal expansion (CTE) of about 2.6×10−6/° C. and the substrate may have a CTE in the range of about 15×10−6/° C. to about 17×10−6/° C. The CTE mismatch between the substrate and die causes the substrate to expand and contract more than the die during a heating and cooling cycle. In packages that include interconnects with copper pillars rather than traditional solder bumps to accommodate finer bump pitch, the copper of the pillars may not be able to deform enough to take up the stress caused by the thermal expansion mismatch between the die and substrate. The higher Young's modulus of the copper pillar causes more of the stress to be “transferred” to the sensitive ELK layers of the die. This increases the chance for ELK layer cracking for flip chip type interconnects. Such cracking due to high stress in the Extremely Low Dielectric Constant (ELK) layers is a common failure of semiconductor packages.
For a more complete understanding of the present disclosure, reference is now made to the following detailed description and the accompanying drawings. In an exemplary embodiment, a pillar for a flip chip interconnect is provided. The pillar includes an electrically conductive material such as copper, gold or silver.
An apparatus according to an aspect of the present disclosure includes a semiconductor die and at least one conductive pad disposed on a surface of the semiconductor die. At least one pillar is coupled to the conductive pad. The pillar(s) have a non-uniform compliance geometry defining a compliant direction for each pillar.
According to another aspect of the disclosure, an apparatus includes a semiconductor die and a number of conductive pads disposed on a surface of the semiconductor die. A first pillar that has a first pillar geometry is coupled to one of the conductive pads at a first location on the semiconductor die. A second pillar has a second pillar geometry that is different from the first pillar geometry. The second pillar is coupled to a different one of the conductive pads at a second location on the semiconductor die.
Another aspect of the present disclosure provides a method for packaging a semiconductor die. The method includes fabricating a number of conductive pads on a surface of the semiconductor die. A first pillar that has a first pillar geometry is deposited on one of the conductive pads at a first location on the semiconductor die. A second pillar that has a second pillar geometry different from the first pillar geometry is deposited on a different one of the conductive pads at a second location on the semiconductor die.
Yet another aspect of the present disclosure provides an apparatus for packaging a semiconductor die. The apparatus includes means for fabricating conductive pads on a surface of the semiconductor die and means for depositing a first pillar that has a first pillar geometry on one of the conductive pads at a first location on the semiconductor die. The apparatus also includes means for depositing a second pillar that has a second pillar geometry different from the first pillar geometry on a different one of the conductive pads at a second location on the semiconductor die.
This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
The accompanying drawings are presented to aid in the description of embodiments. The drawings are provided solely for illustration of the embodiments and not limitation thereof.
Referring to
A conventional pillar has a symmetrical geometry and does include any particular directionality. For example, conventional pillars used in semiconductor packaging are substantially cylindrical and form an electrically conductive interconnect with the substrate through a solder on pad (SOP) connection. To reduce the susceptibility of the ELK layer to cracking and increase the robustness of the ELK layers, aspects of the present disclosure provide a directionally oriented pillar design on a semiconductor die or wafer. This reduces the stress on the ELK layers.
Referring to
Although the rectangular pillar 300 is compliant in two directions 302, 304, along the same line alternative aspects of the present disclosure provide pillars of different shapes which may have a single direction of maximum compliance or multiple different directions of maximum compliance. For example,
The mismatched thermal expansion of a die and substrate causes more relative displacement or the die and substrate in some areas of the die and less relative displacement in other areas of the die. For example, if the die is centered relative to the substrate, the central portion of the die may be subject to little or no displacement relative to the central portion of the substrate. In contrast the edges of a die may be subject to significant displacement relative to the edge portions of a substrate. These different relative displacements cause the stress on a pillar to vary as a function of location on the die.
In addition to orienting similarly shaped pillars as a function of their position on a die, aspects of the present disclosure also may include using differently shaped pillars as a function of their position on a die. For example, a pillar that is located near the center of a die and thereby subject to very little stress due to CTE mismatch may have a circular cross section having no particular direction of maximum compliance. On the same die, a pillar that is located near the edge may have a rectangular cross section to absorb large stresses due to CTE mismatch.
Another aspect of the present disclosure provides a method for depositing material to form pillars of various shapes on a semiconductor die. Referring to
The exemplary pattern 602 shown as a cross section in
Referring to
In
Although certain aspects of the present disclosure are described in terms of a copper pillar, it should be understood that other materials such as nickel, gold and silver may also be used to form pillars according various aspects of the disclosure.
Although the term “pillar” is used throughout the present disclosure to describe a particular structure for coupling a semiconductor die to a substrate, it should be understood that various other terms such as “post” and “bump,” for example, are commonly used for the same general type of structure. Although the term “interconnect” is used throughout the present disclosure, it should be understood that various other terms such as “connection” and “joint,” for example, to describe the same type of structure.
While exemplary embodiments incorporating the principles of the present disclosure have been disclosed hereinabove, the present disclosure is not limited to the disclosed embodiments. Instead, this application is intended to cover any variations, uses, or adaptations of the disclosure using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this disclosure pertains and which fall within the limits of the appended claims.
