Patent Grant
10418331
The present invention relates to integrated circuit device fabrication, and more particularly, to apparatus and methods for assembling integrated circuit elements on a substrate.
Large substrates with electronically active components distributed over the extent of the substrate are used in a variety of electronic systems, for example imaging devices such as flat-panel liquid crystal or OLED display devices and in digital radiographic plates. Large substrates with electrically active components are also found in flat-panel solar cells.
The electronically active components on flat-panel substrates are typically formed by sputtering a layer of inorganic semiconductor material or by spin-coating a layer of organic semiconductor material over the entire substrate and processing the layer to form electronic components. However, such coatings typically may have relatively poor electronic characteristics. Inorganic semiconductor materials can be processed to improve their electronic characteristics; for example, amorphous silicon can be heat-treated to form polycrystalline silicon. In other processes, microcrystalline semiconductor layers can be formed by using an underlying seeding layer. These methods typically improve the electron mobility of the semiconductor, but the performance of the resulting layer may still be worse than is often desired or needed.
The substrate and layer of semiconductor material can be photo-lithographically processed to define electronically active components, such as transistors. Such transistors are known as thin-film transistors (TFTs) since they are formed in a thin layer of semiconductor material, typically silicon. The photo-lithographic processing typically requires high-resolution mask steps to pattern the semiconductor materials and metal interconnections on the substrate. In these devices, the substrate is often made of glass, for example, Corning Eagle® or Jade® glass designed for display applications.
However, these conventional thin-film techniques may have limitations. Despite processing methods used to improve the performance of thin-film transistors, such transistors may have a performance lower than the performance of conventional integrated circuits formed in mono-crystalline semiconductor material. Also, semiconductor material and active components may be used on only portions of the substrate, leading to wasted material and increased material and processing costs. The substrate materials may be limited by the processing steps that may be necessary to process the semiconductor material, as well as the photo-lithographic steps used to pattern the active components. For example, plastic substrates have a limited chemical and heat tolerance and typically do not readily survive photo-lithographic processing. Furthermore, the manufacturing equipment used to process large substrates with thin-film circuitry may require relatively high resolution and may be expensive.
In another manufacturing technique, a mono-crystalline semiconductor wafer may be employed as the substrate. While this approach can provide substrates with similar performance as integrated circuits, the size of such substrates may be limited, for example, to a 12-inch diameter circle, and the wafers are relatively expensive compared to other substrate materials such as glass or polymer.
In yet another approach, thin layers of semiconductor may be bonded to a substrate and then processed. Such a method is known as semiconductor-on-glass or silicon-on-glass (SOG) and is described, for example, in U.S. Patent Application Publication No. 2008/0224254, published Sep. 18, 2008. If the semiconductor material is crystalline, high-performance thin-film circuits can be obtained. However, the bonding technique can be expensive and the high-resolution processing equipment needed to form thin-film active components on large substrates may be expensive.
It is also known to provide relatively large integrated circuits in surface mountable packages that are directly adhered to a substrate. However, these integrated circuits are relatively large and additional layers may not be easily formed over the integrated circuits. Furthermore, electrical inter-connections to the surface-mountable package may require high-resolution patterning.
Publication number 11-142878 of the Patent Abstracts of Japan entitled “Formation of Display Transistor Array Panel” describes etching a substrate to remove it from a thin-film transistor array on which the TFT array was formed. TFT circuits formed on a first substrate can be transferred to a second substrate by adhering the first substrate and the TFTs to the surface of the second substrate and then etching away the first substrate, leaving the TFTs bonded to the second substrate. This method typically requires etching a significant quantity of material and risks damaging the exposed TFT array. Also, as with the other techniques discussed above, the patterned processing may require expensive, high-resolution equipment.
Another method of locating material on a substrate is described in U.S. Pat. No. 7,127,810. In this method, a first substrate carries a thin-film object to be transferred to a second substrate. An adhesive is applied to the object to be transferred or to the second substrate in the desired location of the object. The substrates are aligned and brought into contact. A laser beam irradiates the object to abrade the transferring thin film so that the transferring thin film adheres to the second substrate. The first and second substrates are separated, peeling the film in the abraded areas from the first substrate and transferring it to the second substrate. In one embodiment, a plurality of objects may be selectively transferred by employing a plurality of laser beams to abrade selected areas. Objects to be transferred can include thin-film circuits. Further processing, for example to provide electrical interconnections between the transferred objects, may require high-resolution processing.
U.S. Pat. No. 6,969,624 describes a method of transferring a device from a first substrate onto a holding substrate by selectively irradiating an interface with an energy beam. The interface is located between a device for transfer and the first substrate and includes a material that generates ablation upon irradiation, thereby releasing the device from the substrate. For example, a light-emitting device (LED) can be made of a nitride semiconductor on a sapphire substrate. The energy beam is directed to the interface between the sapphire substrate and the LED nitride semiconductor releasing the LED and allowing the LED to adhere to a holding substrate coated with an adhesive. The adhesive is then cured. These methods, however, may require the patterned deposition of adhesive on the object(s) or on the second substrate. Moreover, the laser beam that irradiates the object may be shaped to match the shape of the object and the laser abrasion can damage the object to be transferred. Furthermore, the adhesive cure takes time, which may reduce the throughput of the manufacturing system. Further processing, for example to provide electrical interconnections between the transferred objects, may also require high-resolution processing.
In another method for transferring active components from one substrate to another, described in “AMOLED Displays using Transfer-Printed Integrated Circuits” published in the Proceedings of the 2009 Society for Information Display International Symposium Jun. 2-5, 2009, in San Antonio, Tex., US, vol. 40, Book 2, ISSN 0009-0966X, paper 63.2 p. 947, small integrated circuits (chiplets) with connection pads formed on the chiplet surface are formed in a wafer and released from the wafer by etching beneath the circuits. A PDMS stamp is pressed against the wafer and the circuits adhered to the stamp. The circuits are then pressed against a substrate coated with an adhesive, adhered to the substrate, and the adhesive is subsequently cured. Subsequent photo-lithographic processes are used to form electrical wires over the substrate and on to the connection pads. However, the position and orientation of the chiplets resulting from the printing process can vary somewhat. Thus, the connection pads may need to be relatively large so that the wires formed by the photo-lithographic processing steps contact the contact pads. The relatively large connection pads can reduce the space available for circuits and circuit connections, and thus can reduce the functionality of the chiplets.
According to some embodiments of the present invention, integrated circuit elements are provided on a receiving substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof, where the connection pad and the conductor element are electrically separated. At least one of the integrated circuit elements is misaligned on the receiving substrate relative to a desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad. A conductive layer is formed on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer.
In some embodiments, each of the integrated circuit elements may include an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate or isolate the conductor element from the conductive layer.
In some embodiments, a planarization layer may be formed on the receiving substrate including the integrated circuit elements thereon. The planarization layer may include via openings therein, where respective positions of the via openings in the planarization layer may be based on respective desired positions of the integrated circuit elements on the receiving substrate. The conductive layer may be formed on the planarization layer and in the via openings to electrically contact the connection pad of each of the integrated circuit elements.
In some embodiments, at least one of the via openings has a diameter or other dimension sufficient to expose a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit elements that is misaligned on the receiving substrate. For example, the dimension of the at least one of the via openings may be greater than the distance between the conductor element and the connection pad on the surface of the chiplet substrate.
In some embodiments, the connection pad of each of the integrated circuit elements may be coupled to an active element therein such that the conductive layer provides an electrical connection between respective active elements of each chiplet substrate, and the conductor element of each of the integrated circuit elements may provide an electrical connection between respective active elements of a same chiplet substrate.
In some embodiments, each chiplet substrate may include a plurality of connection pads and a plurality of conductor elements, and at least one of the conductor elements may be provided between adjacent ones of the connection pads on the surface of each chiplet substrate.
In some embodiments, the integrated circuit elements including a plurality of active elements therein may be formed on a source substrate. The integrated circuit elements may be transferred from the source substrate to the receiving substrate such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.
In some embodiments, the source substrate may include a sacrificial layer thereon between the integrated circuit elements and the source substrate. The integrated circuit elements may be transferred by separating the integrated circuit elements from one another on the source substrate to define tethers attaching the integrated circuit elements to respective anchor areas on the source substrate, and etching the sacrificial layer to release the integrated circuit elements from the source substrate without releasing the anchor areas therefrom.
In some embodiments, the integrated circuit elements may be transferred by pressing a stamp against the source substrate to break the tethers attaching the integrated circuit elements to the respective anchor areas, retracting the stamp from the source substrate such that the integrated circuit elements are adhered to the stamp, pressing the stamp including the integrated circuit elements thereon against the receiving substrate, and retracting the stamp from the receiving substrate to delaminate the integrated circuit elements therefrom and such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.
In some embodiments, a protective layer may be formed on the integrated circuit elements prior to separating and/or etching. The protective layer may include a silicon dioxide layer and an amorphous silicon layer thereon.
According to further embodiments of the present invention, an electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires.
In some embodiments, a planarization layer including via openings therein may be provided on the backplane substrate including the integrated circuit elements thereon. The conductive wires may respectively extend into the corresponding via openings to electrically contact the connection pad of each of the integrated circuit elements.
In some embodiments, respective positions of the via openings in the planarization layer may be based on respective desired positions of the integrated circuit elements on the backplane substrate. At least one of the via openings may expose a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit element that is misaligned on the receiving substrate.
In some embodiments, the exposed portion of the connection pad may be smaller than a dimension of the at least one via opening.
In some embodiments, an adhesive layer may be provided between each of the chiplet substrates and the backplane substrate. The adhesive layer adheres each of the chiplet substrates to the backplane substrate.
In some embodiments, the connection pad of each of the integrated circuit elements may be coupled to an active element therein, and the conductive wires may provide an electrical connection between respective active elements of each chiplet substrate. Also, in some embodiments, the conductor element of each of the integrated circuit elements may provide an electrical connection between respective active elements of a same chiplet substrate.
In some embodiments, each chiplet substrate may include a plurality of connection pads and a plurality of conductor elements on the surface thereof. At least one of the conductor elements may be provided between adjacent ones of the connection pads on the surface of each chiplet substrate.
In some embodiments, the integrated circuit elements may be transfer-printed elements.
In some embodiments, the conductor element and the connection pad on each chiplet substrate may be portions of a same metal layer.
According to still further embodiments of the present invention, a substrate for printing transferrable integrated circuit chiplets includes a patterned sacrificial layer on the substrate, and a plurality of integrated circuit chiplets on the patterned sacrificial layer. Each of the integrated circuit chiplets includes a separate chiplet substrate detached from the substrate by a pattern of the sacrificial layer, active elements on or in the chiplet substrate, a connection pad on a surface of the chiplet substrate, chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad on the surface of the chiplet substrate, where the conductor is electrically connected to a chiplet wire or one of the active elements, and an insulating layer on the chiplet substrate and the conductor, where the insulating layer leaves at least a portion of the connection pad exposed.
In some embodiments, one or more test pads, a plurality of electrically conductive tethers, and anchors may be provided on the substrate. Each anchor may be located over and in contact with the patterned sacrificial layer and having a tether connecting the anchor to one of the integrated circuit chiplets. The tether may electrically connect active elements in the one of the integrated circuit chiplets to one or more exposed electrical test pads in the anchor.
According to yet further embodiments of the present invention, a method of fabricating transferrable integrated circuit chiplets includes providing a substrate, forming a sacrificial layer on the substrate, forming a chiplet substrate layer on the sacrificial layer, forming active elements on or in the chiplet substrate layer, forming a connection pad on a surface of the chiplet substrate layer, forming chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, forming a conductor electrically separate from the connection pad on the surface of the chiplet substrate layer, where the conductor is electrically connected to a chiplet wire or active element, forming an insulating layer over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed, and patterning the chiplet substrate layer and the sacrificial layer to form separate chiplet substrates detached from the substrate.
In some embodiments, a protective layer may be formed on the insulating layer and the connection pad. The protective layer may be a bi-layer, and each layer of the bi-layer may include a different material. For example, the protective bi-layer may include a silicon dioxide layer and an amorphous silicon layer.
According to yet other embodiments of the present invention, a backplane includes a backplane substrate and a plurality of integrated circuits located on the backplane substrate. Each integrated circuit includes a separate chiplet substrate having a surface, active elements formed on or in the chiplet substrate, a connection pad formed on the surface of the chiplet substrate, chiplet wires formed on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the chiplet substrate, the conductor electrically connected to a chiplet wire or active element, and an insulating layer formed over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed. Electrically conductive wires are formed in a single layer over the backplane substrate, where the connection pad of each of the plurality of integrated circuits is connected to an electrically conductive wire.
According to still yet other embodiments of the present invention, a method of making a backplane having integrated circuits includes providing a backplane substrate, and providing a plurality of integrated circuits located on the backplane substrate. Each integrated circuit includes a separate chiplet substrate having a surface, active elements formed on or in the chiplet substrate, a connection pad formed on the surface of the chiplet substrate, chiplet wires formed on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the chiplet substrate and electrically connected to a chiplet wire or active element, and an insulating layer formed over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed. The integrated circuits are located on the backplane substrate, and electrically conductive wires are formed in a single layer over the backplane substrate. The connection pad of each of the plurality of integrated circuits is connected to an electrically conductive wire.
Other methods and/or devices according to some embodiments will become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above embodiments, be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
Embodiments of the present invention provide advantages such as improved electrical performance and density in integrated circuits transfer-printed over large substrates. Embodiments of the invention also reduce the number of large-area photolithographic steps, reduce alignment tolerance requirements, and are compatible with wafer testing and a high-yield release process for the transfer-printed integrated circuits.
The figures are not drawn to scale since the individual elements of the drawings have too great a size variation to permit depiction to scale.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the present specification and in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entireties.
Some embodiments of the present invention may be used in the fabrication of advanced display backplanes, for example, by assembling thousands of tiny integrated circuits onto glass substrates using transfer-printing. In particular, once circuits are printed onto a backplane or other target substrate, it may be necessary to form electrical interconnections. However, while the printing process may provide a high degree of accuracy, the chips may still be misplaced or misaligned on the order of 2-3 microns. Thus, interconnection processes may need to take such possible misalignment into consideration.
One interconnection approach towards addressing such misalignment is to form contact pads in the circuits that are large enough to account for both the transfer-printing accuracy and also the misalignment and size of the via to be formed down to the metal pad. In practice, such metal contact pads were relatively large, typically about 20 microns×20 microns in size.
In some embodiments of the present invention, a smaller contact pad can be formed in the circuit, for example, about 5 micrometers (μm)×5 μM, with a comparatively small via, for example, about 2 μm×2 μm, formed above the metal contact. As described in greater detail below, this process may be performed during the fabrication of the integrated circuit wafer, so the related design rules may be of reduced importance. Using the integrated-circuit vias according to some embodiments, the metal contact pad is reduced in size, and thus the design rules for the interconnection via to be formed on the large target substrate may be relaxed. Embodiments of the present invention may therefore provide improved electrical performance, fewer large-area photolithographic steps, improved yields, improved testability, increased density, and improved alignment tolerances for electrical circuit devices transferred from a source substrate to a destination substrate.
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The chiplet substrate 55 can be a semiconductor layer, for example silicon, GaAs, and/or other III-V compound semiconductors. The chiplet substrate 55 can be crystalline, amorphous, polycrystalline, or microcrystalline and can have multiple patterned or unpatterned layers of different materials, including electrically insulating layers such as some oxides and nitrides, e.g. silicon dioxide and silicon nitride. The active layer 54 can be a doped semiconductor or otherwise be processed to enable the formation of active elements 82, 83, 84. The active elements 82, 83, 84 can include electrical elements such as transistors, capacitors, resistors, and/or wires or electro-optical elements such as photo-sensors and/or light-emitting diodes, or both. The term “integrated circuit” may refer to a substrate that has been processed to form circuits integrated into a substrate, for example by photo-lithographic processes, to form optical, electrical, or electro-optic circuits that transform, process, and/or conduct electrical or optical energy. A “chiplet” can refer to a small integrated circuit, for example an integrated circuit that may be too small to be packaged and used in an electrical circuit using conventional pick-and place, surface mount, or flip-chip methods. For example, chiplets as described herein can have substrates that are 5-10 microns thick, 10-20 microns thick, 20-50 microns thick, or 50-100 microns thick. Chiplets can be 10-100 microns wide and 20-500 microns long, for example. The chiplets can have different sizes or areas, for example, 1000 square microns or 10,000 square microns, 100,000 square microns, or 1 square mm, or larger, and can have variable aspect ratios, for example 2:1, 5:1, or 10:1. Although embodiments of the present invention are described herein with reference to small chiplet integrated circuit devices, is the present invention is not limited thereto. Thus, the term “chiplet” should not be used for purposes of limitation, but may be used to distinguish integrated circuit elements of different sizes from one another.
The active elements described herein can be constructed in a source wafer using conventional photo-lithographic processes. The source wafer can be a crystalline semiconductor with very good electrical performance. The chiplet wires 80 can be made of metal, for example aluminum, in layers, for example metal layer 1, metal layer 2, metal layer 3, and so forth, as is done in the integrated circuit design and layout arts. The chiplet wires 80 in the various layers are used to electrically interconnect the active elements 82, 83, 84 to form electrical circuits. The top metal layer can be formed on the surface 58 of the chiplet substrate 55 to provide a connection pad 24 to which control or power signals external to the chiplet 20 can be electrically connected. The conductor 26 can be formed from a same layer and in a common processing step with the connection pad 24, for example a patterned metal layer. The conductor element 26 can be a metal interconnect such as a chiplet wire 80 or can be or include an active element 82, 83, 84 or a portion of an active element 82, 83, 84. The conductor 26 conducts or otherwise controls electrical current and is isolated from the connection pad 24 so that the conductor 26 and connection pads 24 are electrically separate and distinct. For example, the conductor 26 can be a connection pad separate from connection pad 24. A patterned insulating layer can be located in a layer beneath the conductors 26, 26′ and connection pad 24 and semiconductor layers in the active layer 54 to reduce and/or prevent unwanted electrical conduction.
The insulating layer 28 is located at least partly over the conductors 26, 26′ and connection pad 24 and is electrically insulating. The insulating layer 28 can be made of a variety of materials and perform multiple functions. The insulating layer 28 can be, for example a passivation or planarization layer and can comprise, for example, an oxide layer, a nitride layer, and/or a polymer layer, such as a resin (for example a curable resin). The insulating layer 28 does not necessarily cover the entire chiplet substrate 55, active layer 54, and conductors 26, 26′, but covers at least a portion of each of the chiplet substrate 55, active layer 54, and conductors 26, 26′.
The connection pad 24 can be formed of patterned metal, for example aluminum, silver, titanium, tungsten, metal alloys, and/or layers of metals. The connection pad 24 can be exposed through the insulating layer 28 by forming a via 32 through the insulating layer 28. Vias can be formed by coating a photo-curable resin over the surface, pattern-wise curing the resin to define the via, and then etching the resin and the insulating layer 28 beneath the resin to form the via 32 and removing the resin. Methods of coating photo-curable resins, pattern-wise exposing (e.g. with ultra-violet light though a mask) and pattern-etching the resin and layers beneath the resin to form vias are used in the art. Additionally or alternatively, the coated resin can form the insulating layer 28 and/or a portion thereof. Referring to
In the integrated circuit design arts, it is desirable to provide as much circuitry in an integrated circuit as possible, in light of increasing demands for device functionality. Large and complex circuits can be difficult to route by providing electrical wire connections between the various elements of the circuit. Hence, it is often helpful to have many layers of interconnections. As such, it may be desirable to reduce the size or surface area the connection pads 24 so that other areas of the surface 58 of the chiplet substrate 55 and active layer 54 can be used for routing wires to other active elements 82, 83, 84 with conductors 26 independently of the connection pad 24. To enable this, the conductor 26 is not directly electrically connected to the connection pad 24. As illustrated in
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In various embodiments of the present invention, the backplane of the present invention can be used, for example, to form an active-matrix backplane where the chiplets are organized into an array controlling a corresponding array of elements, for example pixels in a display or a digital radiographic plate. In another example, the chiplets can be light-emitters, for example light-emitting diodes or LEDs, or a vertical cavity side-emission laser (e.g. edge laser). In yet another example, the chiplets can serve to convert incident light into electricity, forming a photovoltaic device, for example with photo-diodes. In cases where it is desirable to collect or emit light efficiently, the contacts or any metal layers formed beneath the active layer can reflect incident light that passes through the active component back through the active component. In cases where a chiplet serves to convert light to electrical current, this reflection can allow for improved absorption of light by the chiplet. In the case where the chiplet emits light, or controls the emission of light by other layers, the reflection can provide improved emission of light.
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In some embodiments of the present invention, wafer-scale testing can be applied at this stage. While conventional testing probes could be applied to the chiplet structures shown in
In some embodiments of the present invention as shown in
Trenches 34 are formed, as shown in
In a further process, the bi-layer of
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The chiplets and the processes described herein can include additional layers and process steps. Furthermore, the process steps can be performed in various different orders, depending on the materials and process capabilities. For example, the insulating layer etch that exposes the connection pad (shown in
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The adhered chiplets 20 on the stamp 60 are pressed against a destination backplane 10 (
The protective layer (29 in
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The planarization layer 30 can comprise, for example, a curable resin, and can be patterned to form a via using photo-sensitive resins, masks, and light exposure through the masks. In embodiments illustrated in
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For clarity of illustration,
The present invention can provide a chiplet structure that is robust in the presence of manufacturing process faults that may create relative mis-alignments between features on a chiplet and features on the backplane, even when using relatively small features on the chiplet, e.g. the connection pad. The small features can provide additional space within the chiplets for active elements or wiring, thereby increasing the functionality of the chiplets an enabling improved electrical performance. Specifically, embodiments of the present invention can enable smaller connection pads that do not require as much space on a chiplet substrate surface. Therefore, chiplets can have a greater functionality or, alternatively, smaller chiplets can be employed. For example, in embodiments of the present invention, chiplet location tolerances of 10 microns can be used, whereas, conventional tolerances can be 5 microns, 2 microns, or 1 micron. Thus interconnection methods that have greater margins of error can be applied to transfer-printed substrates. Hence, embodiments of the present invention can provide higher manufacturing yields and lower costs in the presence of manufacturing variability and can employ lower-cost tools to manufacture backplanes.
Embodiments of the present invention can provide advantages of improved electrical performance and density in integrated circuits transfer-printed over large substrates. Aspects of the invention can also reduce the number of large-area photolithographic steps, reduce alignment tolerance requirements, and are compatible with wafer testing and high-yield release processes for the transfer-printed integrated circuits.
Some advantages of the present invention will now be described in greater detail with reference to
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In some embodiments, multiple connection pads 24 on a single chiplet 20 can be spaced apart from one another as far as is practical so that any mis-alignment between the chiplet 20 and backplane 10 will not result in short circuits between two connection pads 24 on the same chiplet 20. In particular, because each of the connection pads 24 will have an exposed portion, connection pads 24 that are too close together can be short circuited by wires 40. Therefore, in some embodiments, one or more of the conductors 26 may be arranged between adjacent connection pads 24 to separate the connection pads 24 so far as is practical.
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According to embodiments of the present invention illustrated in
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According to other embodiments of the present invention, a method of fabricating a structured substrate having transferrable integrated circuit chiplets includes the steps of providing a substrate, forming a sacrificial layer on the substrate, forming a chiplet substrate layer on the sacrificial layer, the chiplet substrate layer having a surface, forming active elements on or in the chiplet substrate layer, forming a connection pad on the surface, forming chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, forming a conductor electrically separate from the connection pad on the surface, the conductor electrically connected to a chiplet wire or active element, forming an insulating layer over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed, and patterning the chiplet substrate layer and the sacrificial layer to form separate chiplet substrates detached from the substrate.
In comparison to other thin-film manufacturing methods, using densely populated source substrates and transferring chiplets to a backplane substrate that requires only a sparse array of active components located thereon need not waste or require active layer material on a backplane substrate. Embodiments of the present invention can be used in transferring chiplets made with crystalline semiconductor materials that have much higher performance than thin-film active components. Furthermore, the flatness, smoothness, chemical stability, and heat stability requirements for a backplane substrate used in embodiments of the present invention can be greatly reduced because the adhesion and transfer process is not significantly limited by the backplane substrate material properties. Manufacturing and material costs can also reduced because of higher utilization rates of expensive materials (e.g. the active substrate) and reduced material and processing requirements for the backplane substrate. Embodiments of the present invention can also provide improved circuit density in small integrated circuits while reducing alignment and tolerance requirements for chiplets placed on a backplane. Thus, performance can be increased and costs can be reduced for active integrated circuits distributed over backplanes.
Furthermore, embodiments of the present invention can provide a reduction in masking steps on the backplane improving yields and reducing costs, can provide reduced connection pad size improving device functionality, and can provide less stringent tolerance requirements thereby improving yields and reducing processing costs.
The present invention has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. This application also incorporates the disclosure of U.S. Pat. No. 7,622,367, which is entitled Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements, by reference. The disclosures of U.S. patent application Ser. No. 12/732,868 entitled Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby, U.S. Provisional Patent Application No. 61/371,467 entitled Materials And Processes for Releasing Printable Compound Semiconductor Devices, U.S. Provisional Patent Application No. 61/318,508 entitled Selective Transfer of Active Components, and U.S. Provisional Patent Application No. 61/377,131 entitled Structures And Methods for Testing Printable Integrated Circuits are also incorporated by reference herein.
Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
In the specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. Hence, it is intended that the above embodiments and all of such variations and modifications be included within the scope and spirit of the invention as defined by the claims that follow.
This application is a division of U.S. patent application Ser. No. 13/302,497, entitled Interconnection Structures and Methods for Transfer-Printed Integrated Circuit Elements with Improved Interconnection Alignment Tolerance, filed on Nov. 22, 2011, which claims priority under 35 U.S.C. § 119(e) from U.S. Provisional Patent Application Ser. No. 61/416,527 entitled Interconnection Structure and Method for Transfer-Printed Integrated Circuits, filed with the United States Patent and Trademark Office on Nov. 23, 2010, the disclosure of which is incorporated by reference herein in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| 20180130751 A1 | May 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61416527 | Nov 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13302497 | Nov 2011 | US |
| Child | 15863164 | US |
