Claims
- 1. A method for mounting an electronic component, said method comprising:
placing said electronic component against a frame of a carrier, said electronic component having a plurality of elongate, resilient, electrical contact elements mounted on corresponding first electrical contact pads on said electronic component, said plurality of elongate, resilient, electrical contact elements extending beyond a surface of said carrier; securing said electronic component to said carrier; pressing said carrier against a first substrate having a plurality of second electrical contacts on a surface of said first substrate.
- 2. A method as in claim 1 wherein said electronic component is an integrated circuit (IC).
- 3. A method as in claim 2 wherein said method further comprises: mounting said plurality of elongate, resilient, electrical contact elements on said IC before placing said IC against said frame.
- 4. A method as in claim 3 further comprising:
singulating a wafer comprising said IC after mounting said plurality of elongate, resilient, electrical contact elements to IC's on said wafer.
- 5. A method as in claim 4 wherein each of said elongate, resilient, electrical contact elements is freestanding at least after just mounting said elongate, resilient, electrical contact elements to said IC.
- 6. A method as in claim 5 wherein said securing comprises placing a top on said carrier.
- 7. A method as in claim 5 wherein a dimension of said frame defines a maximum limit of compression for each of said elongate, resilient, electrical contact elements when said elongate, resilient, electrical contact elements are used to make electrical interconnections.
- 8. A method as in claim 7 wherein said elongate, resilient, electrical contact elements electrically interconnect said first electrical contact pads to corresponding ones of said second electrical contacts.
- 9. A method as in claim 7 wherein said first substrate is a testing circuit board for testing said IC.
- 10. A method as in claim 7 wherein said first substrate is a final package for using said IC.
- 11. A method as in claim 7 wherein said IC is placed against said frame without a package for said IC.
- 12. A method as in claim 6 wherein said top is substantially planar.
- 13. A method as in claim 6 wherein said top comprises an element which protrudes from a surface of said top and which is configured to press against a surface of said IC.
- 14. A method as in claim 7 wherein said elongate, resilient, electrical contact element is compressed less during testing of said IC than during use after testing.
- 15. A method as in claim 7 further comprising:
aligning automatically said carrier relative to said first substrate.
- 16. A method as in claim 15 wherein said carrier comprises a plurality of first elements and said first substrate comprises a plurality of second elements which are configured to uniquely mate with said plurality of first elements to automatically align said carrier relative to said first substrate.
- 17. A method as in claim 16 wherein said plurality of first elements protrude from said surface of said carrier, said surface facing said first substrate and wherein said plurality of second elements are receptors on said first substrate, said receptors for receiving said first elements.
- 18. A method as in claim 17 wherein said plurality of first elements protect said plurality of elongate, resilient, electrical contact elements when said carrier is not pressed against said first substrate.
- 19. A method as in claim 5 wherein said IC is secured in said carrier by:
securing a first side of said IC by a retainer which is coupled to said carrier; and wherein said frame secures a second side of said IC, said second side opposing said first side, said plurality of elongate, resilient, electrical contact elements mounted on said second side of said IC.
- 20. A method as in claim 19 wherein said retainer mechanically abuts at least a portion of said first side of said IC and said frame mechanically abuts at least a portion of said second side of said IC.
- 21. A method as in claim 20 wherein said retainer comprises at least one opening.
- 22. A method as in claim 21 further comprising:
marking an indicia on said IC through said at least one opening in said retainer after said IC is secured in said carrier.
- 23. A method as in claim 22 wherein said indicia represents information relating to a result of testing said IC.
- 24. A method as in claim 23 wherein said testing comprises burn-in testing of said IC.
- 25. A method as in claim 5 further comprising:
transferring heat from said IC to a heat transfer media on said carrier.
- 26. A method as in claim 20 wherein said retainer comprises openings for transferring heat from said IC.
- 27. A method as in claim 20 wherein said retainer comprises a probe for measuring a temperature of said IC.
- 28. A method as in claim 20 wherein said carrier is mounted against said first substrate and then said IC is placed against said frame, and said IC is then secured to said carrier.
- 29. A method as in claim 20 wherein said IC is placed against said frame and then said IC is secured to said carrier and then said carrier is pressed against said first substrate.
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of co-pending, commonly assigned U.S. patent application Ser. No. 09/205,502, filed Dec. 4, 1998, entitled “Socket for Mating with Electronic Component, Particularly Semiconductor Device with Spring Packaging for Fixturing, Testing, Burning-In.” That application is incorporated herein in full by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09205502 |
Dec 1998 |
US |
Child |
09260795 |
Mar 1999 |
US |