BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a cross-sectional diagram schematically showing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional diagram schematically showing a leadframe of the semiconductor device shown in FIG. 1;
FIG. 3 is a diagram for explaining a mounting process for a second semiconductor chip of the semiconductor device shown in FIG. 1;
FIG. 4 is a diagram for explaining a wire bonding process for the second semiconductor chip of the semiconductor device shown in FIG. 1;
FIG. 5 is a diagram for explaining a mounting process for a first semiconductor chip of the semiconductor device shown in FIG. 1;
FIG. 6 is a diagram for explaining a wire bonding process for the first semiconductor chip of the semiconductor device shown in FIG. 1;
FIG. 7 is a diagram for explaining a resin encapsulating process for the semiconductor device shown in FIG. 1;
FIGS. 8A and 8B are explanatory diagrams for comparing reverse wire bonding for the semiconductor device shown in FIG. 1 with normal bonding therefor;
FIG. 9 is a cross-sectional diagram of a conventional semiconductor device;
FIG. 10 is a cross-sectional diagram of the conventional semiconductor device; and
FIG. 11 is a cross-sectional diagram of the conventional semiconductor device.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that in each figure, the same components are denoted by the same reference numerals and appropriate explanations thereof will be omitted. In addition, in each figure described below, structures of portions that are not related to essential parts of the present invention are omitted.
FIG. 1 is a cross-sectional diagram schematically showing a semiconductor device according to the embodiment of the present invention. A semiconductor device 100 according to this embodiment includes: a leadframe 1 including an island portion 3 and a plurality of leads 5; a first semiconductor chip 20 which has a top surface 20a provided with a plurality of electrode pads 22 on a periphery thereof, and an under surface 20b provided on an opposite side of the top surface 20a, and which is mounted with a side of the top surface 20a being opposed to an under surface 3b of the island portion 3 of the leadframe 1; a second semiconductor chip 10 which has a top surface 10a provided with a plurality of electrode pads 12 on a periphery thereof, and an under surface 10b provided on a side opposite to the top surface 10a, and which is mounted with a side of the under surface 10b being opposed to a top surface 3a of the island portion 3 of the leadframe 1; a plurality of wires 30 each connecting an associated one of the lead and associated one of the electrode pads by reverse bonding, with a point on each lead 5 of the plurality of leads 5 of the leadframe 1 being a starting point, and with electrode pads 22 and 12 of one of the corresponding first semiconductor chip 20 and second semiconductor chip 10 being an ending point; and an encapsulation resin 40 for encapsulating the first semiconductor chip 20 and the second semiconductor chip 10. The wires 30 are connected such that each side surface of the wires 30 contacts one of the electrode pads substantially in parallel with each of the top surfaces 10a and 20a of the first semiconductor chip 20 and the second semiconductor chip 10.
The under surface 3b of the island portion 3 has a size smaller than the dimension of the first semiconductor chip 20 excluding the electrode pads 22 thereof, the first semiconductor chip 20 being mounted under the island portion 3. The island portion 3 of the leadframe 1 may have a thickness of about less than 80 μm to 25 μm. In this embodiment, the thickness of the island portion 3 is set to 75 μm. In addition, in this embodiment, the first semiconductor chip 20 and the second semiconductor chip 10 have the same shape.
Next, a method of manufacturing the semiconductor device 100 according to this embodiment will be described with reference to FIGS. 2 to 8. FIGS. 2 to 7 are cross-sectional diagrams each showing a process for manufacturing the semiconductor device 100 according to this embodiment. FIGS. 8A and 8B are explanatory diagrams for comparing reverse bonding for the semiconductor device 100 according to this embodiment with normal bonding therefor.
The method of manufacturing the semiconductor device 100 according to this embodiment includes the steps of: preparing the leadframe 1 having the island portion 3 and the plurality of leads 5 (FIG. 2); mounting the first semiconductor chip 20 having the top surface 20a provided with the plurality of electrode pads 22 on the periphery thereof, and the under surface 20b, with a side of the top surface 20a being opposed to the under surface 3b of the island portion 3 of the leadframe 1 (FIG. 3); mounting the second semiconductor chip 10 having the top surface 10a provided with the plurality of electrode pads 12 on the periphery thereof, and the under surface 10b, with a side of the under surface 10b being opposed to the top surface 3a of the island portion 3 of the leadframe 1 (FIG. 5); connecting wires 30 to each an associated one of the leads and associated one of the electrode pad by reverse bonding, with a point on each lead 5 of the plurality of leads 5 of the leadframe 1 being a starting point, and with the electrode pads 22 and 12 of the corresponding first semiconductor chip 20 and second semiconductor chip 10 being an ending point (FIGS. 4 and 6); and encapsulating the first semiconductor chip 20 and the second semiconductor chip 10 with the encapsulation resin 40 (FIG. 7). The wires 30 are connected such that each side surface of the wires 30 contacts each electrode pad substantially in parallel with each of the top surfaces 10a and 20a of the first semiconductor chip 20 and the second semiconductor chip 10.
Specifically, as shown in FIG. 2, the leadframe 1 is prepared as a preparation for an assembly of the semiconductor device 100. In the vicinity of the center of the leadframe 1, the island portion 3 is formed.
Next, as shown in FIG. 3, the first semiconductor chip 20 is mounted on the leadframe 1 by bonding the top surface 20a of the first semiconductor chip 20 to the under surface 3b of the island portion 3 of the leadframe 1 with an adhesive 7 for mounting. The leadframe 1 is fixed by using a jig (not shown), and the first semiconductor chip 20 is subjected to contact bonding from below by using a jig (not shown). At this time, the electrode pads 22 of the first semiconductor chip 20 are positioned to an outer side of the island portion 3 of the leadframe 1, and are disposed so that the electrode pads 22 and the island portion 3 do not overlap with each other.
Next, as shown in FIG. 4, the electrode pads 22 of the first semiconductor chip 20 corresponding to the leads 5 of the leadframe 1 are subjected to reverse wire bonding. The reverse bonding is disclosed in JP 11-097476 A (JP 2954109 B) filed by the applicant of this application. Specifically, a bump 32 serving as a golden ball is formed on the electrode pad 22 of the first semiconductor chip 20 by a bonder, the bump 32 serving as a golden ball is also formed on the corresponding lead 5. Then, reverse bonding is performed with a point on the lead 5 of the leadframe 1 being a starting point, and with each electrode pad 22 of the corresponding first semiconductor chip 20 being an ending point.
The wires 30 thus formed through reverse bonding are connected such that each side surface of the wires 30 contacts each electrode pad substantially in parallel with the top surface 20a of the first semiconductor chip 20. A loop height d1 of the wire 30 thus formed is reduced as shown in FIG. 8A. In a case of using the conventional normal bonding, as shown in FIG. 8B, the wire 30 rises and extends vertically from the electrode pad 22 of the first semiconductor chip 20, so a loop height d3 of the wire 30 is increased as compared to the loop height d1 of FIG. 8A.
In this embodiment, the loop height d1 of the wire 30 extending from the electrode pad 22 of the first semiconductor chip 20 is about less than 50 μm to 25 μm. In FIG. 4, the loop height d1 is 45 μm to 40 μm.
Next, as shown in FIG. 5, the second semiconductor chip 10 is mounted on the leadframe 1 by bonding the under surface 10b of the second semiconductor chip 10 to the top surface 3a of the island portion 3 of the leadframe 1 with the adhesive 7 for mounting. The second semiconductor chip 10 is mounted on the leadframe 1 from above by using a jig (not shown). At this time, the second semiconductor chip 10 is mounted at the center so that the wires 30 each connected to the first semiconductor chip 20 will not be in contact with the under surface 10b of the second semiconductor chip 10.
As shown in FIG. 8A, the loop height d1 of the wire 30 connected to the first semiconductor chip 20 is about less than 50 μm to 25 μm. Accordingly, when a distance d2 between the second semiconductor chip 10 and the first semiconductor chip 20 is about less than 80 μm to 25 μm of the thickness of the island portion 3, the wires 30 are not in contact with the under surface 10b of the second semiconductor chip 10. Therefore, it is unnecessary to provide a spacer 50 as shown in FIG. 8B.
Next, as shown in FIG. 6, the electrode pad 12 of the second semiconductor chip 10 corresponding to the lead 5 of the leadframe 1 is subjected to reverse bonding in the same manner as described above. Specifically, the bump 32 serving as a golden ball is formed on the electrode pad 12 of the second semiconductor chip 10 by a bonder, the bump 32 serving as a golden ball is also formed on the corresponding lead 5. Then, reverse bonding is performed with a point on the lead 5 of the leadframe 1 being a starting point, and the electrode pad 12 of the corresponding second semiconductor chip 10 being an ending point.
The loop height of the wire 30 thus formed by reverse bonding can be reduced as compared with the case of employing the conventional normal bonding, in the same manner as the loop height d1 of the first semiconductor chip 20.
Next, as shown in FIG. 7, the semiconductor chips are encapsulated with the plastic resin 40 by using a mold for encapsulating, to thereby obtain a predetermined shape. After that, the leads 5 are molded and made into a product. In this embodiment, it is unnecessary to provide the spacer, and the loop height of the wires 30 extending from the electrode pads 12 and 22 of the semiconductor chips 10 and 20 is also reduced. Accordingly, the distance between the second semiconductor chip 10 and the first semiconductor chip 20 is reduced, and the height of the mold for encapsulating can be reduced, which results in reduction in entire thickness of the semiconductor device 100.
As described above, according to the semiconductor device 100 of the embodiment of the present invention, and according to the method of manufacturing the same, by employment of reverse bonding, the height of the semiconductor device 100 can be reduced, thereby making it possible to mounting the plurality of semiconductor chips in compact on the leadframe. In addition, by eliminating the necessity of the spacer, the material costs for the spacer and the process for providing the spacer can be omitted, thereby reducing the manufacturing costs.
Further, in a conventional semiconductor device having a laminated structure, the semiconductor chip disposed above is formed with a shape smaller than that of the semiconductor chip disposed below so that the electrode pads of the lower semiconductor chip do not overlap the upper semiconductor chip. However, in the semiconductor device 100 according to this embodiment, it is unnecessary to form the upper semiconductor chip to be smaller than the lower semiconductor chip, and the second semiconductor chip 10 can be formed with the same shape as the first semiconductor chip 20. Further, irrespective of mounting the second semiconductor chip 10 and the first semiconductor chip 20 on both surfaces of the island portion 3 of the leadframe 1, it is possible to set directions in which the wires 30 are connected to the semiconductor chips to be the same directions. Accordingly, in the process for manufacturing the semiconductor device 100, it is unnecessary to place the second semiconductor chip 10 upside down to be bonded after the first semiconductor chip 20 is bonded to the leadframe 1, which simplifies the manufacturing process.
As described above, the embodiments of the present invention has been described with reference to the drawings. However, the embodiments are merely illustrative of the present invention, and various structures other than the above-mentioned structures can also be employed.
Patent Application
20080038872
