The present technology is directed generally to microelectronic devices with through-substrate interconnects and associated methods of manufacturing.
Semiconductor dies typically include a plurality of integrated circuits, bond-pads coupled to the integrated circuits, and metal routing layers for routing electrical signals between the bond-pads and external contacts. Fabricating and packaging such semiconductor dies include forming interconnects to electrically couple the bond-pads and/or metal routing layers to externally devices (e.g., a lead frame, a printed circuit board, etc.).
In some applications, the interconnects extend completely through or through a significant portion of the semiconductor dies (commonly referred to as “through-substrate interconnects”). One conventional process for forming through-substrate interconnects can include forming deep vias on the front and/or back side of a die in alignment with corresponding bond-pads. The vias are then filled with a conductive material (e.g., copper). Solder balls and/or other external electrical contacts are subsequently attached to the through-substrate interconnects.
The through-substrate interconnects may be formed (1) prior to integrating processing (commonly referred to as a “via-first” process), or (2) after the integration processing has been substantially completed (commonly referred to as a “via-last” process). However, both the via-first and via-last processes have certain drawbacks, as discussed in more detail later. Accordingly, several improvements to the process of through-substrate formation may be desirable.
Several embodiments of the present technology are described below with reference to processes for forming through vias and conductive routing layers in semiconductor substrates. Many details of certain embodiments are described below with reference to semiconductor dies. The term “semiconductor substrate” is used throughout to include a variety of articles of manufacture, including, for example, individual integrated circuit dies, imager dies, sensor dies, and/or dies having other semiconductor features.
Several of the processes described below may be used to form through vias and conductive routing layers in an individual die or in a plurality of dies, on a wafer or portion of a wafer. The wafer or wafer portion (e.g., wafer form) can include an unsingulated wafer or wafer portion, or a repopulated carrier wafer. The repopulated carrier wafer can include an adhesive material (e.g., a flexible adhesive) surrounded by a generally rigid frame having a perimeter shape that is comparable to that of an unsingulated wafer and can include singulated elements (e.g., dies) surrounded by the adhesive.
Many specific details of certain embodiments are set forth in
The semiconductor dies 102 can individually include a semiconductor substrate 106 carrying a signal routing structure 108 proximate to a first side 106a of the semiconductor substrate 106, a plurality of bond-pads 112 (identified individually as first to fifth bond-pads 112a-112e, respectively) on the signal routing structure 108, and a plurality of through-substrate interconnects 110 (identified individually as first to fourth interconnects 110a-110d, respectively) extending between the first side 106a and a second side 106b of the semiconductor substrate 106. The semiconductor dies 102 can also include an input/output (“I/O”) buffer 114 associated with the first through-substrate interconnect 110a and a chip-select (“C/S”) buffer 116 associated with the second, third, and fourth through-substrate interconnects 110b-110d.
The through-substrate interconnects 110 can be selectively connected to certain metallization layers (not shown in
The conductive couplers 104 can interface with corresponding bond-pads 112 based on a desired signal routing scheme. As shown in
In operation, the electrically coupled first through-substrate interconnect 110a of the semiconductor dies 102 forms an electrical path for carrying input/output signals to all the semiconductor dies 102. The signal routing structures 108 of the individual semiconductor dies 102 route the input/output signals to the individual I/O buffers 114 of the semiconductor dies 102 from the electrical path. The signal routing structure 108 can also route a chip-select signal (and/or other suitable signals) to a selected semiconductor die 102 to enable processing the input/output signals received at the I/O buffer 114 at a selected semiconductor die 102. For example, the signal routing structure 108 routes a chip-select signal received at the fifth bond-pad 112e to the C/S buffer 116 of the first semiconductor die 102a to enable the first semiconductor die 102a to process the received input/output signals. In another example, the signal routing structure 108 can also route a chip-select signal received at the fourth bond-pad 112d to the second semiconductor die 102b via the fourth through-substrate interconnect 110d of the first semiconductor die 102a.
In accordance with conventional techniques, the through-substrate interconnects 110 may be formed based on a via-first process or a via-last process. However, the inventors have recognized that both the via-first and via-last processes have certain drawbacks. For example, the via-last process may not adequately accommodate routing the chip-select signals because such modification may significantly add cost and/or complexity to the manufacturing process. For example, techniques that may be used to route signals at the last metallization layer can include (1) controlling the formation (or the lack of formation) of conductive bumps to an adjacent semiconductor die 102; (2) routing the signals back down to the lower metallization layers; (3) adding control gates (e.g., MOSFET) to the signal routing structure 108; (4) patterning each of the semiconductor dies 102 differently; and (5) adding a redistribution layer (not shown) on the semiconductor dies 102.
The inventors also recognized that the via-first process may negatively impact the electrical reliability of the semiconductor dies 102 because the electrical contacts between the signal routing structures 108 and integrated circuits (not shown) in the semiconductor dies 102 may be damaged during formation of the signal routing structures 108. Several embodiments of a process for addressing at least some of the foregoing drawbacks of the via-first and via-last processes are discussed below with reference to
As shown in
The process can include forming an insulator 124 on the semiconductor substrate 106. In the illustrated embodiment, the insulator 124 includes four layers of silicon oxide, silicon nitride, and/or other suitable dielectrics (identified individually as first to fourth insulation materials 124a-124d, respectively). In other embodiments, the insulator 124 can also include another desired number of dielectric and/or other suitable insulation materials. Techniques for forming the insulator 124 can include thermal oxidation, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), spin-on glass, and/or other suitable techniques.
The process can also include forming a conductive link 126 in the insulator 124 that is electrically connected to the integrated circuit 118. In one embodiment, forming the conductive link 126 includes patterning the insulator 124 with photolithography and/or other suitable techniques, and removing a portion of the patterned insulator 124 to form an aperture 127 via wet etching, dry etching, reactive ion etching, and/or other suitable techniques. The aperture 127 may then be filled with a conductive material 129 (e.g., copper, aluminum, gold, and/or other suitable conductive materials) via physical vapor deposition (PVD), CVD, ALD, electroplating, and/or other suitable techniques. In other embodiments, forming the conductive link 126 may include other processing operations in addition to or in lieu of the foregoing operations.
The process can include forming the first metallization layer 128a by forming a first dielectric 130 on the insulator 124, patterning the first dielectric 130 according to a desired metal routing profile, removing a portion of the first dielectric 130 to form trenches, channels, and/or other openings 135 in the first dielectric 130, and depositing a conductive material 137 (e.g., copper, aluminum, gold, and/or other suitable conductive materials) in the openings 135. The process can then include forming a first barrier 132 (e.g., BLOK provided by Applied Materials, Inc., Santa Clara, California) on the first metallization layer 128a and depositing a second dielectric 134 (e.g., silicon oxide) on the first barrier 132. The second dielectric 134 includes a first surface 134a proximate to the first barrier 132 and a second surface 134b opposite the first surface 134a.
After forming the first metallization layer 128a,
As shown in
As shown in
As shown in
As shown in
Even though the TSV module discussed above includes depositing and patterning the second photoresist 148, in certain embodiments, the second photoresist 148 may be omitted. Instead, the TSV module can include depositing the first conductive material 152 with the first portion 152a in the interconnect aperture 140 and the second portion 152b substantially covering the second surface 134b of the second dielectric 134. Subsequently, at least a part of the second portion 152b may be removed to yield the through-substrate interconnect 110 as shown in
Following the TSV module, the process can include forming a second metallization layer. As shown in
The process can then include depositing a third photoresist 158 on the third dielectric 156 and patterning the third photoresist 158 to form third openings 160 corresponding to a desired routing profile for a second metallization layer 128b (not shown). As shown in
As shown in
In one embodiment, the second conductive material 164 includes the same composition (e.g., copper) as the first conductive material 152. As a result, the first and second conductive materials 152 and 164 may be generally homogeneous (a phantom line is used in
After forming the second metallization layer 128b, the process can include forming additional metallization layers on the semiconductor substrate 106. For example,
The third metallization layer 128c can then be formed following operations generally similar to those described with reference to
In certain embodiments, the process can also include processing the semiconductor substrate 106 to form additional features in and/or on the semiconductor substrate 106. For example, as shown in
Even though only first, second and third metallization layers 128a, 128b, and 128c are illustrated in
Several embodiments of the foregoing process can reduce the risk of damaging the electrical connection between the first metallization layer 128a and the conductive link 126. The inventors have observed that forming the through-substrate interconnect 110 before forming the first metallization layer 128a can result in a defective electrical connection between the first metallization layer 128a and the conductive link 126. Without being bound by theory, it is believed that several operations during the formation of the first metallization layer 128a (e.g., deposition of the conductive material, removal of excess conductive material, etc.) may physically weaken and/or damage the electrical connection between the first metallization layer 128a and the conductive link 126. As a result, by forming the through-substrate interconnect 110 subsequent to forming the first metallization layer 128a, the risk of creating a defective electrical connection may be lowered.
Several embodiments of the foregoing process can also be more cost-effective and flexible when compared to conventional techniques. For example, the selection of electrical connection between the through-substrate interconnect 110 and the metallization layers may be postponed until later processing stages than the via-first process. As a result, the number of generic intermediate products (i.e., semiconductor dies with partially formed metallization layers) may be increased to enable a production manager to continue producing the semiconductor dies 102 before making a decision concerning the final connection configuration of the semiconductor dies 102.
Even though specific operations are discussed above with reference to
Unlike the embodiment shown in
As shown in
The process can then include depositing a photoresist 182 on the third dielectric 156 and patterning the photoresist 182 to form openings 184 corresponding to a desired routing profile for the second metallization layer 128b. As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
The process can then include depositing the aperture barrier 144 and the seed material 146 in the interconnect aperture 140, as discussed above with reference to
As shown in
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. Many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the technology is not limited except as by the appended claims.
This application is a continuation of U.S. patent application Ser. No. 16/902,115, filed Jun. 15, 2020, which is a divisional of U.S. patent application Ser. No. 14/563,953 filed Dec. 8, 2014, now U.S. Pat. No. 10,685,878, which is a divisional of U.S. patent application Ser. No. 12/701,800 filed Feb. 8, 2010, now U.S. Pat. No. 8,907,457, which are incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
5173442 | Carey | Dec 1992 | A |
6107186 | Erb | Aug 2000 | A |
6221769 | Dhong et al. | Apr 2001 | B1 |
6455425 | Besser et al. | Sep 2002 | B1 |
6582992 | Poo et al. | Jun 2003 | B2 |
6903443 | Farnworth et al. | Jun 2005 | B2 |
6962867 | Jackson et al. | Nov 2005 | B2 |
7091124 | Rigg et al. | Aug 2006 | B2 |
7111149 | Eilert | Sep 2006 | B2 |
7317256 | Williams et al. | Jan 2008 | B2 |
7449098 | Mayer et al. | Nov 2008 | B1 |
7745931 | Takao | Jun 2010 | B2 |
8039962 | Lee | Oct 2011 | B2 |
8278152 | Liu et al. | Oct 2012 | B2 |
8658529 | Idani | Feb 2014 | B2 |
20020064729 | Ching et al. | May 2002 | A1 |
20030113967 | Allman et al. | Jun 2003 | A1 |
20030234416 | Thomas et al. | Dec 2003 | A1 |
20040048459 | Patti | Mar 2004 | A1 |
20040121521 | Jackson et al. | Jun 2004 | A1 |
20050001326 | Masuda | Jan 2005 | A1 |
20050009333 | Lee et al. | Jan 2005 | A1 |
20050022491 | Zurn et al. | Feb 2005 | A1 |
20050029630 | Matsuo | Feb 2005 | A1 |
20050224921 | Gupta et al. | Oct 2005 | A1 |
20060046461 | Benson et al. | Mar 2006 | A1 |
20060246699 | Weidman et al. | Nov 2006 | A1 |
20060258111 | Jagueneau et al. | Nov 2006 | A1 |
20060270196 | Kirby | Nov 2006 | A1 |
20070048896 | Andry et al. | Mar 2007 | A1 |
20070063240 | Torres et al. | Mar 2007 | A1 |
20070178694 | Hiatt | Aug 2007 | A1 |
20080164573 | Basker et al. | Jul 2008 | A1 |
20080286900 | Jung | Nov 2008 | A1 |
20080299759 | Chatterjee et al. | Dec 2008 | A1 |
20080299762 | Mathew et al. | Dec 2008 | A1 |
20080318361 | Han et al. | Dec 2008 | A1 |
20090008790 | Lee | Jan 2009 | A1 |
20090020842 | Shiau | Jan 2009 | A1 |
20090051039 | Kuo | Feb 2009 | A1 |
20090091962 | Chung et al. | Apr 2009 | A1 |
20090124072 | Park | May 2009 | A1 |
20090127668 | Choi | May 2009 | A1 |
20090152602 | Akiyama | Jun 2009 | A1 |
20090160058 | Kuo et al. | Jun 2009 | A1 |
20090180257 | Lee et al. | Jul 2009 | A1 |
20090224405 | Chiou et al. | Sep 2009 | A1 |
20090239375 | Riess et al. | Sep 2009 | A1 |
20090278237 | Cooney et al. | Nov 2009 | A1 |
20090315154 | Kirby | Dec 2009 | A1 |
20100019390 | Jung | Jan 2010 | A1 |
20100140749 | Kuo | Jun 2010 | A1 |
20100178761 | Chen et al. | Jul 2010 | A1 |
20110193226 | Kirby et al. | Aug 2011 | A1 |
20120199970 | Yun et al. | Aug 2012 | A1 |
20200312714 | Kirby et al. | Oct 2020 | A1 |
Number | Date | Country |
---|---|---|
1686623 | Aug 2006 | EP |
11-251316 | Sep 1999 | JP |
20050073372 | Jul 2005 | KR |
200539244 | Dec 2005 | TW |
I245379 | Dec 2005 | TW |
200821636 | May 2008 | TW |
Entry |
---|
Office Action mailed Nov. 26, 2020 for European Application No. 11740230.5, 4 pages. |
“Extended European Search Report in European Application No. 11740230.5, mailed Mar. 9, 2015, 12 pages.”. |
“International Search Report and Written Opinion mailed Sep. 16, 2011 in International Application No. PCT/US2011/023150, 7 pages.”. |
“Kurita, Y et al., A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology, 2007 IEEE Electronic Components and Technology Conference, pp. 821-829, May 29-Jun. 1, 2007, ISBN 1-4244-0985-3.”. |
“Office Action mailed May 18, 2015 in China App. No. 201180014446.4, 22 pages.”. |
“Supplementary European Search Report mailed Nov. 13, 2014 in European App. No. 11740230.5, 5 pages.”. |
“U.S. Appl. No. 12/545,196, filed Aug. 21, 2009, to Kirby et al.”. |
European Patent Office, “Extended Search Report,” issued in connection with European Patent Application No. 23199195.1 dated Jun. 5, 2024 (10 pages). |
Number | Date | Country | |
---|---|---|---|
20220336273 A1 | Oct 2022 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14563953 | Dec 2014 | US |
Child | 16902115 | US | |
Parent | 12701800 | Feb 2010 | US |
Child | 14563953 | US |
Number | Date | Country | |
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Parent | 16902115 | Jun 2020 | US |
Child | 17850848 | US |