Information
-
Patent Grant
-
6465743
-
Patent Number
6,465,743
-
Date Filed
Monday, December 5, 199431 years ago
-
Date Issued
Tuesday, October 15, 200223 years ago
-
Inventors
-
Original Assignees
-
Examiners
Agents
-
CPC
- H01L21/481 - Insulating layers on insulating parts, with or without metallisation
- H01L23/13 - characterised by the shape
- H01L23/49816 - Spherical bumps on the substrate for external connection
- H01L24/97 - the devices being connected to a common substrate
- H05K3/0097 - Processing two or more printed circuits simultaneously
- H01L21/4846 - Leads on or in insulating or insulated substrates
- H01L24/48 - of an individual wire connector
- H01L24/73 - Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
- H01L2224/32225 - the item being non-metallic
- H01L2224/48091 - Arched
- H01L2224/48227 - connecting the wire to a bond pad of the item
- H01L2224/48465 - the other connecting portion not on the bonding area being a wedge bond
- H01L2224/73265 - Layer and wire connectors
- H01L2224/97 - the devices being connected to a common substrate
- H01L2924/00014 - the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
- H01L2924/01004 - Beryllium [Be]
- H01L2924/01006 - Carbon [C]
- H01L2924/01029 - Copper [Cu]
- H01L2924/01033 - Arsenic [As]
- H01L2924/01078 - Platinum [Pt]
- H01L2924/01079 - Gold [Au]
- H01L2924/01082 - Lead [Pb]
- H01L2924/01087 - Francium [Fr]
- H01L2924/12042 - LASER
- H01L2924/12044 - OLED
- H01L2924/14 - Integrated circuits
- H01L2924/15311 - being a ball array
- H01L2924/181 - Encapsulation
- H01L2924/3025 - Electromagnetic shielding
- H05K3/0052 - Depaneling
- H05K2201/09063 - Holes or slots in insulating substrate not used for electrical connections
- Y10T29/49126 - Assembling bases
- Y10T29/4913 - Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49222 - forming array of contacts or terminals
-
US Classifications
Field of Search
US
- 174 261
- 174 266
- 174 262
- 174 260
- 029 846
- 029 830
- 361 760
- 361 765
- 361 767
- 361 810
- 257 684
- 257 687
- 257 737
-
International Classifications
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Abstract
A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.
Description
BACKGROUND OF THE INVENTION
This invention relates, in general, to semiconductor packages, and more particularly, to ball-grid array semiconductor packaging.
Ball-grid array (BGA) semiconductor packages are well known in the electronics industry. BGA packages provide denser surface mount interconnects than quad flat pack (QFP) packages. Industry consensus is that BGA packages are more cost effective than QFP packages for input/output (I/O) requirements greater than 250. However, there is a great demand for cost effective BGA solutions down to 100 I/O.
During the assembly of a BGA package, an organic resin printed wiring board substrate having a thickness on the order of 0.35 millimeters (mm) is placed on a metal pallet or support device. The metal pallet provides support for the printed wiring board during the majority of assembly steps. The printed wiring board comprises a single BGA substrate or a single row or strand of a number of BGA substrates. The largest available single strand printed wiring board is a 1×6 printed wiring board with a maximum total length of about 200 mm. Next, a semiconductor die having a multitude of bonding pads is attached to a die pad located on the top side of the BGA substrate. Wire bonds are then attached to the bonding pads and to bond posts on the top side of the BGA substrate. Next, the semiconductor die and the wire bonds are encapsulated with an organic material. After encapsulation, the encapsulation material is cured at an elevated temperature. Conductive solder balls are then attached to contact pads, which are on the lower side of the BGA substrate and electrically coupled through conductive traces to the bond posts, using a solder reflow process. Each BGA package is then marked. When a single strand of multiple BGA packages is used, a singulation process such as a punch press is used to separate the multiple BGA packages into single units.
The above assembly process has several disadvantages. Because the above process requires a metal pallet to support the thin BGA substrates during the majority of assembly steps, the process is not conducive to large scale automated assembly. As a result, manufacturers must purchase additional equipment to assemble BGA packages. This requires capital investment in equipment and additional factory space. Also, because only single substrates or a single strand of a several substrates is used, it is difficult for manufacturers to produce a large volume of BGA packages efficiently. In addition, the above process requires significant labor inputs to load and unload the metal pallets or support devices at the various process steps. This negatively impacts manufacturing cycle time and quality. Furthermore, the pallets are expensive because they require precise tolerances for use with automated equipment and they require a manufacturer to carry a large inventory to support work-in-process (WIP) throughout a manufacturing line.
Industry standards require that after assembly, each BGA substrate must maintain a planarity variation of less than approximately 0.15 mm (approximately 6 mils) as measured at three points across a substrate. In other words, each BGA substrate must not be excessively warped or non-planar. Because of this strict standard and a concern over warpage, printed wiring board suppliers and BGA semiconductor manufacturers have not been motivated to expand beyond the existing 1×6 single strand printed wiring board.
With the rapid increase in demand for BGA packages, it is readily apparent that a need exists for cost effective printed wiring board substrates that are conducive to large scale automated assembly, that support existing automated assembly equipment, and that do not warp during the assembly process.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
illustrates a top view of an embodiment of a printed circuit board substrate for BGA assemblies according to the present invention; and
FIG. 2
illustrates an enlarged cross-sectional side view of one BGA assembly according to FIG.
1
.
DETAILED DESCRIPTION OF THE DRAWINGS
The present invention can be better understood with reference to
FIGS. 1 and 2
.
FIG. 1
illustrates a top view of multi-strand substrate, printed circuit board, or wiring board (PCB)
11
. PCB
11
typically comprises an organic epoxy-glass resin based material, such as bismaleimide-triazin (BT) resin, FR-4 board, or the like. PCB
11
includes BGA substrates or patterned package substrates
12
arranged in N rows
14
and M columns
16
to form an N by M pattern or array. Each of BGA substrates
12
includes a die attach or bonding pad
13
, which typically comprises copper or gold plated copper. Die attach pad
13
is a solid metallization area or a patterned metallization area shaped like a cross, “Union Jack”, or other specialized geometry. To avoid overcrowding the drawing, conductive traces are not shown (conductive traces are shown in FIG.
2
). PCB
11
is formed using well known printed circuit board manufacturing techniques.
To support efficient large scale automated assembly, N and M are preferably at least greater than or equal to 2. Depending on the final dimensions of BGA substrates
12
, N and M are selected such that after all assembly steps are completed, each of BGA substrates
12
exhibit a planarity variation of less than approximately 0.15 mm across each of BGA substrates
12
. In other words, during assembly, each of BGA substrates
12
does not warp to a non-planar condition in excess of approximately 0.15 mm. Also, PCB
11
has a thickness
26
(shown in
FIG. 2
) sufficient to minimize warpage or non-planarity. As stated below, thickness
26
preferably is on an order of at least 0.5 mm. According to standard industry practice, warpage within a given unit is determined by measuring a maximum difference between a seating plane (formed by the three conductive solder balls (see
FIG. 2
) having the greatest amount of standoff from the BGA substrate) and the conductive solder ball with the least amount of stand-off from the substrate. The warpage measurement is taken after PCB
11
is separated into individual BGA units.
Preferably, PCB
11
further includes a plurality of stress-relief slots or slots
19
at various locations on PCB
11
. Preferably, slots
19
extend through PCB
11
. Slots
19
are all the same size or of different sizes. Slots
19
further minimize warpage of each of BGA substrates
12
. Also, PCB
11
preferably includes alignment holes
21
along one side or both sides of PCB
11
. Alignment holes
21
extend from the top surface to the lower surface of PCB
11
. Alignment holes
21
are placed according to the requirements of die attaching and wire bonding equipment to support automated assembly. Additionally, PCB
11
preferably includes holes
22
around the perimeter of PCB
11
and hole
23
along one side of PCB
11
. Holes
22
provide for an automatic orientation feature so that a manufacturer does not insert PCB
11
into assembly equipment backwards or reversed. Hole
23
provides for an orientation feature to allow a manufacturer to robotically place PCB
11
in a jig apparatus.
In a preferred embodiment for a 27 mm by 27 mm BGA device, N is equal to 2 and M is equal to 6 with PCB
11
having a length
17
on an order of 187 mm and a width
18
on an order of 63 mm. The above specifications also are preferred for a 23 mm by 23 mm and a 25 mm by 25 mm BGA device. In a preferred embodiment for a 9 mm by 9 mm BGA device, N is equal to 4 and M is equal to 12 with length
17
on an order of 200 mm and width
18
on an order of 63 mm. In a preferred embodiment for a 10.4 mm by 10.4 mm BGA device, N is equal to 4 and M is equal to 12 with length
17
on an order of 212 mm and width
18
on an order of 63 mm. In a preferred embodiment for a 15 mm by 15 mm BGA device, N is equal to 3 and M is equal to 9 with length
17
on an order of 187 mm and width
18
on an order of 63 mm. In a preferred embodiment for a 14 mm by 22 mm BGA device, N is equal to 2 and M is equal to 9 with length
17
on an order of 187 mm and width
18
on an order of 63 mm. Optionally, for a 14 mm by 22 mm BGA device, N is equal to 3 and M is equal 6 with length
17
and width
18
the same as above. In a preferred embodiment for a 35 mm by 35 mm BGA device, N is equal to 1 and M is equal to 4 with length
17
on an order of 187 mm and width
18
on an order of 63 mm. The above dimensions are preferred to take advantage of standard automatic assembly equipment requirements. This allows a manufacturer to use existing tooling and equipment. The above dimensions are easily modified to meet the requirements of different types of automated assembly equipment.
FIG. 2
illustrates an enlarged cross-sectional view of one BGA structure, assembly, or package
22
after assembly but before singulation or separation into individual packages. BGA structure
22
comprises one of BGA substrates
12
within PCB
11
. PCB
11
with BGA substrates
12
preferably has a thickness
26
such that PCB
11
can undergo magazine-to-magazine automated assembly processes without using a metal support pallet. Currently available single BGA substrate PCB's and single strand BGA substrates PCB's have thicknesses on the order of 0.35 mm, which is too flimsy for reliable automated assembly unless pallets or carriers are used. Thickness
26
also is selected to minimize planarity variation of each of BGA substrates
12
. Preferably, thickness
26
is greater than approximately 0.5 mm. Preferably, thickness
26
is in a range from approximately 0.5 mm to approximately 0.8 mm.
BGA structure
22
further includes a semiconductor die
24
attached die attach pad
13
on an upper surface of each of BGA substrates
12
. Semiconductor die
24
has a plurality of bonding or bond pads
28
. Each of BGA substrates
12
has a conductive connective structure comprising bond posts
31
, upper conductive traces
32
, vias
33
, lower conductive traces
36
and contact pads
38
. Conductive solder balls
41
are attached to contact pads
38
. Conductive wires or wire bonds
43
electrically couple bond pads
28
to bond posts
31
. Alternatively, semiconductor die
24
is mounted in a “flip-chip” embodiment with bond pads
28
directly connected to bond posts directly below bond pads
28
, eliminating conductive wires
43
and die attach pad
13
. An encapsulating layer or encapsulant
46
covers semiconductor die
24
and wire bonds
43
to provide protection of active circuit elements from physical damage and/or corrosion.
A typical BGA assembly process incorporating PCB
11
having BGA substrates
12
to form BGA structure
22
is described as follows. First PCB
11
is provided having the desired N by M pattern. PCB
11
is loaded onto an automated die attach machine such as an ESEC 2006. This type of die attach machine is an industry standard machine that manufacturers use to attach semiconductor die to other types of semiconductor packages such as plastic dual-in-line (PDIP), small outline integrated circuit (SOIC), and QFP packages. The die attach machine automatically attaches one semiconductor die
24
to one of die attach pads
13
on PCB
11
. Preferably, semiconductor die
24
is attached to one of die attach pads
13
using a die attach epoxy.
After die attach, PCB
11
is then cleaned using an automated cleaning system such as an ULVAC cleaning system available from the ULVAC Corp. Next, PCB
11
is placed on an automated wire bonder such as a Shinkawa UTC-100 where wire bonds
43
are attached to bond pads
22
and bond posts
31
. In conventional BGA processing, wire bonding is done using a similar wirebonder configured for semi-automatic operation.
Next, encapsulant
46
is applied to cover semiconductor die
24
and wire bonds
43
. Encapsulant
46
comprises an organic material and is applied using an over-mold process or a glob-top process. For an over-mold process, automolds from Towa, Fico, or similar suppliers are used. When an over-molding process is used, encapsulant
46
preferably comprises an organic mold compound. When a glob-top process is used, encapsulant
46
preferably comprises an anhydride epoxy organic compound. Preferably, the material selected for encapsulant
46
has a thermal coefficient of expansion (TCE) close (within a few points or parts per million) to the TCE's of the material of PCB
11
and semiconductor die
24
. This further helps to minimize warpage of BGA substrates
12
during the remainder of the assembly process. Such encapsulents are available from several suppliers including The Dexter Corp., of Industry, Calif., Ciba-Giegy Corp., Hitachi Corp., Sumitomo Corp., and Nitto-Denko Corp.
Next, encapsulant
46
is cured preferably using a belt furnace, vertical oven, or batch oven at a temperature that is function of the type of material used for encapsulant
46
. For the curing process, a tray or some other form of protection preferably is used to protect contact pads
38
from foreign matter contamination.
After encapsulation, conductive solder balls
41
are attached to contact pads
38
using a room temperature attach process. Next, an automated solder reflow process is used to reflow conductive solder balls
41
. Automated reflow/equipment such as a belt furnace. After reflow, PCB
11
is again cleaned using automated cleaning equipment with an aqueous or terpene media to remove any corrosive flux residues from the conductive solder ball attachment process. Each BGA structure
22
is then marked on an automated marking machine such as an automated laser marker. Optionally , marking occurs immediately following encapsulation. Finally each of BGA substrates
12
is divided into individual packages. To divide the packages, a punch-press process is used. Optionally, a routing, dicing, or snapping separation process is used.
By now it should appreciated that there has been provided a multi-strand PCB containing an N by M array of BGA substrates for manufacturing BGA type semiconductor packages. N and M are selected and the thickness of the PCB is such so as to enable enhanced manufacturing efficiency. The enhanced manufacturing efficiency comes from the ability to manufacture more BGA packages from one multi-strand PCB and from the ability to use standard automated assembly equipment. Manufacturing efficiency is enhanced while still providing BGA substrate planarity variation less than approximately 0.15 mm. Because the multi-strand PCB according to the present invention enables the use of standard automated assembly equipment, a BGA manufacturer is able to use the same types of equipment to manufacture different types of packages thus reducing capital expenditures and needed factory floor space. Also, labor costs are reduced and quality is increased because of the reduced handling requirements.
Claims
- 1. A method for assembling ball-grid array (BGA) packages, comprising the steps of:providing a plurality of BGA substrates arranged in an N by M array within a printed circuit board having a thickness, wherein N and M are greater than or equal to 2, each of the plurality of BGA substrates having a plurality of bond posts on one side and a plurality of contact pads on an opposite side; attaching a semiconductor die to each of the plurality of BGA substrates, the semiconductor die having a plurality of bond pads; encapsulating the semiconductor die with an encapsulant; curing the encapsulant; attaching conductive solder balls to each of the plurality of contact pads; and dividing the N by M array into separate BGA packages, and wherein each of the separate BGA packages is substantially planar.
- 2. The method of claim 1 wherein the step of encapsulating the semiconductor die includes encapsulating with an encapsulant having a thermal coefficient of expansion close to that of the semiconductor die and the printed circuit board, and wherein size of the N by M array and the thickness are such that each of the plurality of BGA substrates maintains a planarity variation less than approximately 0.15 mm after assembly.
- 3. The method of claim 1 wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within a printed circuit board having a plurality of stress-relief slots at various locations within the printed circuit board.
- 4. The method of claim 1 wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within a printed circuit board having a thickness in a range from approximately 0.5 mm to approximately 0.8 mm.
- 5. The method of claim 1 wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within a printed circuit board having a width on an order of 63 mm.
- 6. The method of claim 1 wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within a printed circuit board having a length in a range from approximately 187 mm to 212 mm.
- 7. The method of claim 1 further comprising the steps of:bonding conductive wires to the plurality of bond pads and the plurality of bond posts after the step of attaching the semiconductor die; and marking the BGA packages after the step of encapsulating the semiconductor die.
- 8. The method of claim 1 wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within a printed circuit board comprises of an organic resin.
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A |
|
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|
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|
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|
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|
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