Patent Application
20240079358
The present technology is generally related to systems and methods for reducing die slippage in stacked semiconductor devices. In particular, the present technology relates to craters formed in bond pads to reduce die slippage.
Microelectronic devices, such as memory devices, microprocessors, and other electronics, typically include one or more semiconductor dies mounted on a substrate and encased in a protective covering. The semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. To meet continual demands on decreasing size, individual semiconductor dies and/or active components are typically manufactured in bulk and then stacked on a printed circuit board (PCB) or other substrates. The die stacks can make use of bond pads and/or metallization layers on each side of the semiconductor dies in the die stacks to form electrical connections. The die stacks are then heated to reflow solder structures between the bond pads. However, the electrical connections formed by the solder structures are dependent on alignment between the dies and the bond pads thereon.
The drawings have not necessarily been drawn to scale. Further, it will be understood that several of the drawings have been drawn partially schematically. Similarly, some components and/or operations can be separated into different blocks or combined into a single block for the purpose of discussing some of the implementations of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular implementations described.
Stacked semiconductor devices are typically formed by stacking each die in the die stack on a package substrate (or other suitable substrate) with corresponding pairs of bond pads having a solder structure positioned between them. For example, the solder structure can be a solder ball formed on one of the bond pads in the pair. The manufacturing process can then apply heat and/or a load to the die stack in a bonding process to reflow each of the solder structures to electrically, thermally, and/or physically couple the corresponding pairs of bond pads. To be successful, the die stack must be carefully aligned before the bonding process to ensure alignment between pairs of bond pads (sometimes also referred to herein as contact pads) when heat and compression are applied to the die stack. If the bond pads are not aligned, no joint will be formed when the solder structures are reflowed. The missing joint can undermine the structural and/or electrical integrity of the stacked semiconductor device. For example, if the third die in a ten-die stack is misaligned, each of the third-tenth dies may not be electrically coupled to the package substrate. As a result, the stacked semiconductor device will not have a usable performance rating. Problems with misalignment are exacerbated by die slippage. Die slippage occurs when forces in the die stack cause one or more of the dies to move laterally, undermining any previously established alignment. The forces can result from the expansion of the solder structures during the bonding process, compression applied to the die stack during the bonding process, and/or the weight of the dies in the die stack. Each source can cause the solder to move laterally, thereby causing the die slippage.
Stacked semiconductor devices, and related systems and methods, are disclosed herein to help address the problems discussed above. In some embodiments, the stacked semiconductor device includes a package substrate and a stack of semiconductor dies carried by the package substrate. The stack of semiconductor dies (“die stack”) can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die, and a solder structure (e.g., a reflowed solder ball) electrically coupled between the first and second semiconductor dies. For example, the first semiconductor die can have an upper surface and a first bond pad carried by the upper surface while the second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The solder structure can be electrically coupled between the first and second bond pads. To reduce the chance of die slippage (and thereby maintain alignment of the dies in the die stack), the first bond pad can include a depression formed in the uppermost surface of the first bond pad that interfaces with the solder structure such that the solder structure at least partially fills the depression. In some embodiments, the depression has a curvilinear, concave shape that generally matches the shape of the solder structure before a bonding process (e.g., matching the shape of a solder ball). In some embodiments, the depression has a stepped concave shape and/or a series of linear sloped walls that interface with solder structure. Further, in some embodiments, the depression is formed in the lowermost surface of the second bond pads instead of (or in addition to) the uppermost surface of the first bond pads.
The depression can reduce the chance of die slippage by increasing the contact area between the first bond pad and the solder structure relative to a planar contact area of a bond pad with an identical plan-form dimension and no depression formed thereon. In some embodiments, the depression increases the contact pressure (e.g., the pressure between two surfaces) between the first bond pad and the solder structure during a bonding process. The contact pressure helps resist movement between two surfaces due to the forces therebetween. Accordingly, by increasing the contact pressure, the depression reduces the chance that pressure from dies in the die stack (e.g., resulting from their load on the dies beneath them) and/or the expansion of the solder structure (and other conductive features in the die stack) will exceed the maximum contact pressure. Additionally, the depression can provide the solder structure with room to expand into that maintains contact with the bond pad, thereby reducing the chance that the expansion will cause die slippage.
In some embodiments, depression has a depth that is between 3 percent and 15 percent of the height of the solder structure before a bonding process. In some embodiments, the depression has a depth between 0.2 micrometers (μm) and 1.2 μm. In some embodiments, the depression has a depth below 0.2 μm. In some embodiments, the depression has a width (or diameter) that is between 5 percent and 25 percent of the diameter of the solder structure before the bonding process.
In some embodiments, the die stack includes additional semiconductor dies carried by the first and second semiconductor dies. In such embodiments, each of the semiconductor dies in the die stack be electrically and/or physically coupled through an interface that includes a lower bond pad (e.g., analogous to the first bond pad above) on a lower die, an upper bond pad (e.g., analogous to the second bond pad above) on an upper die, and a solder structure electrically and/or physically coupling the lower and upper bond pads. Further, each of the interfaces can include a depression formed in at least one of the lower and upper bond pads that is at least partially filled by the solder structure.
In some embodiments, the first semiconductor die is also electrically and/or physically coupled to the package substrate through an interface that includes two bond pads (e.g., one on the package substrate and one on the first semiconductor die) and a solder structure electrically and/or physically coupling the two bond pads. In such embodiments, at least one of the two bond pads (e.g., the bond pad on the package substrate) can include a depression formed thereon that interfaces with the solder structure to reduce the chance of die slippage between the package substrate and the first semiconductor die.
An example of a method for forming a stacked semiconductor device, in accordance with some embodiments of the present technology, includes, for each of N-number of semiconductor dies (e.g., one or more), forming a first bond pad with a depression on a first side of the semiconductor die; forming a second bond pad with on a second side of the semiconductor die opposite the first side; and forming a solder structure on the second bond pad. Once each of the N-number of semiconductor dies has been formed with the first and second bond pads, the method includes stacking the N-number of semiconductor dies along with a top semiconductor die (e.g., only having the second bond pads and a solder structure formed on each of the second bond pads) on a package substrate. In the stack, the first and second bond pads of corresponding pairs of semiconductor dies are aligned, with the solder structure at least partially filling the depression of the first bond pad in each of the corresponding pairs. The method can then include heating the stacked semiconductor dies in a bonding process to reflow (or at least partially reflow) the solder structures, thereby electrically and/or physically coupling the first and second bond pads of the corresponding pairs of semiconductor dies.
In some embodiments, forming the first bond pad with the depression includes depositing a photoresist mask on the first side of the semiconductor die, patterning the photoresist mask to create an opening with a central, non-patterned portion of the photoresist mask, and at least partially filling the opening with a conductive material. In some embodiments, the formation process also includes a repetitive process (e.g., with M-number of iterations) of re-patterning the photoresist mask to reduce the size of the central, non-patterned portion of the photoresist mask in the opening and at least partially filling the opening with a conductive material. In various embodiments, the repetitions can form a curvilinear depression, a stepped depression, a depression with various sloped sidewalls, and the like. In some embodiments, the reduction in the size of the central, non-patterned portion of the photoresist mask is controlled in each iteration to help shape the depression to match the solder structure (e.g., to match the outer surface of a solder ball). In some embodiments, the Mth iteration removes all of the non-patterned portion of the photoresist mask from the opening.
In some embodiments, forming the first bond pad with the depression includes depositing a conductive material on the first side of the semiconductor die to form the first bond pad, forming a photoresist mask over the first side of the semiconductor die and the first bond pad, patterning the photoresist mask to create an opening that exposes a portion of the first bond pad, and etching the conductive material in the first bond pad through the opening to form at least a portion of the depression. In various embodiments, the etching process can be perfectly isotropic (e.g., resulting in a curvilinear depression), perfectly anisotropic (e.g., resulting in vertical sidewalls), an imperfectly anisotropic wet etching process (e.g., resulting in sloped sidewalls), and the like. In some embodiments, the formation process includes any suitable number of additional iterations (e.g., one iteration, three iterations, five iterations, ten iterations, and/or any other suitable number) of patterning the photoresist material and etching the conductive material in the first bond pad through the patterned photoresist material.
As further illustrated in
During a manufacturing process, to enable the solder structures 130 to form the electrical and/or physical connections, the solder structures 130 can be formed on the second bond pads 126 of each of the dies (or on the first bond pads 124 of each of the dies). The core dies 122 and the top die 128 can then be stacked with the corresponding pairs of bond pads vertically aligned and the solder structures 130 positioned therebetween. The die stack 120 can then be heated and/or pressured in a bonding process to reflow the solder structures 130 and form a connection between the corresponding pairs of bond pads.
However, as further illustrated in
The inventors have realized that the interface 200 has a contact pressure resulting from the pressure between surfaces at the interface 200 (e.g., the pressure between the solder structure 130 and the upper surface 224). While the force the force along the force line F during the bonding process can result in deleterious effects (e.g., the solder structure 130 sliding longitudinally with respect to the first bond pad 124), the contact pressure can help resist the deleterious effects. In particular, the contact pressure helps the surfaces at the interface 200 grip each other. As a result, the higher the contact pressure (i.e., the higher the mutual pressure between the surfaces), the less chance there is of die slippage occurring. In a typical stacked semiconductor device, the maximum contact pressure (e.g., the highest value in contact pressure at the interface 200) is between about 420 megapascals (MPa) and about 460 MPa, or at about 444 MPa. Between increasing pressures from stacks of semiconductor dies, expansion of the solder structure 130 during a bonding process, and load applied to the die stack during the bonding process, the magnitude of the force along force line F typical at the interface 200 (or similar interfaces) is constantly increasing, thereby increasing the chance of die slippage and threatening to undermine the electrical and/or structural integrity of the resulting die stacks.
For example, as best illustrated in
In some embodiments, the arrangement of features on the first bond pad 324, solder structure 330, and the second bond pad 326 is inversed. That is, the solder structure 330 can be formed on the first bond pad 324 and the depression 340 can be formed into the second bond pad 326 to increase the maximum contact pressure of the interface. Further, although discussed primarily herein with reference to the interface between two dies in the die stack, the interface between the package substrate and a lowermost die in the die stack can also include bond pads with a depression formed thereon.
In the embodiment illustrated in
As discussed above, the inclusion of the depression 414 into the bond pad 410 increases the area of contact between the solder structure and the bond pad 410, which can thereby increase the maximum contact pressure for the corresponding interface. Purely by way of a specific, non-limiting example, the inventors measure that for a bond pad 410 with a thickness of about 5 μm and a depression 414 with a first depth Dp1 of about 2.5 the depression 414 increased the maximum contact pressure from about 444 MPa to about 616 MPa, on average. The resulting increase in the maximum contact pressure can reduce the chance of issue with die slippage during a stacking process and/or during a bonding process on the stacked dies.
In some embodiments, rather than maximizing the size of the interface surface based on the size of the bond pad and/or the solder structure, the size of the depression can be chosen to increase the contact area (e.g., relative to a bond pad with a planar contact area) between the bond pad and the solder structure as the solder structure expands (e.g., as it is heated in the bonding process). For example,
The smaller dimensions of the depression 424 can allow the depression 424 to conform to a distal tip of the solder structure during the stacking process, and to accept a distalmost portion of the solder structure without impeding the expansion of the solder structure during the bonding process. As a result, the depression 424 can significantly increase the contact area between the solder structure and the bond pad. Purely by way of a specific, non-limiting example, the inventors measure that for a bond pad 420 with a thickness of about 4 μm and a depression 424 with a first depth Dp2 of about 0.2 the depression 424 increased the maximum contact pressure from about 444 MPa to about 1416.5 MPa, on average. The resulting increase in the maximum contact pressure can reduce the chance of issues with die slippage during a stacking process and/or during a bonding process on the stacked dies.
As further illustrated in
In the illustrated embodiment, each of the first bond pads 524 on each of the core dies 522 includes a depression 540 formed thereon. In some embodiments, only a subset of the first bond pads 524 includes a depression 540. For example, half of the first bond pads 524 on each of the core dies 522 can include a depression 540. In various other examples, any suitable portion of the first bond pads 524 on each of the core dies 522 can include a depression 540 (e.g., a quarter, three-quarters, a third, two-thirds, etc.). In some embodiments, only a subset of the core dies 522 include first bond pads 524 with a depression 540 formed thereon. For example, the depression 540 can be limited to regions of the die stack 520 that are especially likely to slide (e.g., at the interface between an uppermost one of the core dies 522 and the top die 528). Further, in some embodiments, the solder structures 530 can be formed on the first bond pads 524 while the depression is formed into one or more of the second bond pads 526 (e.g., reversing the illustrated arrangement).
As illustrated in
As illustrated in
As illustrated in
The re-patterning and deposition processes can then be repeated until the bond pad is fully formed. For example, the photoresist material 640 can be repatterned to form new openings 642c, as illustrated in
In some embodiments, the repatterning processes can reduce the size of the photoresist material 640 at the center of the openings 642 by a non-constant amount to help create a depression in the bond pad that matches (or generally matches) the shape of the solder structure (e.g., the solder ball) that the bond pad will interface within a die stack. In some embodiments, the formation process can include a grinding or other removal process to help create a curvilinear shape and/or to help match the shape of the depression to the shape of the solder structure.
In some embodiments, the openings 642 in the photoresist material 640 are fully filled and the photoresist material 640 is replaced by a second photoresist material for each repetition of the process. For example, when the deposition process covers the photoresist material 640, the photoresist material 640 may need to be stripped entirely. In such embodiments, the formation process includes stripping the old photoresist material, depositing a new photoresist material, and patterning the new photoresist material in place of each of the repatterning processes discussed above.
As illustrated in
As illustrated in
In some embodiments, the etching process creates vertical, straight sidewalls to form a stepped depression 726 in the bond pad 724 (e.g., resulting from a perfectly anisotropic etching process). In some embodiments, the etching process creates linearly sloped sidewalls in the depression 726 (e.g., resulting from an imperfectly anisotropic wet etching process). In some embodiments, the etching process creates curvilinear sidewalls in the depression 726 (e.g., resulting from a perfectly isotropic etching process). In some embodiments, the formation process can also include a grinding process (or other processes) to help create a curvilinear shape and/or to help match the shape of the depression to the shape of the solder structure.
The resulting system 800 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system 800 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system 800 include lights, cameras, vehicles, etc. With regard to these and other examples, the system 800 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system 800 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. To the extent any material incorporated herein by reference conflicts with the present disclosure, the present disclosure controls. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Furthermore, as used herein, the phrase “and/or” as in “A and/or B” refers to A alone, B alone, and both A and B. Additionally, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or additional types of other features are not precluded. Further, the terms “approximately” and “about” are used herein to mean within at least within 10 percent of a given value or limit. Purely by way of example, an approximate ratio means within ten percent of the given ratio.
From the foregoing, it will also be appreciated that various modifications may be made without deviating from the disclosure or the technology. For example, one of ordinary skill in the art will understand that various components of the technology can be further divided into subcomponents, or that various components and functions of the technology may be combined and integrated. In addition, certain aspects of the technology described in the context of particular embodiments may also be combined or eliminated in other embodiments.
Furthermore, although advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
