This application is a Continuation of U.S. application Ser. No. 08/986,998, filed on Dec. 8, 1997 now U.S. Pat. No. 5,976,953, which is a Divisional Application of U.S. application Ser. No. 08/315,027, filed on Sep. 29, 1994, now U.S. Pat. No. 5,793,115 which is a Continuation-in-Part Application of U.S. application No. 08/130,033, filed on Sep. 30, 1993, now abandoned, the entire teachings of the above applications being incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
4612083 | Yasumoto et al. | Sep 1986 | A |
4649415 | Hebert | Mar 1987 | A |
4727047 | Bolzer et al. | Feb 1988 | A |
4748485 | Vasudev | May 1988 | A |
4818728 | Rai et al. | Apr 1989 | A |
4847146 | Yeh et al. | Jul 1989 | A |
4897708 | Clements | Jan 1990 | A |
4980034 | Volfson et al. | Dec 1990 | A |
5128737 | van der Have | Jul 1992 | A |
5138437 | Kumamoto et al. | Aug 1992 | A |
5202754 | Bertin et al. | Apr 1993 | A |
5206749 | Zavracky et al. | Apr 1993 | A |
5212778 | Dally et al. | May 1993 | A |
5256562 | Vu et al. | Oct 1993 | A |
5258325 | Spitzer et al. | Nov 1993 | A |
5280192 | Kryzaniwsky | Jan 1994 | A |
5300788 | Fan et al. | Apr 1994 | A |
5324980 | Kusunoki | Jun 1994 | A |
5347154 | Takahashi et al. | Sep 1994 | A |
5354695 | Leedy | Oct 1994 | A |
5373189 | Massit et al. | Dec 1994 | A |
5376561 | Vu et al. | Dec 1994 | A |
5407511 | Nakatani et al. | Apr 1995 | A |
5656548 | Zavracky et al. | Aug 1997 | A |
5793115 | Zavracky et al. | Aug 1998 | A |
5976953 | Zavracky et al. | Nov 1999 | A |
Number | Date | Country |
---|---|---|
468 080 | Mar 1968 | DE |
316 799 | May 1989 | EP |
0 474 474 | Mar 1992 | EP |
0 486 318 | May 1992 | EP |
0 486 829 | May 1992 | EP |
0 517 369 | Dec 1992 | EP |
4240762 | Aug 1992 | JP |
9213363 | Aug 1992 | WO |
9316491 | Aug 1993 | WO |
Entry |
---|
Yamazaki, et al., “4-Layer 3-D IC Technologies For Parallel Signal Processing” IDEM pp. 599-602 (1990). |
Kopin Corp., et al., “3D Circuits Formed By Film Transfer Techniques” DARPA BAA 92-18 Proposal PP. 1-50 (Jul. 31, 1992). |
Nishimura, et al., “Three Dimensional IC For High Performance Image Signal Processor” IEDM pp. 111-114 (1987). |
Sasaki, “Feasibility of 3D Integration” ETT 1(2):55-60 (Mar./Apr. 1990). |
Gotzlich, “Technology and Devices From Silicon Based Three-Dimensional Circuits” pp. 1-35 (1989). |
Neudeck, “Three-Dimensional CMOS Integration” Circuits and Devices pp. 32-38 (Sep. 1990). |
“Industry News” Micro-conductor Int'l one page (Dec. 1991). |
Kawasura, et al., “3-D High-Voltage CMOS ICS by Recrystallized SOI Merged With Bulk Control-Unit” IEDM pp. 758-761 (1987). |
Dunne, et al., “Materials and Devices Toward Three-Dimensional Integration” Microelec. Eng. 8 (1988) pp. 235-253. |
Ulf Kong, “Draft Designs For Multi-functional IC's Three Dimensional Integration” Elektroniker No. 10/1989; pp. 79-82 (with translation). |
Ernst Hofmeister, “Microelectronics 2000” Trends (1989); pp. 1-16 (with translation). |
R.W. Johnson, et al., “Multi-chip Modules—Systems Advantages, Major Constructions, and Materials Technologies,” IEEE Press, The Institute of Electrical and Electronics Engineers, Inc., pp. 150-155 (1991). |
Hayashi, et al., “A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual-CMOS Layers” IEDM pp. 657-660 (1990). |
Number | Date | Country | |
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Parent | 08/986998 | Dec 1997 | US |
Child | 09/430968 | US |
Number | Date | Country | |
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Parent | 08/130033 | Sep 1993 | US |
Child | 08/315027 | US |